From 6fb2eb6b4eb9027cf6ba893188987fcca049c295 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 24 Feb 2021 13:50:45 -0800 Subject: [PATCH] Remove unnecessary delays from testbenches --- tb/dma_client_axis_sink/test_dma_client_axis_sink.py | 3 --- tb/dma_if_pcie_us/test_dma_if_pcie_us.py | 3 --- tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py | 3 --- 3 files changed, 9 deletions(-) diff --git a/tb/dma_client_axis_sink/test_dma_client_axis_sink.py b/tb/dma_client_axis_sink/test_dma_client_axis_sink.py index cc94638a8..b8eb720c6 100644 --- a/tb/dma_client_axis_sink/test_dma_client_axis_sink.py +++ b/tb/dma_client_axis_sink/test_dma_client_axis_sink.py @@ -144,9 +144,6 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins assert int(status.tag) == cur_tag assert int(status.id) == cur_tag - for k in range(10): - await RisingEdge(dut.clk) - tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48)) if len(test_data) <= len(test_data2): diff --git a/tb/dma_if_pcie_us/test_dma_if_pcie_us.py b/tb/dma_if_pcie_us/test_dma_if_pcie_us.py index 7383a9e38..4222746bb 100644 --- a/tb/dma_if_pcie_us/test_dma_if_pcie_us.py +++ b/tb/dma_if_pcie_us/test_dma_if_pcie_us.py @@ -263,9 +263,6 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): assert int(status.tag) == cur_tag - for k in range(10): - await RisingEdge(dut.clk) - tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM ")) assert tb.dma_ram.read(ram_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8 diff --git a/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py b/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py index a49f69cae..92a6108fb 100644 --- a/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py +++ b/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py @@ -203,9 +203,6 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): assert int(status.tag) == cur_tag - for k in range(10): - await RisingEdge(dut.clk) - tb.log.debug("%s", tb.dma_ram.hexdump_str((ram_addr & ~0xf)-16, (((ram_addr & 0xf)+length-1) & ~0xf)+48, prefix="RAM ")) assert tb.dma_ram.read(ram_addr-8, len(test_data)+16) == b'\xaa'*8+test_data+b'\xaa'*8