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Add dedicated pipeline registers for RAM addresses that are not reset

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This commit is contained in:
Alex Forencich 2016-06-27 12:25:18 -07:00
parent 385c9cc90a
commit 6fe4a033e5
8 changed files with 64 additions and 16 deletions
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10
rtl/axis_async_fifo.v
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@ -63,8 +63,10 @@ module axis_async_fifo #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
@ -155,8 +157,10 @@ always @(posedge input_clk) begin
wr_ptr_gray_reg <= wr_ptr_gray_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -215,8 +219,10 @@ always @(posedge output_clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_async_fifo_64.v
View File

@ -66,8 +66,10 @@ module axis_async_fifo_64 #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
@ -158,8 +160,10 @@ always @(posedge input_clk) begin
wr_ptr_gray_reg <= wr_ptr_gray_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -218,8 +222,10 @@ always @(posedge output_clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_async_frame_fifo.v
View File

@ -74,8 +74,10 @@ module axis_async_frame_fifo #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
@ -237,8 +239,10 @@ always @(posedge input_clk) begin
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -331,8 +335,10 @@ always @(posedge output_clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_async_frame_fifo_64.v
View File

@ -77,8 +77,10 @@ module axis_async_frame_fifo_64 #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
@ -240,8 +242,10 @@ always @(posedge input_clk) begin
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -334,8 +338,10 @@ always @(posedge output_clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_fifo.v
View File

@ -58,7 +58,9 @@ module axis_fifo #
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
@ -106,8 +108,10 @@ always @(posedge clk) begin
wr_ptr_reg <= wr_ptr_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -141,8 +145,10 @@ always @(posedge clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_fifo_64.v
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@ -61,7 +61,9 @@ module axis_fifo_64 #
);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
@ -109,8 +111,10 @@ always @(posedge clk) begin
wr_ptr_reg <= wr_ptr_next;
end
wr_addr_reg <= wr_ptr_next;
if (write) begin
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -145,8 +149,10 @@ always @(posedge clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_frame_fifo.v
View File

@ -66,7 +66,9 @@ module axis_frame_fifo #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
@ -168,8 +170,10 @@ always @(posedge clk) begin
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -204,8 +208,10 @@ always @(posedge clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end

10
rtl/axis_frame_fifo_64.v
View File

@ -69,7 +69,9 @@ module axis_frame_fifo_64 #
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH+KEEP_WIDTH+1-1:0] mem_read_data_reg = {DATA_WIDTH+2{1'b0}};
@ -171,8 +173,10 @@ always @(posedge clk) begin
good_frame_reg <= good_frame_next;
end
wr_addr_reg <= wr_ptr_cur_next;
if (write) begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= mem_write_data;
end
end
@ -206,8 +210,10 @@ always @(posedge clk) begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
end
rd_addr_reg <= rd_ptr_next;
if (read) begin
mem_read_data_reg <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
end
end