From 70cc19ff152a9a2bc9f74f1b79ceabefb983c016 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 23 Jul 2023 22:24:42 -0700 Subject: [PATCH] Add MAC control layer to core 1G and 10G MAC modules Signed-off-by: Alex Forencich --- rtl/eth_mac_10g.v | 531 +++++++++++++++++++++++++++-- rtl/eth_mac_1g.v | 496 ++++++++++++++++++++++++++- syn/vivado/eth_mac.tcl | 46 +++ tb/eth_mac_10g/Makefile | 8 +- tb/eth_mac_10g/test_eth_mac_10g.py | 341 +++++++++++++++++- tb/eth_mac_1g/Makefile | 8 +- tb/eth_mac_1g/test_eth_mac_1g.py | 354 ++++++++++++++++++- 7 files changed, 1733 insertions(+), 51 deletions(-) create mode 100644 syn/vivado/eth_mac.tcl diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v index b9e89c9af..b34b91d2b 100644 --- a/rtl/eth_mac_10g.v +++ b/rtl/eth_mac_10g.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2015-2018 Alex Forencich +Copyright (c) 2015-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -49,7 +49,9 @@ module eth_mac_10g # parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter RX_PTP_TS_WIDTH = 96, parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, - parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1 + parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1, + parameter PFC_ENABLE = 0, + parameter PAUSE_ENABLE = PFC_ENABLE ) ( input wire rx_clk, @@ -93,6 +95,31 @@ module eth_mac_10g # output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag, output wire tx_axis_ptp_ts_valid, + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire tx_lfc_req, + input wire tx_lfc_resend, + input wire rx_lfc_en, + output wire rx_lfc_req, + input wire rx_lfc_ack, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire [7:0] tx_pfc_req, + input wire tx_pfc_resend, + input wire [7:0] rx_pfc_en, + output wire [7:0] rx_pfc_req, + input wire [7:0] rx_pfc_ack, + + /* + * Pause interface + */ + input wire tx_lfc_pause_en, + input wire tx_pause_req, + output wire tx_pause_ack, + /* * Status */ @@ -101,13 +128,65 @@ module eth_mac_10g # output wire [1:0] rx_start_packet, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, + output wire stat_tx_mcf, + output wire stat_rx_mcf, + output wire stat_tx_lfc_pkt, + output wire stat_tx_lfc_xon, + output wire stat_tx_lfc_xoff, + output wire stat_tx_lfc_paused, + output wire stat_tx_pfc_pkt, + output wire [7:0] stat_tx_pfc_xon, + output wire [7:0] stat_tx_pfc_xoff, + output wire [7:0] stat_tx_pfc_paused, + output wire stat_rx_lfc_pkt, + output wire stat_rx_lfc_xon, + output wire stat_rx_lfc_xoff, + output wire stat_rx_lfc_paused, + output wire stat_rx_pfc_pkt, + output wire [7:0] stat_rx_pfc_xon, + output wire [7:0] stat_rx_pfc_xoff, + output wire [7:0] stat_rx_pfc_paused, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay, + input wire [47:0] cfg_mcf_rx_eth_dst_mcast, + input wire cfg_mcf_rx_check_eth_dst_mcast, + input wire [47:0] cfg_mcf_rx_eth_dst_ucast, + input wire cfg_mcf_rx_check_eth_dst_ucast, + input wire [47:0] cfg_mcf_rx_eth_src, + input wire cfg_mcf_rx_check_eth_src, + input wire [15:0] cfg_mcf_rx_eth_type, + input wire [15:0] cfg_mcf_rx_opcode_lfc, + input wire cfg_mcf_rx_check_opcode_lfc, + input wire [15:0] cfg_mcf_rx_opcode_pfc, + input wire cfg_mcf_rx_check_opcode_pfc, + input wire cfg_mcf_rx_forward, + input wire cfg_mcf_rx_enable, + input wire [47:0] cfg_tx_lfc_eth_dst, + input wire [47:0] cfg_tx_lfc_eth_src, + input wire [15:0] cfg_tx_lfc_eth_type, + input wire [15:0] cfg_tx_lfc_opcode, + input wire cfg_tx_lfc_en, + input wire [15:0] cfg_tx_lfc_quanta, + input wire [15:0] cfg_tx_lfc_refresh, + input wire [47:0] cfg_tx_pfc_eth_dst, + input wire [47:0] cfg_tx_pfc_eth_src, + input wire [15:0] cfg_tx_pfc_eth_type, + input wire [15:0] cfg_tx_pfc_opcode, + input wire cfg_tx_pfc_en, + input wire [8*16-1:0] cfg_tx_pfc_quanta, + input wire [8*16-1:0] cfg_tx_pfc_refresh, + input wire [15:0] cfg_rx_lfc_opcode, + input wire cfg_rx_lfc_en, + input wire [15:0] cfg_rx_pfc_opcode, + input wire cfg_rx_pfc_en ); +parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE; +parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH; + // bus width assertions initial begin if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin @@ -121,6 +200,19 @@ initial begin end end +wire [DATA_WIDTH-1:0] tx_axis_tdata_int; +wire [KEEP_WIDTH-1:0] tx_axis_tkeep_int; +wire tx_axis_tvalid_int; +wire tx_axis_tready_int; +wire tx_axis_tlast_int; +wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int; + +wire [DATA_WIDTH-1:0] rx_axis_tdata_int; +wire [KEEP_WIDTH-1:0] rx_axis_tkeep_int; +wire rx_axis_tvalid_int; +wire rx_axis_tlast_int; +wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int; + generate if (DATA_WIDTH == 64) begin @@ -140,11 +232,11 @@ axis_xgmii_rx_inst ( .rst(rx_rst), .xgmii_rxd(xgmii_rxd), .xgmii_rxc(xgmii_rxc), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(rx_axis_tkeep), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tkeep(rx_axis_tkeep_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .start_packet(rx_start_packet), .error_bad_frame(rx_error_bad_frame), @@ -162,20 +254,20 @@ axis_xgmii_tx_64 #( .PTP_PERIOD_FNS(PTP_PERIOD_FNS), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), - .PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_xgmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(tx_axis_tkeep), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tkeep(tx_axis_tkeep_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), .ptp_ts(tx_ptp_ts), @@ -202,11 +294,11 @@ axis_xgmii_rx_inst ( .rst(rx_rst), .xgmii_rxd(xgmii_rxd), .xgmii_rxc(xgmii_rxc), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tkeep(rx_axis_tkeep), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tkeep(rx_axis_tkeep_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .start_packet(rx_start_packet[0]), .error_bad_frame(rx_error_bad_frame), @@ -224,20 +316,20 @@ axis_xgmii_tx_32 #( .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), - .PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_xgmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tkeep(tx_axis_tkeep), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tkeep(tx_axis_tkeep_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .xgmii_txd(xgmii_txd), .xgmii_txc(xgmii_txc), .ptp_ts(tx_ptp_ts), @@ -245,13 +337,392 @@ axis_xgmii_tx_inst ( .m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag), .m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid), .ifg_delay(ifg_delay), - .start_packet(tx_start_packet[0]) + .start_packet(tx_start_packet[0]), + .error_underflow(tx_error_underflow) ); assign tx_start_packet[1] = 1'b0; end +if (MAC_CTRL_ENABLE) begin : mac_ctrl + + localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2; + + wire tx_mcf_valid; + wire tx_mcf_ready; + wire [47:0] tx_mcf_eth_dst; + wire [47:0] tx_mcf_eth_src; + wire [15:0] tx_mcf_eth_type; + wire [15:0] tx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params; + + wire rx_mcf_valid; + wire [47:0] rx_mcf_eth_dst; + wire [47:0] rx_mcf_eth_src; + wire [15:0] rx_mcf_eth_type; + wire [15:0] rx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params; + + // terminate LFC pause requests from RX internally on TX side + wire tx_pause_req_int; + wire rx_lfc_ack_int; + + reg tx_lfc_req_sync_reg_1 = 1'b0; + reg tx_lfc_req_sync_reg_2 = 1'b0; + reg tx_lfc_req_sync_reg_3 = 1'b0; + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + tx_lfc_req_sync_reg_1 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_1 <= rx_lfc_req; + end + end + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_lfc_req_sync_reg_2 <= 1'b0; + tx_lfc_req_sync_reg_3 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1; + tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2; + end + end + + reg rx_lfc_ack_sync_reg_1 = 1'b0; + reg rx_lfc_ack_sync_reg_2 = 1'b0; + reg rx_lfc_ack_sync_reg_3 = 1'b0; + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + rx_lfc_ack_sync_reg_1 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0; + end + end + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_lfc_ack_sync_reg_2 <= 1'b0; + rx_lfc_ack_sync_reg_3 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1; + rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2; + end + end + + assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0); + + assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3; + + // handle PTP TS enable bit in tuser + wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in; + + if (TX_PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin + assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]}; + end else begin + assign tx_axis_tuser_in = tx_axis_tuser; + end + + mac_ctrl_tx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(TX_USER_WIDTH_INT), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(tx_axis_tdata), + .s_axis_tkeep(tx_axis_tkeep), + .s_axis_tvalid(tx_axis_tvalid), + .s_axis_tready(tx_axis_tready), + .s_axis_tlast(tx_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser_in), + + /* + * AXI stream output + */ + .m_axis_tdata(tx_axis_tdata_int), + .m_axis_tkeep(tx_axis_tkeep_int), + .m_axis_tvalid(tx_axis_tvalid_int), + .m_axis_tready(tx_axis_tready_int), + .m_axis_tlast(tx_axis_tlast_int), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_axis_tuser_int), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + .mcf_id(0), + .mcf_dest(0), + .mcf_user(0), + + /* + * Pause interface + */ + .tx_pause_req(tx_pause_req_int), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .stat_tx_mcf(stat_tx_mcf) + ); + + mac_ctrl_rx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(KEEP_WIDTH), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(RX_USER_WIDTH), + .USE_READY(0), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(rx_axis_tdata_int), + .s_axis_tkeep(rx_axis_tkeep_int), + .s_axis_tvalid(rx_axis_tvalid_int), + .s_axis_tready(), + .s_axis_tlast(rx_axis_tlast_int), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_axis_tuser_int), + + /* + * AXI stream output + */ + .m_axis_tdata(rx_axis_tdata), + .m_axis_tkeep(rx_axis_tkeep), + .m_axis_tvalid(rx_axis_tvalid), + .m_axis_tready(1'b1), + .m_axis_tlast(rx_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + .mcf_id(), + .mcf_dest(), + .mcf_user(), + + /* + * Configuration + */ + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_ENABLE), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + + /* + * Status + */ + .stat_rx_mcf(stat_rx_mcf) + ); + + mac_pause_ctrl_tx #( + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + + /* + * Configuration + */ + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_quanta_step((DATA_WIDTH*256)/512), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused) + ); + + mac_pause_ctrl_rx #( + .MCF_PARAMS_SIZE(18), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack_int), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Configuration + */ + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en), + .cfg_quanta_step((DATA_WIDTH*256)/512), + .cfg_quanta_clk_en(1'b1), + + /* + * Status + */ + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused) + ); + +end else begin + + assign tx_axis_tdata_int = tx_axis_tdata; + assign tx_axis_tkeep_int = tx_axis_tkeep; + assign tx_axis_tvalid_int = tx_axis_tvalid; + assign tx_axis_tready = tx_axis_tready_int; + assign tx_axis_tlast_int = tx_axis_tlast; + assign tx_axis_tuser_int = tx_axis_tuser; + + assign rx_axis_tdata = rx_axis_tdata_int; + assign rx_axis_tkeep = rx_axis_tkeep_int; + assign rx_axis_tvalid = rx_axis_tvalid_int; + assign rx_axis_tlast = rx_axis_tlast_int; + assign rx_axis_tuser = rx_axis_tuser_int; + + assign rx_lfc_req = 0; + assign rx_pfc_req = 0; + assign tx_pause_ack = 0; + + assign stat_tx_mcf = 0; + assign stat_rx_mcf = 0; + assign stat_tx_lfc_pkt = 0; + assign stat_tx_lfc_xon = 0; + assign stat_tx_lfc_xoff = 0; + assign stat_tx_lfc_paused = 0; + assign stat_tx_pfc_pkt = 0; + assign stat_tx_pfc_xon = 0; + assign stat_tx_pfc_xoff = 0; + assign stat_tx_pfc_paused = 0; + assign stat_rx_lfc_pkt = 0; + assign stat_rx_lfc_xon = 0; + assign stat_rx_lfc_xoff = 0; + assign stat_rx_lfc_paused = 0; + assign stat_rx_pfc_pkt = 0; + assign stat_rx_pfc_xon = 0; + assign stat_rx_pfc_xoff = 0; + assign stat_rx_pfc_paused = 0; + +end + endgenerate endmodule diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 27cd40b36..2f3c3605f 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2015-2018 Alex Forencich +Copyright (c) 2015-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -44,7 +44,9 @@ module eth_mac_1g # parameter RX_PTP_TS_ENABLE = TX_PTP_TS_ENABLE, parameter RX_PTP_TS_WIDTH = 96, parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, - parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1 + parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1, + parameter PFC_ENABLE = 0, + parameter PAUSE_ENABLE = PFC_ENABLE ) ( input wire rx_clk, @@ -88,6 +90,31 @@ module eth_mac_1g # output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag, output wire tx_axis_ptp_ts_valid, + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + input wire tx_lfc_req, + input wire tx_lfc_resend, + input wire rx_lfc_en, + output wire rx_lfc_req, + input wire rx_lfc_ack, + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + input wire [7:0] tx_pfc_req, + input wire tx_pfc_resend, + input wire [7:0] rx_pfc_en, + output wire [7:0] rx_pfc_req, + input wire [7:0] rx_pfc_ack, + + /* + * Pause interface + */ + input wire tx_lfc_pause_en, + input wire tx_pause_req, + output wire tx_pause_ack, + /* * Control */ @@ -104,13 +131,76 @@ module eth_mac_1g # output wire rx_start_packet, output wire rx_error_bad_frame, output wire rx_error_bad_fcs, + output wire stat_tx_mcf, + output wire stat_rx_mcf, + output wire stat_tx_lfc_pkt, + output wire stat_tx_lfc_xon, + output wire stat_tx_lfc_xoff, + output wire stat_tx_lfc_paused, + output wire stat_tx_pfc_pkt, + output wire [7:0] stat_tx_pfc_xon, + output wire [7:0] stat_tx_pfc_xoff, + output wire [7:0] stat_tx_pfc_paused, + output wire stat_rx_lfc_pkt, + output wire stat_rx_lfc_xon, + output wire stat_rx_lfc_xoff, + output wire stat_rx_lfc_paused, + output wire stat_rx_pfc_pkt, + output wire [7:0] stat_rx_pfc_xon, + output wire [7:0] stat_rx_pfc_xoff, + output wire [7:0] stat_rx_pfc_paused, /* * Configuration */ - input wire [7:0] ifg_delay + input wire [7:0] ifg_delay, + input wire [47:0] cfg_mcf_rx_eth_dst_mcast, + input wire cfg_mcf_rx_check_eth_dst_mcast, + input wire [47:0] cfg_mcf_rx_eth_dst_ucast, + input wire cfg_mcf_rx_check_eth_dst_ucast, + input wire [47:0] cfg_mcf_rx_eth_src, + input wire cfg_mcf_rx_check_eth_src, + input wire [15:0] cfg_mcf_rx_eth_type, + input wire [15:0] cfg_mcf_rx_opcode_lfc, + input wire cfg_mcf_rx_check_opcode_lfc, + input wire [15:0] cfg_mcf_rx_opcode_pfc, + input wire cfg_mcf_rx_check_opcode_pfc, + input wire cfg_mcf_rx_forward, + input wire cfg_mcf_rx_enable, + input wire [47:0] cfg_tx_lfc_eth_dst, + input wire [47:0] cfg_tx_lfc_eth_src, + input wire [15:0] cfg_tx_lfc_eth_type, + input wire [15:0] cfg_tx_lfc_opcode, + input wire cfg_tx_lfc_en, + input wire [15:0] cfg_tx_lfc_quanta, + input wire [15:0] cfg_tx_lfc_refresh, + input wire [47:0] cfg_tx_pfc_eth_dst, + input wire [47:0] cfg_tx_pfc_eth_src, + input wire [15:0] cfg_tx_pfc_eth_type, + input wire [15:0] cfg_tx_pfc_opcode, + input wire cfg_tx_pfc_en, + input wire [8*16-1:0] cfg_tx_pfc_quanta, + input wire [8*16-1:0] cfg_tx_pfc_refresh, + input wire [15:0] cfg_rx_lfc_opcode, + input wire cfg_rx_lfc_en, + input wire [15:0] cfg_rx_pfc_opcode, + input wire cfg_rx_pfc_en ); +parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE; +parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (TX_PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH; + +wire [DATA_WIDTH-1:0] tx_axis_tdata_int; +wire tx_axis_tvalid_int; +wire tx_axis_tready_int; +wire tx_axis_tlast_int; +wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_int; + +wire [DATA_WIDTH-1:0] rx_axis_tdata_int; +wire rx_axis_tvalid_int; +wire rx_axis_tlast_int; +wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int; + axis_gmii_rx #( .DATA_WIDTH(DATA_WIDTH), .PTP_TS_ENABLE(RX_PTP_TS_ENABLE), @@ -123,10 +213,10 @@ axis_gmii_rx_inst ( .gmii_rxd(gmii_rxd), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), - .m_axis_tdata(rx_axis_tdata), - .m_axis_tvalid(rx_axis_tvalid), - .m_axis_tlast(rx_axis_tlast), - .m_axis_tuser(rx_axis_tuser), + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tuser(rx_axis_tuser_int), .ptp_ts(rx_ptp_ts), .clk_enable(rx_clk_enable), .mii_select(rx_mii_select), @@ -141,19 +231,19 @@ axis_gmii_tx #( .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), .PTP_TS_ENABLE(TX_PTP_TS_ENABLE), .PTP_TS_WIDTH(TX_PTP_TS_WIDTH), - .PTP_TS_CTRL_IN_TUSER(TX_PTP_TS_CTRL_IN_TUSER), + .PTP_TS_CTRL_IN_TUSER(MAC_CTRL_ENABLE ? TX_PTP_TS_ENABLE : TX_PTP_TS_CTRL_IN_TUSER), .PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE), .PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH), - .USER_WIDTH(TX_USER_WIDTH) + .USER_WIDTH(TX_USER_WIDTH_INT) ) axis_gmii_tx_inst ( .clk(tx_clk), .rst(tx_rst), - .s_axis_tdata(tx_axis_tdata), - .s_axis_tvalid(tx_axis_tvalid), - .s_axis_tready(tx_axis_tready), - .s_axis_tlast(tx_axis_tlast), - .s_axis_tuser(tx_axis_tuser), + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tuser(tx_axis_tuser_int), .gmii_txd(gmii_txd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), @@ -168,6 +258,384 @@ axis_gmii_tx_inst ( .error_underflow(tx_error_underflow) ); +generate + +if (MAC_CTRL_ENABLE) begin : mac_ctrl + + localparam MCF_PARAMS_SIZE = PFC_ENABLE ? 18 : 2; + + wire tx_mcf_valid; + wire tx_mcf_ready; + wire [47:0] tx_mcf_eth_dst; + wire [47:0] tx_mcf_eth_src; + wire [15:0] tx_mcf_eth_type; + wire [15:0] tx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params; + + wire rx_mcf_valid; + wire [47:0] rx_mcf_eth_dst; + wire [47:0] rx_mcf_eth_src; + wire [15:0] rx_mcf_eth_type; + wire [15:0] rx_mcf_opcode; + wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params; + + // terminate LFC pause requests from RX internally on TX side + wire tx_pause_req_int; + wire rx_lfc_ack_int; + + reg tx_lfc_req_sync_reg_1 = 1'b0; + reg tx_lfc_req_sync_reg_2 = 1'b0; + reg tx_lfc_req_sync_reg_3 = 1'b0; + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + tx_lfc_req_sync_reg_1 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_1 <= rx_lfc_req; + end + end + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + tx_lfc_req_sync_reg_2 <= 1'b0; + tx_lfc_req_sync_reg_3 <= 1'b0; + end else begin + tx_lfc_req_sync_reg_2 <= tx_lfc_req_sync_reg_1; + tx_lfc_req_sync_reg_3 <= tx_lfc_req_sync_reg_2; + end + end + + reg rx_lfc_ack_sync_reg_1 = 1'b0; + reg rx_lfc_ack_sync_reg_2 = 1'b0; + reg rx_lfc_ack_sync_reg_3 = 1'b0; + + always @(posedge tx_clk or posedge tx_rst) begin + if (tx_rst) begin + rx_lfc_ack_sync_reg_1 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_1 <= tx_lfc_pause_en ? tx_pause_ack : 0; + end + end + + always @(posedge rx_clk or posedge rx_rst) begin + if (rx_rst) begin + rx_lfc_ack_sync_reg_2 <= 1'b0; + rx_lfc_ack_sync_reg_3 <= 1'b0; + end else begin + rx_lfc_ack_sync_reg_2 <= rx_lfc_ack_sync_reg_1; + rx_lfc_ack_sync_reg_3 <= rx_lfc_ack_sync_reg_2; + end + end + + assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en ? tx_lfc_req_sync_reg_3 : 0); + + assign rx_lfc_ack_int = rx_lfc_ack || rx_lfc_ack_sync_reg_3; + + // handle PTP TS enable bit in tuser + wire [TX_USER_WIDTH_INT-1:0] tx_axis_tuser_in; + + if (TX_PTP_TS_ENABLE && !TX_PTP_TS_CTRL_IN_TUSER) begin + assign tx_axis_tuser_in = {tx_axis_tuser[TX_USER_WIDTH-1:1], 1'b1, tx_axis_tuser[0]}; + end else begin + assign tx_axis_tuser_in = tx_axis_tuser; + end + + mac_ctrl_tx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(TX_USER_WIDTH_INT), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(tx_axis_tdata), + .s_axis_tkeep(1'b1), + .s_axis_tvalid(tx_axis_tvalid), + .s_axis_tready(tx_axis_tready), + .s_axis_tlast(tx_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(tx_axis_tuser_in), + + /* + * AXI stream output + */ + .m_axis_tdata(tx_axis_tdata_int), + .m_axis_tkeep(), + .m_axis_tvalid(tx_axis_tvalid_int), + .m_axis_tready(tx_axis_tready_int), + .m_axis_tlast(tx_axis_tlast_int), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_axis_tuser_int), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + .mcf_id(0), + .mcf_dest(0), + .mcf_user(0), + + /* + * Pause interface + */ + .tx_pause_req(tx_pause_req_int), + .tx_pause_ack(tx_pause_ack), + + /* + * Status + */ + .stat_tx_mcf(stat_tx_mcf) + ); + + mac_ctrl_rx #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(RX_USER_WIDTH), + .USE_READY(0), + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE) + ) + mac_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * AXI stream input + */ + .s_axis_tdata(rx_axis_tdata_int), + .s_axis_tkeep(1'b1), + .s_axis_tvalid(rx_axis_tvalid_int), + .s_axis_tready(), + .s_axis_tlast(rx_axis_tlast_int), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_axis_tuser_int), + + /* + * AXI stream output + */ + .m_axis_tdata(rx_axis_tdata), + .m_axis_tkeep(), + .m_axis_tvalid(rx_axis_tvalid), + .m_axis_tready(1'b1), + .m_axis_tlast(rx_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(rx_axis_tuser), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + .mcf_id(), + .mcf_dest(), + .mcf_user(), + + /* + * Configuration + */ + .cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast), + .cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast), + .cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast), + .cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast), + .cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src), + .cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src), + .cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type), + .cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc), + .cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc), + .cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc), + .cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc), + .cfg_mcf_rx_forward(cfg_mcf_rx_forward), + .cfg_mcf_rx_enable(cfg_mcf_rx_enable), + + /* + * Status + */ + .stat_rx_mcf(stat_rx_mcf) + ); + + mac_pause_ctrl_tx #( + .MCF_PARAMS_SIZE(MCF_PARAMS_SIZE), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(tx_mcf_valid), + .mcf_ready(tx_mcf_ready), + .mcf_eth_dst(tx_mcf_eth_dst), + .mcf_eth_src(tx_mcf_eth_src), + .mcf_eth_type(tx_mcf_eth_type), + .mcf_opcode(tx_mcf_opcode), + .mcf_params(tx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .tx_lfc_req(tx_lfc_req), + .tx_lfc_resend(tx_lfc_resend), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .tx_pfc_req(tx_pfc_req), + .tx_pfc_resend(tx_pfc_resend), + + /* + * Configuration + */ + .cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst), + .cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src), + .cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type), + .cfg_tx_lfc_opcode(cfg_tx_lfc_opcode), + .cfg_tx_lfc_en(cfg_tx_lfc_en), + .cfg_tx_lfc_quanta(cfg_tx_lfc_quanta), + .cfg_tx_lfc_refresh(cfg_tx_lfc_refresh), + .cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst), + .cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src), + .cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type), + .cfg_tx_pfc_opcode(cfg_tx_pfc_opcode), + .cfg_tx_pfc_en(cfg_tx_pfc_en), + .cfg_tx_pfc_quanta(cfg_tx_pfc_quanta), + .cfg_tx_pfc_refresh(cfg_tx_pfc_refresh), + .cfg_quanta_step(tx_mii_select ? (4*256)/512 : (8*256)/512), + .cfg_quanta_clk_en(tx_clk_enable), + + /* + * Status + */ + .stat_tx_lfc_pkt(stat_tx_lfc_pkt), + .stat_tx_lfc_xon(stat_tx_lfc_xon), + .stat_tx_lfc_xoff(stat_tx_lfc_xoff), + .stat_tx_lfc_paused(stat_tx_lfc_paused), + .stat_tx_pfc_pkt(stat_tx_pfc_pkt), + .stat_tx_pfc_xon(stat_tx_pfc_xon), + .stat_tx_pfc_xoff(stat_tx_pfc_xoff), + .stat_tx_pfc_paused(stat_tx_pfc_paused) + ); + + mac_pause_ctrl_rx #( + .MCF_PARAMS_SIZE(18), + .PFC_ENABLE(PFC_ENABLE) + ) + mac_pause_ctrl_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * MAC control frame interface + */ + .mcf_valid(rx_mcf_valid), + .mcf_eth_dst(rx_mcf_eth_dst), + .mcf_eth_src(rx_mcf_eth_src), + .mcf_eth_type(rx_mcf_eth_type), + .mcf_opcode(rx_mcf_opcode), + .mcf_params(rx_mcf_params), + + /* + * Pause (IEEE 802.3 annex 31B) + */ + .rx_lfc_en(rx_lfc_en), + .rx_lfc_req(rx_lfc_req), + .rx_lfc_ack(rx_lfc_ack_int), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D) + */ + .rx_pfc_en(rx_pfc_en), + .rx_pfc_req(rx_pfc_req), + .rx_pfc_ack(rx_pfc_ack), + + /* + * Configuration + */ + .cfg_rx_lfc_opcode(cfg_rx_lfc_opcode), + .cfg_rx_lfc_en(cfg_rx_lfc_en), + .cfg_rx_pfc_opcode(cfg_rx_pfc_opcode), + .cfg_rx_pfc_en(cfg_rx_pfc_en), + .cfg_quanta_step(rx_mii_select ? (4*256)/512 : (8*256)/512), + .cfg_quanta_clk_en(rx_clk_enable), + + /* + * Status + */ + .stat_rx_lfc_pkt(stat_rx_lfc_pkt), + .stat_rx_lfc_xon(stat_rx_lfc_xon), + .stat_rx_lfc_xoff(stat_rx_lfc_xoff), + .stat_rx_lfc_paused(stat_rx_lfc_paused), + .stat_rx_pfc_pkt(stat_rx_pfc_pkt), + .stat_rx_pfc_xon(stat_rx_pfc_xon), + .stat_rx_pfc_xoff(stat_rx_pfc_xoff), + .stat_rx_pfc_paused(stat_rx_pfc_paused) + ); + +end else begin + + assign tx_axis_tdata_int = tx_axis_tdata; + assign tx_axis_tvalid_int = tx_axis_tvalid; + assign tx_axis_tready = tx_axis_tready_int; + assign tx_axis_tlast_int = tx_axis_tlast; + assign tx_axis_tuser_int = tx_axis_tuser; + + assign rx_axis_tdata = rx_axis_tdata_int; + assign rx_axis_tvalid = rx_axis_tvalid_int; + assign rx_axis_tlast = rx_axis_tlast_int; + assign rx_axis_tuser = rx_axis_tuser_int; + + assign rx_lfc_req = 0; + assign rx_pfc_req = 0; + assign tx_pause_ack = 0; + + assign stat_tx_mcf = 0; + assign stat_rx_mcf = 0; + assign stat_tx_lfc_pkt = 0; + assign stat_tx_lfc_xon = 0; + assign stat_tx_lfc_xoff = 0; + assign stat_tx_lfc_paused = 0; + assign stat_tx_pfc_pkt = 0; + assign stat_tx_pfc_xon = 0; + assign stat_tx_pfc_xoff = 0; + assign stat_tx_pfc_paused = 0; + assign stat_rx_lfc_pkt = 0; + assign stat_rx_lfc_xon = 0; + assign stat_rx_lfc_xoff = 0; + assign stat_rx_lfc_paused = 0; + assign stat_rx_pfc_pkt = 0; + assign stat_rx_pfc_xon = 0; + assign stat_rx_pfc_xoff = 0; + assign stat_rx_pfc_paused = 0; + +end + +endgenerate + endmodule `resetall diff --git a/syn/vivado/eth_mac.tcl b/syn/vivado/eth_mac.tcl new file mode 100644 index 000000000..7605d1ab0 --- /dev/null +++ b/syn/vivado/eth_mac.tcl @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Ethernet MAC timing constraints + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == eth_mac_1g || REF_NAME == eth_mac_1g || \ + ORIG_REF_NAME == eth_mac_10g || REF_NAME == eth_mac_10g)}] { + puts "Inserting timing constraints for Ethernet MAC instance $inst" + + set sync_ffs [get_cells -quiet -hier -regexp ".*/mac_ctrl.tx_lfc_req_sync_reg_\[1234\]_reg" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/mac_ctrl.tx_lfc_req_sync_reg_1_reg/C]] + + set_max_delay -from [get_cells $inst/mac_ctrl.tx_lfc_req_sync_reg_1_reg] -to [get_cells $inst/mac_ctrl.tx_lfc_req_sync_reg_2_reg] -datapath_only [get_property -min PERIOD $src_clk] + } + + set sync_ffs [get_cells -quiet -hier -regexp ".*/mac_ctrl.rx_lfc_ack_sync_reg_\[1234\]_reg" -filter "PARENT == $inst"] + + if {[llength $sync_ffs]} { + set_property ASYNC_REG TRUE $sync_ffs + + set src_clk [get_clocks -of_objects [get_pins $inst/mac_ctrl.rx_lfc_ack_sync_reg_1_reg/C]] + + set_max_delay -from [get_cells $inst/mac_ctrl.rx_lfc_ack_sync_reg_1_reg] -to [get_cells $inst/mac_ctrl.rx_lfc_ack_sync_reg_2_reg] -datapath_only [get_property -min PERIOD $src_clk] + } +} diff --git a/tb/eth_mac_10g/Makefile b/tb/eth_mac_10g/Makefile index 1b22b8e9e..b7144265d 100644 --- a/tb/eth_mac_10g/Makefile +++ b/tb/eth_mac_10g/Makefile @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alex Forencich +# Copyright (c) 2020-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -34,6 +34,10 @@ VERILOG_SOURCES += ../../rtl/axis_xgmii_rx_32.v VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_32.v VERILOG_SOURCES += ../../rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_tx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters @@ -53,6 +57,8 @@ export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_RX_PTP_TS_WIDTH := 96 export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_RX_PTP_TS_WIDTH) + 1 )) +export PARAM_PFC_ENABLE := 1 +export PARAM_PAUSE_ENABLE := $(PARAM_PFC_ENABLE) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_10g/test_eth_mac_10g.py b/tb/eth_mac_10g/test_eth_mac_10g.py index 8cfe70d9f..f78e24dee 100644 --- a/tb/eth_mac_10g/test_eth_mac_10g.py +++ b/tb/eth_mac_10g/test_eth_mac_10g.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ -Copyright (c) 2020 Alex Forencich +Copyright (c) 2020-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -25,8 +25,11 @@ THE SOFTWARE. import itertools import logging +import struct import os +from scapy.layers.l2 import Ether + import pytest import cocotb_test.simulator @@ -72,6 +75,52 @@ class TB: self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) + dut.tx_lfc_req.setimmediatevalue(0) + dut.tx_lfc_resend.setimmediatevalue(0) + dut.rx_lfc_en.setimmediatevalue(0) + dut.rx_lfc_ack.setimmediatevalue(0) + + dut.tx_pfc_req.setimmediatevalue(0) + dut.tx_pfc_resend.setimmediatevalue(0) + dut.rx_pfc_en.setimmediatevalue(0) + dut.rx_pfc_ack.setimmediatevalue(0) + + dut.tx_lfc_pause_en.setimmediatevalue(0) + dut.tx_pause_req.setimmediatevalue(0) + + dut.ifg_delay.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_type.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_forward.setimmediatevalue(0) + dut.cfg_mcf_rx_enable.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_lfc_opcode.setimmediatevalue(0) + dut.cfg_tx_lfc_en.setimmediatevalue(0) + dut.cfg_tx_lfc_quanta.setimmediatevalue(0) + dut.cfg_tx_lfc_refresh.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_pfc_opcode.setimmediatevalue(0) + dut.cfg_tx_pfc_en.setimmediatevalue(0) + dut.cfg_tx_pfc_quanta.setimmediatevalue(0) + dut.cfg_tx_pfc_refresh.setimmediatevalue(0) + dut.cfg_rx_lfc_opcode.setimmediatevalue(0) + dut.cfg_rx_lfc_en.setimmediatevalue(0) + dut.cfg_rx_pfc_opcode.setimmediatevalue(0) + dut.cfg_rx_pfc_en.setimmediatevalue(0) + async def reset(self): self.dut.rx_rst.setimmediatevalue(0) self.dut.tx_rst.setimmediatevalue(0) @@ -240,6 +289,280 @@ async def run_test_tx_alignment(dut, payload_data=None, ifg=12): await RisingEdge(dut.tx_clk) +async def run_test_lfc(dut, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 1 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while not dut.rx_lfc_req.value.integer: + await RisingEdge(dut.tx_clk) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_lfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.xgmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_lfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_lfc_cnt == 4 + + assert tb.axis_sink.empty() + assert tb.xgmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_pfc(dut, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + + await tb.reset() + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + dut.rx_pfc_en.value = 0xff + dut.rx_pfc_ack.value = 0x00 + + dut.tx_lfc_pause_en.value = 0 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 512 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = XgmiiFrame.from_payload(bytes(test_pkt)) + await tb.xgmii_source.send(test_frame) + + for i in range(8): + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0xff >> (7-i) + + for k in range(200): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0x00 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_pfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.xgmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_pfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_pfc_cnt == 9 + + assert tb.axis_sink.empty() + assert tb.xgmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + def size_list(): return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 @@ -267,6 +590,12 @@ if cocotb.SIM_NAME: factory.add_option("ifg", [12]) factory.generate_tests() + if cocotb.top.PFC_ENABLE.value: + for test in [run_test_lfc, run_test_pfc]: + factory = TestFactory(test) + factory.add_option("ifg", [12]) + factory.generate_tests() + # cocotb-test @@ -276,9 +605,9 @@ lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -@pytest.mark.parametrize("enable_dic", [1, 0]) +@pytest.mark.parametrize(("enable_dic", "pfc_en"), [(1, 1), (1, 0), (0, 0)]) @pytest.mark.parametrize("data_width", [32, 64]) -def test_eth_mac_10g(request, data_width, enable_dic): +def test_eth_mac_10g(request, data_width, enable_dic, pfc_en): dut = "eth_mac_10g" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -289,6 +618,10 @@ def test_eth_mac_10g(request, data_width, enable_dic): os.path.join(rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(rtl_dir, "axis_xgmii_tx_32.v"), os.path.join(rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(rtl_dir, "mac_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_ctrl_tx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(rtl_dir, "lfsr.v"), ] @@ -311,6 +644,8 @@ def test_eth_mac_10g(request, data_width, enable_dic): parameters['RX_PTP_TS_WIDTH'] = 96 parameters['TX_USER_WIDTH'] = ((parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 + parameters['PFC_ENABLE'] = pfc_en + parameters['PAUSE_ENABLE'] = parameters['PFC_ENABLE'] extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/tb/eth_mac_1g/Makefile b/tb/eth_mac_1g/Makefile index cf7a54693..b3475f7cd 100644 --- a/tb/eth_mac_1g/Makefile +++ b/tb/eth_mac_1g/Makefile @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alex Forencich +# Copyright (c) 2020-2023 Alex Forencich # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal @@ -32,6 +32,10 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/axis_gmii_rx.v VERILOG_SOURCES += ../../rtl/axis_gmii_tx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_ctrl_tx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_rx.v +VERILOG_SOURCES += ../../rtl/mac_pause_ctrl_tx.v VERILOG_SOURCES += ../../rtl/lfsr.v # module parameters @@ -47,6 +51,8 @@ export PARAM_RX_PTP_TS_ENABLE := $(PARAM_TX_PTP_TS_ENABLE) export PARAM_RX_PTP_TS_WIDTH := 96 export PARAM_TX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_TX_PTP_TS_ENABLE)),1,$(shell expr $(if $(filter-out 1,$(PARAM_TX_PTP_TAG_ENABLE)),0,$(PARAM_TX_PTP_TAG_WIDTH)) + $(if $(filter-out 1,$(TX_PTP_TS_CTRL_IN_TUSER)),0,1) + 1 )) export PARAM_RX_USER_WIDTH := $(if $(filter-out 1,$(PARAM_RX_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_TX_PTP_TS_WIDTH) + 1 )) +export PARAM_PFC_ENABLE := 1 +export PARAM_PAUSE_ENABLE := $(PARAM_PFC_ENABLE) ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/tb/eth_mac_1g/test_eth_mac_1g.py b/tb/eth_mac_1g/test_eth_mac_1g.py index 9cc24913f..63ca1f32e 100644 --- a/tb/eth_mac_1g/test_eth_mac_1g.py +++ b/tb/eth_mac_1g/test_eth_mac_1g.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ -Copyright (c) 2020 Alex Forencich +Copyright (c) 2020-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -25,8 +25,12 @@ THE SOFTWARE. import itertools import logging +import struct import os +from scapy.layers.l2 import Ether + +import pytest import cocotb_test.simulator import cocotb @@ -73,11 +77,56 @@ class TB: self.tx_ptp_clock = PtpClockSimTime(ts_64=dut.tx_ptp_ts, clock=dut.tx_clk) self.tx_ptp_ts_sink = PtpTsSink(PtpTsBus.from_prefix(dut, "tx_axis_ptp"), dut.tx_clk, dut.tx_rst) + dut.tx_lfc_req.setimmediatevalue(0) + dut.tx_lfc_resend.setimmediatevalue(0) + dut.rx_lfc_en.setimmediatevalue(0) + dut.rx_lfc_ack.setimmediatevalue(0) + + dut.tx_pfc_req.setimmediatevalue(0) + dut.tx_pfc_resend.setimmediatevalue(0) + dut.rx_pfc_en.setimmediatevalue(0) + dut.rx_pfc_ack.setimmediatevalue(0) + + dut.tx_lfc_pause_en.setimmediatevalue(0) + dut.tx_pause_req.setimmediatevalue(0) + dut.rx_clk_enable.setimmediatevalue(1) dut.tx_clk_enable.setimmediatevalue(1) dut.rx_mii_select.setimmediatevalue(0) dut.tx_mii_select.setimmediatevalue(0) + dut.ifg_delay.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_mcast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_dst_ucast.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_check_eth_src.setimmediatevalue(0) + dut.cfg_mcf_rx_eth_type.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_lfc.setimmediatevalue(0) + dut.cfg_mcf_rx_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_check_opcode_pfc.setimmediatevalue(0) + dut.cfg_mcf_rx_forward.setimmediatevalue(0) + dut.cfg_mcf_rx_enable.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_lfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_lfc_opcode.setimmediatevalue(0) + dut.cfg_tx_lfc_en.setimmediatevalue(0) + dut.cfg_tx_lfc_quanta.setimmediatevalue(0) + dut.cfg_tx_lfc_refresh.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_dst.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_src.setimmediatevalue(0) + dut.cfg_tx_pfc_eth_type.setimmediatevalue(0) + dut.cfg_tx_pfc_opcode.setimmediatevalue(0) + dut.cfg_tx_pfc_en.setimmediatevalue(0) + dut.cfg_tx_pfc_quanta.setimmediatevalue(0) + dut.cfg_tx_pfc_refresh.setimmediatevalue(0) + dut.cfg_rx_lfc_opcode.setimmediatevalue(0) + dut.cfg_rx_lfc_en.setimmediatevalue(0) + dut.cfg_rx_pfc_opcode.setimmediatevalue(0) + dut.cfg_rx_pfc_en.setimmediatevalue(0) async def reset(self): self.dut.rx_rst.setimmediatevalue(0) @@ -217,6 +266,292 @@ async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12, enab await RisingEdge(dut.tx_clk) +async def run_test_lfc(dut, ifg=12, enable_gen=None, mii_sel=True): + + tb = TB(dut) + + tb.gmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + tb.dut.rx_mii_select.value = mii_sel + tb.dut.tx_mii_select.value = mii_sel + + if enable_gen is not None: + tb.set_enable_generator_rx(enable_gen()) + tb.set_enable_generator_tx(enable_gen()) + + await tb.reset() + + dut.tx_lfc_req.value = 0 + dut.tx_lfc_resend.value = 0 + dut.rx_lfc_en.value = 1 + dut.rx_lfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 1 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_lfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_lfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_lfc_eth_type.value = 0x8808 + dut.cfg_tx_lfc_opcode.value = 0x0001 + dut.cfg_tx_lfc_en.value = 1 + dut.cfg_tx_lfc_quanta.value = 0xFFFF + dut.cfg_tx_lfc_refresh.value = 0x7F00 + + dut.cfg_rx_lfc_opcode.value = 0x0001 + dut.cfg_rx_lfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 128 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH', 0x0001, 100) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while not dut.rx_lfc_req.value.integer: + await RisingEdge(dut.tx_clk) + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 1 + + for k in range(1000): + await RisingEdge(dut.tx_clk) + + dut.tx_lfc_req.value = 0 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_lfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.gmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_lfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_lfc_cnt == 4 + + assert tb.axis_sink.empty() + assert tb.gmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_pfc(dut, ifg=12, enable_gen=None, mii_sel=True): + + tb = TB(dut) + + tb.gmii_source.ifg = ifg + tb.dut.ifg_delay.value = ifg + tb.dut.rx_mii_select.value = mii_sel + tb.dut.tx_mii_select.value = mii_sel + + if enable_gen is not None: + tb.set_enable_generator_rx(enable_gen()) + tb.set_enable_generator_tx(enable_gen()) + + await tb.reset() + + dut.tx_pfc_req.value = 0x00 + dut.tx_pfc_resend.value = 0 + dut.rx_pfc_en.value = 0xff + dut.rx_pfc_ack.value = 0 + + dut.tx_lfc_pause_en.value = 0 + dut.tx_pause_req.value = 0 + + dut.cfg_mcf_rx_eth_dst_mcast.value = 0x0180C2000001 + dut.cfg_mcf_rx_check_eth_dst_mcast.value = 1 + dut.cfg_mcf_rx_eth_dst_ucast.value = 0xDAD1D2D3D4D5 + dut.cfg_mcf_rx_check_eth_dst_ucast.value = 0 + dut.cfg_mcf_rx_eth_src.value = 0x5A5152535455 + dut.cfg_mcf_rx_check_eth_src.value = 0 + dut.cfg_mcf_rx_eth_type.value = 0x8808 + dut.cfg_mcf_rx_opcode_lfc.value = 0x0001 + dut.cfg_mcf_rx_check_opcode_lfc.value = 1 + dut.cfg_mcf_rx_opcode_pfc.value = 0x0101 + dut.cfg_mcf_rx_check_opcode_pfc.value = 1 + + dut.cfg_mcf_rx_forward.value = 0 + dut.cfg_mcf_rx_enable.value = 1 + + dut.cfg_tx_pfc_eth_dst.value = 0x0180C2000001 + dut.cfg_tx_pfc_eth_src.value = 0x5A5152535455 + dut.cfg_tx_pfc_eth_type.value = 0x8808 + dut.cfg_tx_pfc_opcode.value = 0x0101 + dut.cfg_tx_pfc_en.value = 1 + dut.cfg_tx_pfc_quanta.value = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + dut.cfg_tx_pfc_refresh.value = 0x7F007F007F007F007F007F007F007F00 + + dut.cfg_rx_pfc_opcode.value = 0x0101 + dut.cfg_rx_pfc_en.value = 1 + + test_tx_pkts = [] + test_rx_pkts = [] + + for k in range(32): + length = 128 + payload = bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5', type=0x8000) + test_pkt = eth / payload + test_tx_pkts.append(test_pkt.copy()) + + await tb.axis_source.send(bytes(test_pkt)) + + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='5A:51:52:53:54:55', type=0x8000) + test_pkt = eth / payload + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + if k == 16: + eth = Ether(src='DA:D1:D2:D3:D4:D5', dst='01:80:C2:00:00:01', type=0x8808) + test_pkt = eth / struct.pack('!HH8H', 0x0101, 0x00FF, 10, 20, 30, 40, 50, 60, 70, 80) + test_rx_pkts.append(test_pkt.copy()) + + test_frame = GmiiFrame.from_payload(bytes(test_pkt)) + await tb.gmii_source.send(test_frame) + + for i in range(8): + for k in range(500): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0xff >> (7-i) + + for k in range(500): + await RisingEdge(dut.tx_clk) + + dut.tx_pfc_req.value = 0x00 + + while test_rx_pkts: + rx_frame = await tb.axis_sink.recv() + + rx_pkt = Ether(bytes(rx_frame)) + + tb.log.info("RX packet: %s", repr(rx_pkt)) + + if rx_pkt.type == 0x8808: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert rx_frame.tuser[-1] & 1 + else: + assert rx_frame.tuser & 1 + else: + test_pkt = test_rx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(rx_pkt).find(bytes(test_pkt)) == 0 + if isinstance(rx_frame.tuser, list): + assert not rx_frame.tuser[-1] & 1 + else: + assert not rx_frame.tuser & 1 + + tx_pfc_cnt = 0 + + while test_tx_pkts: + tx_frame = await tb.gmii_sink.recv() + + tx_pkt = Ether(bytes(tx_frame.get_payload())) + + tb.log.info("TX packet: %s", repr(tx_pkt)) + + if tx_pkt.type == 0x8808: + tx_pfc_cnt += 1 + else: + test_pkt = test_tx_pkts.pop(0) + # check prefix as frame gets zero-padded + assert bytes(tx_pkt).find(bytes(test_pkt)) == 0 + + assert tx_pfc_cnt > 2 and tx_pfc_cnt <= 9 + + assert tb.axis_sink.empty() + assert tb.gmii_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + def size_list(): return list(range(60, 128)) + [512, 1514] + [60]*10 @@ -241,6 +576,14 @@ if cocotb.SIM_NAME: factory.add_option("mii_sel", [False, True]) factory.generate_tests() + if cocotb.top.PFC_ENABLE.value: + for test in [run_test_lfc, run_test_pfc]: + factory = TestFactory(test) + factory.add_option("ifg", [12]) + factory.add_option("enable_gen", [None, cycle_en]) + factory.add_option("mii_sel", [False, True]) + factory.generate_tests() + # cocotb-test @@ -250,7 +593,8 @@ lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) -def test_eth_mac_1g(request): +@pytest.mark.parametrize("pfc_en", [1, 0]) +def test_eth_mac_1g(request, pfc_en): dut = "eth_mac_1g" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -259,6 +603,10 @@ def test_eth_mac_1g(request): os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "axis_gmii_rx.v"), os.path.join(rtl_dir, "axis_gmii_tx.v"), + os.path.join(rtl_dir, "mac_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_ctrl_tx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_rx.v"), + os.path.join(rtl_dir, "mac_pause_ctrl_tx.v"), os.path.join(rtl_dir, "lfsr.v"), ] @@ -276,6 +624,8 @@ def test_eth_mac_1g(request): parameters['RX_PTP_TS_WIDTH'] = 96 parameters['TX_USER_WIDTH'] = ((parameters['TX_PTP_TAG_WIDTH'] if parameters['TX_PTP_TAG_ENABLE'] else 0) + (1 if parameters['TX_PTP_TS_CTRL_IN_TUSER'] else 0) if parameters['TX_PTP_TS_ENABLE'] else 0) + 1 parameters['RX_USER_WIDTH'] = (parameters['RX_PTP_TS_WIDTH'] if parameters['RX_PTP_TS_ENABLE'] else 0) + 1 + parameters['PFC_ENABLE'] = pfc_en + parameters['PAUSE_ENABLE'] = parameters['PFC_ENABLE'] extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}