FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update default parameters

Browse Source
This commit is contained in:
Alex Forencich 2018-08-26 14:05:10 -07:00
parent 07a4da3bea
commit 71427e7cf0
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
rtl/axi_interconnect.v
View File

@ -49,9 +49,9 @@ module axi_interconnect #
parameter S_COUNT = 4,
parameter M_COUNT = 4,
parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000},
parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24},
parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111},
parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111}
parameter M_ADDR_WIDTH = {M_COUNT{32'd24}},
parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}}
)
(
input wire clk,

6
rtl/axil_interconnect.v
View File

@ -37,9 +37,9 @@ module axil_interconnect #
parameter S_COUNT = 4,
parameter M_COUNT = 4,
parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000},
parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24},
parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111},
parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111}
parameter M_ADDR_WIDTH = {M_COUNT{32'd24}},
parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}}
)
(
input wire clk,