From 71427e7cf0990a10dfb96874ecb7232fd095da4d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 26 Aug 2018 14:05:10 -0700 Subject: [PATCH] Update default parameters --- rtl/axi_interconnect.v | 6 +++--- rtl/axil_interconnect.v | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rtl/axi_interconnect.v b/rtl/axi_interconnect.v index f2084045b..9b2184078 100644 --- a/rtl/axi_interconnect.v +++ b/rtl/axi_interconnect.v @@ -49,9 +49,9 @@ module axi_interconnect # parameter S_COUNT = 4, parameter M_COUNT = 4, parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000}, - parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24}, - parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111}, - parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111} + parameter M_ADDR_WIDTH = {M_COUNT{32'd24}}, + parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}} ) ( input wire clk, diff --git a/rtl/axil_interconnect.v b/rtl/axil_interconnect.v index 4b7b75dc6..00fb9837c 100644 --- a/rtl/axil_interconnect.v +++ b/rtl/axil_interconnect.v @@ -37,9 +37,9 @@ module axil_interconnect # parameter S_COUNT = 4, parameter M_COUNT = 4, parameter M_BASE_ADDR = {32'h03000000, 32'h02000000, 32'h01000000, 32'h00000000}, - parameter M_ADDR_WIDTH = {32'd24, 32'd24, 32'd24, 32'd24}, - parameter M_CONNECT_READ = {4'b1111, 4'b1111, 4'b1111, 4'b1111}, - parameter M_CONNECT_WRITE = {4'b1111, 4'b1111, 4'b1111, 4'b1111} + parameter M_ADDR_WIDTH = {M_COUNT{32'd24}}, + parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_COUNT{{S_COUNT{1'b1}}}} ) ( input wire clk,