mirror of
https://github.com/corundum/corundum.git
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Add 25G mqnic design for BittWare 250-SoC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
ef5b2449dc
commit
7235484825
24
fpga/mqnic/250_SoC/fpga_25g/README.md
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24
fpga/mqnic/250_SoC/fpga_25g/README.md
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# Corundum mqnic for 250-SoC
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## Introduction
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This design targets the BittWare 250-SoC FPGA board.
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* FPGA: xczu19eg-ffvd1760-2-e
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* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are
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installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the 250-SoC board with Vivado. Then load the
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driver with insmod mqnic.ko. Check dmesg for output from driver
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initialization.
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1
fpga/mqnic/250_SoC/fpga_25g/app
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1
fpga/mqnic/250_SoC/fpga_25g/app
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../../../app/
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126
fpga/mqnic/250_SoC/fpga_25g/common/vivado.mk
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126
fpga/mqnic/250_SoC/fpga_25g/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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vivado: $(FPGA_TOP).xpr
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vivado $(FPGA_TOP).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project -quiet $(FPGA_TOP).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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185
fpga/mqnic/250_SoC/fpga_25g/fpga.xdc
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185
fpga/mqnic/250_SoC/fpga_25g/fpga.xdc
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# XDC constraints for the BittWare 250-SoC board
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# part: xczu19eg-ffvd1760-2-e
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# General configuration
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# System clocks
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# 200 MHz (DDR 0)
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set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_p]
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set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_n]
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create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
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# LEDs
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set_property -dict {LOC B12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC B13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC B10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# QSFP28 Interfaces
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set_property -dict {LOC H41 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H42 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H36 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H37 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G39 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G40 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G34 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC G35 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F41 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F42 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F36 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC F37 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E39 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E40 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E34 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC E35 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6
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set_property -dict {LOC H32 } [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_133 from Y4
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set_property -dict {LOC H33 } [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_133 from Y4
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set_property -dict {LOC L13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
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set_property -dict {LOC J15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_modprsl]
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set_property -dict {LOC K15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp0_intl]
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set_property -dict {LOC L12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
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# 322.265625 MHz MGT reference clock (from Y4)
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create_clock -period 3.103 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
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set_false_path -to [get_ports {qsfp0_resetl qsfp0_lpmode}]
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set_output_delay 0 [get_ports {qsfp0_resetl qsfp0_lpmode}]
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set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
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set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
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set_property -dict {LOC D41 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D42 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D36 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D37 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C39 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C40 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C34 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC C35 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B41 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B42 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B36 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC B37 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A39 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A40 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A34 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC A35 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X10Y7
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set_property -dict {LOC D32 } [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_134 from Y5
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set_property -dict {LOC D33 } [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_134 from Y5
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set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
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set_property -dict {LOC J13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_modprsl]
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set_property -dict {LOC J14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp1_intl]
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set_property -dict {LOC K12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
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# 322.265625 MHz MGT reference clock (from Y5)
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create_clock -period 3.103 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
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set_false_path -to [get_ports {qsfp1_resetl qsfp1_lpmode}]
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set_output_delay 0 [get_ports {qsfp1_resetl qsfp1_lpmode}]
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set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
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set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
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# I2C interface
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set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_ucd_scl]
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set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_ucd_sda]
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set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_i2c_scl]
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set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_i2c_sda]
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set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_smbus_scl]
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set_property -dict {LOC G13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_smbus_sda]
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set_property -dict {LOC R15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports fpga_smbus_en_n]
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set_false_path -to [get_ports {fpga_ucd_sda fpga_ucd_scl}]
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set_output_delay 0 [get_ports {fpga_ucd_sda fpga_ucd_scl}]
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set_false_path -from [get_ports {fpga_ucd_sda fpga_ucd_scl}]
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set_input_delay 0 [get_ports {fpga_ucd_sda fpga_ucd_scl}]
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set_false_path -to [get_ports {fpga_i2c_sda fpga_i2c_scl}]
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set_output_delay 0 [get_ports {fpga_i2c_sda fpga_i2c_scl}]
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set_false_path -from [get_ports {fpga_i2c_sda fpga_i2c_scl}]
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set_input_delay 0 [get_ports {fpga_i2c_sda fpga_i2c_scl}]
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set_false_path -to [get_ports {fpga_smbus_sda fpga_smbus_scl}]
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set_output_delay 0 [get_ports {fpga_smbus_sda fpga_smbus_scl}]
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set_false_path -from [get_ports {fpga_smbus_sda fpga_smbus_scl fpga_smbus_en_n}]
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set_input_delay 0 [get_ports {fpga_smbus_sda fpga_smbus_scl fpga_smbus_en_n}]
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# PCIe Interface
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set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_227 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_227 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC AG8 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_227 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
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set_property -dict {LOC AG7 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_227 GTHE4_CHANNEL_X1Y15 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_227 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_227 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AH6 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_227 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AH5 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_227 GTHE4_CHANNEL_X1Y14 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_227 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_227 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AJ8 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_227 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AJ7 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_227 GTHE4_CHANNEL_X1Y13 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_227 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_227 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AK6 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_227 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AK5 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_227 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_226 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_226 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AL8 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_226 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AL7 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_226 GTHE4_CHANNEL_X1Y11 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_226 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_226 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AM6 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_226 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AM5 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_226 GTHE4_CHANNEL_X1Y10 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_226 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_226 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AN8 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_226 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AN7 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_226 GTHE4_CHANNEL_X1Y9 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_226 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_226 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AP6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_226 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AP5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_226 GTHE4_CHANNEL_X1Y8 / GTHE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[8]}] ;# MGTHRXP3_225 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[8]}] ;# MGTHRXN3_225 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AP10} [get_ports {pcie_tx_p[8]}] ;# MGTHTXP3_225 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AP9 } [get_ports {pcie_tx_n[8]}] ;# MGTHTXN3_225 GTHE4_CHANNEL_X1Y7 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[9]}] ;# MGTHRXP2_225 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[9]}] ;# MGTHRXN2_225 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AR8 } [get_ports {pcie_tx_p[9]}] ;# MGTHTXP2_225 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AR7 } [get_ports {pcie_tx_n[9]}] ;# MGTHTXN2_225 GTHE4_CHANNEL_X1Y6 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[10]}] ;# MGTHRXP1_225 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[10]}] ;# MGTHRXN1_225 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AT6 } [get_ports {pcie_tx_p[10]}] ;# MGTHTXP1_225 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AT5 } [get_ports {pcie_tx_n[10]}] ;# MGTHTXN1_225 GTHE4_CHANNEL_X1Y5 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[11]}] ;# MGTHRXP0_225 GTHE4_CHANNEL_X1Y4 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[11]}] ;# MGTHRXN0_225 GTHE4_CHANNEL_X1Y4 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AT10} [get_ports {pcie_tx_p[11]}] ;# MGTHTXP0_225 GTHE4_CHANNEL_X1Y4 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AT9 } [get_ports {pcie_tx_n[11]}] ;# MGTHTXN0_225 GTHE4_CHANNEL_X1Y4 / GTHE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[12]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X1Y3 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[12]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X1Y3 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AU8 } [get_ports {pcie_tx_p[12]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X1Y3 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AU7 } [get_ports {pcie_tx_n[12]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X1Y3 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AY6 } [get_ports {pcie_rx_p[13]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X1Y2 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AY5 } [get_ports {pcie_rx_n[13]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X1Y2 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AV6 } [get_ports {pcie_tx_p[13]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X1Y2 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AV5 } [get_ports {pcie_tx_n[13]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X1Y2 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA4 } [get_ports {pcie_rx_p[14]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X1Y1 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA3 } [get_ports {pcie_rx_n[14]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X1Y1 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AW8 } [get_ports {pcie_tx_p[14]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X1Y1 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AW7 } [get_ports {pcie_tx_n[14]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X1Y1 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB6 } [get_ports {pcie_rx_p[15]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X1Y0 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB5 } [get_ports {pcie_rx_n[15]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X1Y0 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA8 } [get_ports {pcie_tx_p[15]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X1Y0 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA7 } [get_ports {pcie_tx_n[15]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X1Y0 / GTHE4_COMMON_X1Y0
|
||||
set_property -dict {LOC AH10} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_226 from edge via U6 and U8
|
||||
set_property -dict {LOC AH9 } [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_226 from edge via U6 and U8
|
||||
#set_property -dict {LOC AM10} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_224 from edge via U6 and U7
|
||||
#set_property -dict {LOC AM9 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_224 from edge via U6 and U7
|
||||
set_property -dict {LOC AM16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
154
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
Normal file
154
fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile
Normal file
@ -0,0 +1,154 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xczu19eg-ffvd1760-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = zynquplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/rb_drp.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
289
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
Normal file
289
fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl
Normal file
@ -0,0 +1,289 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4758093]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x198a]
|
||||
set board_device_id [expr 0x250e]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0x1001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
|
||||
# FW ID block
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Board configuration
|
||||
dict set params TDMA_BER_ENABLE "0"
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {25.78125}
|
||||
set eth_xcvr_sec_line_rate {10.3125}
|
||||
set eth_xcvr_refclk_freq {322.265625}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "0"
|
||||
dict set params PTP_PEROUT_ENABLE "0"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "13"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16]
|
||||
dict set params AXIS_ETH_TX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
# PCIe IDs
|
||||
set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie
|
||||
set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie
|
||||
set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
|
||||
|
||||
# PCIe IP core configuration
|
||||
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
|
||||
|
||||
# Internal interface settings
|
||||
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
|
||||
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]
|
||||
dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161]
|
||||
dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137]
|
||||
dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183]
|
||||
dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81]
|
||||
dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
# Transceiver configuration
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel]
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
# set_property generic $param_list [current_fileset]
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
154
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
Normal file
154
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile
Normal file
@ -0,0 +1,154 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xczu19eg-ffvd1760-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = zynquplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_interface_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_port_tx.v
|
||||
SYN_FILES += rtl/common/mqnic_port_rx.v
|
||||
SYN_FILES += rtl/common/mqnic_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_egress.v
|
||||
SYN_FILES += rtl/common/mqnic_l2_ingress.v
|
||||
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_fifo.v
|
||||
SYN_FILES += rtl/common/rx_fifo.v
|
||||
SYN_FILES += rtl/common/tx_req_mux.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/rb_drp.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v
|
||||
SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_demux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
289
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
Normal file
289
fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl
Normal file
@ -0,0 +1,289 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4758093]
|
||||
set fw_id [expr 0x00000000]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x198a]
|
||||
set board_device_id [expr 0x250e]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0x1001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
|
||||
# FW ID block
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# Board configuration
|
||||
dict set params TDMA_BER_ENABLE "0"
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {10.3125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {322.265625}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
# Structural configuration
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
|
||||
dict set params PORT_MASK "0"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_CLOCK_PIPELINE "0"
|
||||
dict set params PTP_CLOCK_CDC_PIPELINE "0"
|
||||
dict set params PTP_PORT_CDC_PIPELINE "0"
|
||||
dict set params PTP_PEROUT_ENABLE "0"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "13"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Interface configuration
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_CPL_FIFO_DEPTH "32"
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_IMM_ENABLE "0"
|
||||
dict set params DMA_IMM_WIDTH "32"
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# Interrupt configuration
|
||||
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16]
|
||||
dict set params AXIS_ETH_TX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "4"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "1"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
# PCIe IDs
|
||||
set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie
|
||||
set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie
|
||||
set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie
|
||||
set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie
|
||||
|
||||
# PCIe IP core configuration
|
||||
set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie
|
||||
|
||||
# Internal interface settings
|
||||
dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]]
|
||||
dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32]
|
||||
dict set params AXIS_PCIE_RC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 75 : 161]
|
||||
dict set params AXIS_PCIE_RQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 62 : 137]
|
||||
dict set params AXIS_PCIE_CQ_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 85 : 183]
|
||||
dict set params AXIS_PCIE_CC_USER_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH] < 512 ? 33 : 81]
|
||||
dict set params RQ_SEQ_NUM_WIDTH [expr [dict get $params AXIS_PCIE_RQ_USER_WIDTH] == 60 ? 4 : 6]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
# Transceiver configuration
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel]
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
# set_property generic $param_list [current_fileset]
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
129
fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl
Normal file
129
fpga/mqnic/250_SoC/fpga_25g/ip/eth_xcvr_gty.tcl
Normal file
@ -0,0 +1,129 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set base_name {eth_xcvr_gty}
|
||||
|
||||
set preset {GTY-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {25.78125}
|
||||
set sec_line_rate {10.3125}
|
||||
set refclk_freq {322.265625}
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {64}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# DRP connections
|
||||
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
|
||||
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
# channel digital monitor
|
||||
lappend extra_ports dmonitorout_out
|
||||
# channel PRBS
|
||||
lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
|
||||
# channel eye scan
|
||||
lappend extra_ports eyescandataerror_out
|
||||
# channel loopback
|
||||
lappend extra_ports loopback_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_channel" $preset $config
|
||||
32
fpga/mqnic/250_SoC/fpga_25g/ip/pcie4_uscale_plus_0.tcl
Normal file
32
fpga/mqnic/250_SoC/fpga_25g/ip/pcie4_uscale_plus_0.tcl
Normal file
@ -0,0 +1,32 @@
|
||||
|
||||
create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
|
||||
CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
|
||||
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
|
||||
CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
|
||||
CONFIG.axisten_if_enable_client_tag {true} \
|
||||
CONFIG.axisten_if_width {512_bit} \
|
||||
CONFIG.extended_tag_field {true} \
|
||||
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
|
||||
CONFIG.axisten_freq {250} \
|
||||
CONFIG.PF0_CLASS_CODE {020000} \
|
||||
CONFIG.PF0_DEVICE_ID {1001} \
|
||||
CONFIG.PF0_SUBSYSTEM_ID {250e} \
|
||||
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {198a} \
|
||||
CONFIG.pf0_bar0_64bit {true} \
|
||||
CONFIG.pf0_bar0_prefetchable {true} \
|
||||
CONFIG.pf0_bar0_scale {Megabytes} \
|
||||
CONFIG.pf0_bar0_size {16} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
1
fpga/mqnic/250_SoC/fpga_25g/lib
Symbolic link
1
fpga/mqnic/250_SoC/fpga_25g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
16
fpga/mqnic/250_SoC/fpga_25g/placement.xdc
Normal file
16
fpga/mqnic/250_SoC/fpga_25g/placement.xdc
Normal file
@ -0,0 +1,16 @@
|
||||
# Placement constraints
|
||||
create_pblock pblock_pcie
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_plus_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"]
|
||||
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X2Y0:CLOCKREGION_X3Y3}
|
||||
|
||||
create_pblock pblock_eth
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_phy_quad_inst qsfp1_phy_quad_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
|
||||
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
|
||||
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y8:CLOCKREGION_X0Y10}
|
||||
1
fpga/mqnic/250_SoC/fpga_25g/rtl/common
Symbolic link
1
fpga/mqnic/250_SoC/fpga_25g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
1544
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
Normal file
1544
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
1394
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
Normal file
1394
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
62
fpga/mqnic/250_SoC/fpga_25g/rtl/sync_signal.v
Normal file
62
fpga/mqnic/250_SoC/fpga_25g/rtl/sync_signal.v
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
450
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
Normal file
450
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
Normal file
@ -0,0 +1,450 @@
|
||||
# Copyright 2020-2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
|
||||
export PARAM_PORT_MASK ?= 0
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_CLK_PERIOD_NS_NUM = 512
|
||||
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
|
||||
export PARAM_PTP_CLOCK_PIPELINE ?= 0
|
||||
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
|
||||
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 0
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Interface configuration
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 32768
|
||||
export PARAM_RX_RAM_SIZE ?= 131072
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ID ?= $(shell echo $$((0x00000000)) )
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_IMM_ENABLE ?= 0
|
||||
export PARAM_DMA_IMM_WIDTH ?= 32
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 256
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# Interrupt configuration
|
||||
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 4
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/mqnic.py
Symbolic link
1
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../../common/tb/mqnic.py
|
||||
906
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
Normal file
906
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
Normal file
@ -0,0 +1,906 @@
|
||||
"""
|
||||
|
||||
Copyright 2020-2022, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.axi import AxiStreamBus
|
||||
from cocotbext.eth import XgmiiSource, XgmiiSink
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut, msix_count=32):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = UltraScalePlusPcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
pcie_link_width=16,
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
|
||||
cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
|
||||
rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
|
||||
rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
|
||||
rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
enable_rx_msg_interface=False,
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=msix_count-1,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00010000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00018000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
user_clk=dut.clk_250mhz,
|
||||
user_reset=dut.rst_250mhz,
|
||||
# user_lnk_up
|
||||
# sys_clk
|
||||
# sys_clk_gt
|
||||
# sys_reset
|
||||
# phy_rdy_out
|
||||
|
||||
# Requester reQuest Interface
|
||||
rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
|
||||
pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
|
||||
pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
|
||||
pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
|
||||
pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
|
||||
# pcie_rq_tag0
|
||||
# pcie_rq_tag1
|
||||
# pcie_rq_tag_av
|
||||
# pcie_rq_tag_vld0
|
||||
# pcie_rq_tag_vld1
|
||||
|
||||
# Requester Completion Interface
|
||||
rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
|
||||
|
||||
# Completer reQuest Interface
|
||||
cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
|
||||
# pcie_cq_np_req
|
||||
# pcie_cq_np_req_count
|
||||
|
||||
# Completer Completion Interface
|
||||
cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
|
||||
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=dut.cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
|
||||
cfg_mgmt_write=dut.cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=dut.cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
|
||||
# cfg_mgmt_debug_access
|
||||
|
||||
# Configuration Status Interface
|
||||
# cfg_phy_link_down
|
||||
# cfg_phy_link_status
|
||||
# cfg_negotiated_width
|
||||
# cfg_current_speed
|
||||
cfg_max_payload=dut.cfg_max_payload,
|
||||
cfg_max_read_req=dut.cfg_max_read_req,
|
||||
# cfg_function_status
|
||||
# cfg_vf_status
|
||||
# cfg_function_power_state
|
||||
# cfg_vf_power_state
|
||||
# cfg_link_power_state
|
||||
# cfg_err_cor_out
|
||||
# cfg_err_nonfatal_out
|
||||
# cfg_err_fatal_out
|
||||
# cfg_local_error_out
|
||||
# cfg_local_error_valid
|
||||
# cfg_rx_pm_state
|
||||
# cfg_tx_pm_state
|
||||
# cfg_ltssm_state
|
||||
# cfg_rcb_status
|
||||
# cfg_obff_enable
|
||||
# cfg_pl_status_change
|
||||
# cfg_tph_requester_enable
|
||||
# cfg_tph_st_mode
|
||||
# cfg_vf_tph_requester_enable
|
||||
# cfg_vf_tph_st_mode
|
||||
|
||||
# Configuration Received Message Interface
|
||||
# cfg_msg_received
|
||||
# cfg_msg_received_data
|
||||
# cfg_msg_received_type
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
# cfg_msg_transmit
|
||||
# cfg_msg_transmit_type
|
||||
# cfg_msg_transmit_data
|
||||
# cfg_msg_transmit_done
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
cfg_fc_ph=dut.cfg_fc_ph,
|
||||
cfg_fc_pd=dut.cfg_fc_pd,
|
||||
cfg_fc_nph=dut.cfg_fc_nph,
|
||||
cfg_fc_npd=dut.cfg_fc_npd,
|
||||
cfg_fc_cplh=dut.cfg_fc_cplh,
|
||||
cfg_fc_cpld=dut.cfg_fc_cpld,
|
||||
cfg_fc_sel=dut.cfg_fc_sel,
|
||||
|
||||
# Configuration Control Interface
|
||||
# cfg_hot_reset_in
|
||||
# cfg_hot_reset_out
|
||||
# cfg_config_space_enable
|
||||
# cfg_dsn
|
||||
# cfg_bus_number
|
||||
# cfg_ds_port_number
|
||||
# cfg_ds_bus_number
|
||||
# cfg_ds_device_number
|
||||
# cfg_ds_function_number
|
||||
# cfg_power_state_change_ack
|
||||
# cfg_power_state_change_interrupt
|
||||
cfg_err_cor_in=dut.status_error_cor,
|
||||
cfg_err_uncor_in=dut.status_error_uncor,
|
||||
# cfg_flr_in_process
|
||||
# cfg_flr_done
|
||||
# cfg_vf_flr_in_process
|
||||
# cfg_vf_flr_func_num
|
||||
# cfg_vf_flr_done
|
||||
# cfg_pm_aspm_l1_entry_reject
|
||||
# cfg_pm_aspm_tx_l0s_entry_disable
|
||||
# cfg_req_pm_transition_l23_ready
|
||||
# cfg_link_training_enable
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
# cfg_ext_write_received
|
||||
# cfg_ext_register_number
|
||||
# cfg_ext_function_number
|
||||
# cfg_ext_write_data
|
||||
# cfg_ext_write_byte_enable
|
||||
# cfg_ext_read_data
|
||||
# cfg_ext_read_data_valid
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start())
|
||||
dut.ptp_rst.setimmediatevalue(0)
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
# Ethernet
|
||||
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
|
||||
|
||||
dut.qsfp0_rx_status_1.setimmediatevalue(1)
|
||||
dut.qsfp0_rx_status_2.setimmediatevalue(1)
|
||||
dut.qsfp0_rx_status_3.setimmediatevalue(1)
|
||||
dut.qsfp0_rx_status_4.setimmediatevalue(1)
|
||||
|
||||
dut.qsfp1_rx_status_1.setimmediatevalue(1)
|
||||
dut.qsfp1_rx_status_2.setimmediatevalue(1)
|
||||
dut.qsfp1_rx_status_3.setimmediatevalue(1)
|
||||
dut.qsfp1_rx_status_4.setimmediatevalue(1)
|
||||
|
||||
dut.fpga_i2c_scl_i.setimmediatevalue(1)
|
||||
dut.fpga_i2c_sda_i.setimmediatevalue(1)
|
||||
|
||||
dut.fpga_ucd_scl_i.setimmediatevalue(1)
|
||||
dut.fpga_ucd_sda_i.setimmediatevalue(1)
|
||||
|
||||
dut.fpga_smbus_scl_i.setimmediatevalue(1)
|
||||
dut.fpga_smbus_sda_i.setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp0_drp_clk, 8, units="ns").start())
|
||||
dut.qsfp0_drp_rst.setimmediatevalue(0)
|
||||
dut.qsfp0_drp_do.setimmediatevalue(0)
|
||||
dut.qsfp0_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
|
||||
dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
|
||||
dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
|
||||
dut.qsfp0_rx_error_count_4.setimmediatevalue(0)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_drp_clk, 8, units="ns").start())
|
||||
dut.qsfp1_drp_rst.setimmediatevalue(0)
|
||||
dut.qsfp1_drp_do.setimmediatevalue(0)
|
||||
dut.qsfp1_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
|
||||
dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
|
||||
dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
|
||||
dut.qsfp1_rx_error_count_4.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp0_modprsl.setimmediatevalue(0)
|
||||
dut.qsfp0_intl.setimmediatevalue(1)
|
||||
|
||||
dut.qsfp1_modprsl.setimmediatevalue(0)
|
||||
dut.qsfp1_intl.setimmediatevalue(1)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(1)
|
||||
|
||||
await FallingEdge(self.dut.rst_250mhz)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
if self.loopback_enable:
|
||||
if not self.qsfp0_1_sink.empty():
|
||||
await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv())
|
||||
if not self.qsfp0_2_sink.empty():
|
||||
await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv())
|
||||
if not self.qsfp0_3_sink.empty():
|
||||
await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv())
|
||||
if not self.qsfp0_4_sink.empty():
|
||||
await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv())
|
||||
if not self.qsfp1_1_sink.empty():
|
||||
await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv())
|
||||
if not self.qsfp1_2_sink.empty():
|
||||
await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv())
|
||||
if not self.qsfp1_3_sink.empty():
|
||||
await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv())
|
||||
if not self.qsfp1_4_sink.empty():
|
||||
await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await tb.driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
for k in range(tb.driver.interfaces[0].tx_queue_count):
|
||||
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.qsfp0_1_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp0_1_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
# await tb.driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# pkt = await tb.qsfp1_1_sink.recv()
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
|
||||
# await tb.qsfp1_1_source.send(pkt)
|
||||
|
||||
# pkt = await tb.driver.interfaces[1].recv()
|
||||
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.qsfp0_1_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp0_1_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Queue mapping offset test")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert pkt.queue == k
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k in range(64):
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=k+0)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
for k in range(64):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == 4
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_fifo.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rb_drp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_demux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
|
||||
parameters['PORT_MASK'] = 0
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_CLK_PERIOD_NS_NUM'] = 512
|
||||
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
|
||||
parameters['PTP_CLOCK_PIPELINE'] = 0
|
||||
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
|
||||
parameters['PTP_PORT_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PEROUT_ENABLE'] = 0
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Interface configuration
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 32
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 131072
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ID'] = 0x00000000
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_IMM_ENABLE'] = 0
|
||||
parameters['DMA_IMM_WIDTH'] = 32
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['AXIS_PCIE_DATA_WIDTH'] = 512
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 256
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# Interrupt configuration
|
||||
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 4
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user