From 729c3a04581a5f4312a046bafd49825883b00841 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 8 Jul 2022 22:07:18 -0700
Subject: [PATCH] Update for PCIe shim changes, enable TLP straddling on US/US+
 devices, and use 256 tags on US+ devices

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 .../dma_bench/tb/mqnic_core_pcie_us/Makefile  |  4 +-
 .../test_mqnic_core_pcie_us.py                | 14 ++++---
 .../template/tb/mqnic_core_pcie_us/Makefile   |  4 +-
 .../test_mqnic_core_pcie_us.py                | 14 ++++---
 fpga/common/rtl/mqnic_core_pcie.v             | 37 ++++++++++++-------
 fpga/common/rtl/mqnic_core_pcie_s10.v         | 18 ++++++---
 fpga/common/rtl/mqnic_core_pcie_us.v          | 28 ++++++++++----
 fpga/common/tb/mqnic_core_pcie_s10/Makefile   |  5 ++-
 .../test_mqnic_core_pcie_s10.py               |  9 +++--
 fpga/common/tb/mqnic_core_pcie_us/Makefile    |  4 +-
 .../test_mqnic_core_pcie_us.py                | 14 ++++---
 .../tb/mqnic_core_pcie_us_tdma/Makefile       |  4 +-
 .../test_mqnic_core_pcie_us.py                | 14 ++++---
 .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile      |  2 +
 .../ADM_PCIE_9V3/fpga_100g/fpga/config.tcl    |  4 +-
 .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile |  2 +
 .../fpga_100g/fpga_tdma/config.tcl            |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v  | 10 ++++-
 .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v    | 10 ++++-
 .../fpga_100g/tb/fpga_core/Makefile           |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile |  2 +
 .../ADM_PCIE_9V3/fpga_25g/fpga/config.tcl     |  4 +-
 .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile   |  2 +
 .../ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile  |  2 +
 .../fpga_25g/fpga_tdma/config.tcl             |  6 +--
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  4 +-
 fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v   | 10 ++++-
 .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v     | 10 ++++-
 .../fpga_25g/tb/fpga_core/Makefile            |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/AU200/fpga_100g/fpga/Makefile      |  2 +
 fpga/mqnic/AU200/fpga_100g/fpga/config.tcl    |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/AU200/fpga_100g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v    | 10 ++++-
 .../AU200/fpga_100g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/AU200/fpga_25g/fpga/Makefile       |  2 +
 fpga/mqnic/AU200/fpga_25g/fpga/config.tcl     |  4 +-
 fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile   |  2 +
 fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl |  4 +-
 fpga/mqnic/AU200/fpga_25g/rtl/fpga.v          | 10 ++++-
 fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v     | 10 ++++-
 .../AU200/fpga_25g/tb/fpga_core/Makefile      |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/AU250/fpga_100g/fpga/Makefile      |  2 +
 fpga/mqnic/AU250/fpga_100g/fpga/config.tcl    |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/AU250/fpga_100g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v    | 10 ++++-
 .../AU250/fpga_100g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/AU250/fpga_25g/fpga/Makefile       |  2 +
 fpga/mqnic/AU250/fpga_25g/fpga/config.tcl     |  4 +-
 fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile   |  2 +
 fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl |  4 +-
 fpga/mqnic/AU250/fpga_25g/rtl/fpga.v          | 10 ++++-
 fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v     | 10 ++++-
 .../AU250/fpga_25g/tb/fpga_core/Makefile      |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/AU280/fpga_100g/fpga/Makefile      |  2 +
 fpga/mqnic/AU280/fpga_100g/fpga/config.tcl    |  4 +-
 .../fpga_100g/ip/pcie4c_uscale_plus_0.tcl     |  4 +-
 fpga/mqnic/AU280/fpga_100g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v    | 10 ++++-
 .../AU280/fpga_100g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/AU280/fpga_25g/fpga/Makefile       |  2 +
 fpga/mqnic/AU280/fpga_25g/fpga/config.tcl     |  4 +-
 fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile   |  2 +
 fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../fpga_25g/ip/pcie4c_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/AU280/fpga_25g/rtl/fpga.v          | 10 ++++-
 fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v     | 10 ++++-
 .../AU280/fpga_25g/tb/fpga_core/Makefile      |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/AU50/fpga_100g/fpga/Makefile       |  2 +
 fpga/mqnic/AU50/fpga_100g/fpga/config.tcl     |  4 +-
 .../fpga_100g/ip/pcie4c_uscale_plus_0.tcl     |  4 +-
 fpga/mqnic/AU50/fpga_100g/rtl/fpga.v          | 10 ++++-
 fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v     | 10 ++++-
 .../AU50/fpga_100g/tb/fpga_core/Makefile      |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/AU50/fpga_25g/fpga/Makefile        |  2 +
 fpga/mqnic/AU50/fpga_25g/fpga/config.tcl      |  4 +-
 fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile    |  2 +
 fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl  |  4 +-
 .../AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl |  4 +-
 fpga/mqnic/AU50/fpga_25g/rtl/fpga.v           | 10 ++++-
 fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v      | 10 ++++-
 .../mqnic/AU50/fpga_25g/tb/fpga_core/Makefile |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 .../fpga/fpga_ku040/Makefile                  |  2 +
 .../fpga/fpga_ku040/config.tcl                |  2 +-
 .../fpga/fpga_ku060/Makefile                  |  2 +
 .../fpga/fpga_ku060/config.tcl                |  2 +-
 .../fpga/ip/pcie3_ultrascale_0.tcl            |  2 +-
 .../DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v    |  8 ++++
 .../fpga/rtl/fpga_core.v                      |  8 ++++
 .../fpga/tb/fpga_core/Makefile                |  2 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  4 +-
 fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile    |  2 +
 fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl  |  2 +-
 .../mqnic/NetFPGA_SUME/fpga/ip/pcie3_7x_0.tcl |  2 +-
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v       |  8 ++++
 fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v  |  8 ++++
 .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile   |  2 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  4 +-
 fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile     |  2 +
 fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl   |  2 +-
 .../fpga/ip/pcie3_ultrascale_0.tcl            |  2 +-
 fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v        |  8 ++++
 fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v   |  8 ++++
 .../Nexus_K35_S/fpga/tb/fpga_core/Makefile    |  2 +
 .../fpga/tb/fpga_core/test_fpga_core.py       |  4 +-
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile |  2 +
 .../Nexus_K3P_Q/fpga_25g/fpga/config.tcl      |  4 +-
 .../Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile    |  2 +
 .../Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl  |  4 +-
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  2 +-
 fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v    | 10 ++++-
 .../Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v      | 10 ++++-
 .../fpga_25g/tb/fpga_core/Makefile            |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile |  2 +
 .../Nexus_K3P_S/fpga_25g/fpga/config.tcl      |  4 +-
 .../Nexus_K3P_S/fpga_25g/fpga_10g/Makefile    |  2 +
 .../Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl  |  4 +-
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  2 +-
 fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v    | 10 ++++-
 .../Nexus_K3P_S/fpga_25g/rtl/fpga_core.v      | 10 ++++-
 .../fpga_25g/tb/fpga_core/Makefile            |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 .../S10MX_DK/fpga_10g/fpga_1sm21b/Makefile    |  3 ++
 .../S10MX_DK/fpga_10g/fpga_1sm21c/Makefile    |  3 ++
 .../S10MX_DK/fpga_10g/tb/fpga_core/Makefile   |  3 ++
 .../fpga_10g/tb/fpga_core/test_fpga_core.py   |  3 ++
 fpga/mqnic/VCU108/fpga_10g/fpga/Makefile      |  2 +
 fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl    |  2 +-
 .../VCU108/fpga_10g/ip/pcie3_ultrascale_0.tcl |  2 +-
 fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v         |  8 ++++
 fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v    |  8 ++++
 .../VCU108/fpga_10g/tb/fpga_core/Makefile     |  2 +
 .../fpga_10g/tb/fpga_core/test_fpga_core.py   |  4 +-
 fpga/mqnic/VCU118/fpga_100g/fpga/Makefile     |  2 +
 fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl   |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v        | 10 ++++-
 fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v   | 10 ++++-
 .../VCU118/fpga_100g/tb/fpga_core/Makefile    |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/VCU118/fpga_25g/fpga/Makefile      |  2 +
 fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl    |  4 +-
 fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile  |  2 +
 .../mqnic/VCU118/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  4 +-
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v    | 10 ++++-
 .../VCU118/fpga_25g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile    |  2 +
 fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl  |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v       | 10 ++++-
 fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v  | 10 ++++-
 .../VCU1525/fpga_100g/tb/fpga_core/Makefile   |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile     |  2 +
 fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl   |  4 +-
 fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile |  2 +
 .../VCU1525/fpga_25g/fpga_10g/config.tcl      |  4 +-
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  4 +-
 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v        | 10 ++++-
 fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v   | 10 ++++-
 .../VCU1525/fpga_25g/tb/fpga_core/Makefile    |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile     |  2 +
 fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl   |  4 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v        | 10 ++++-
 fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v   | 10 ++++-
 .../XUPP3R/fpga_100g/tb/fpga_core/Makefile    |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile      |  2 +
 fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl    |  4 +-
 fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile  |  2 +
 .../mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl |  4 +-
 .../fpga_25g/ip/pcie4_uscale_plus_0.tcl       |  4 +-
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v    | 10 ++++-
 .../XUPP3R/fpga_25g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile     |  2 +
 fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl   |  4 +-
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v        |  6 ++-
 fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v   |  6 ++-
 .../ZCU106/fpga_pcie/tb/fpga_core/Makefile    |  4 +-
 .../fpga_pcie/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile      |  2 +
 fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl    |  2 +-
 .../fpga_100g/fpga_app_dma_bench/Makefile     |  2 +
 .../fpga_100g/fpga_app_dma_bench/config.tcl   |  2 +-
 .../fpga_100g/fpga_app_template/Makefile      |  3 ++
 .../fpga_100g/fpga_app_template/config.tcl    |  2 +-
 fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile |  2 +
 .../fb2CG/fpga_100g/fpga_tdma/config.tcl      |  2 +-
 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl      |  4 +-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v         | 10 ++++-
 fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v    | 10 ++++-
 .../fb2CG/fpga_100g/tb/fpga_core/Makefile     |  4 +-
 .../fpga_100g/tb/fpga_core/test_fpga_core.py  | 14 ++++---
 fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile       |  2 +
 fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl     |  2 +-
 fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile   |  2 +
 fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl |  2 +-
 fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile  |  2 +
 .../mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl |  4 +-
 .../fb2CG/fpga_25g/ip/pcie4_uscale_plus_0.tcl |  4 +-
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v          | 10 ++++-
 fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v     | 10 ++++-
 .../fb2CG/fpga_25g/tb/fpga_core/Makefile      |  4 +-
 .../fpga_25g/tb/fpga_core/test_fpga_core.py   | 14 ++++---
 tox.ini                                       |  2 +-
 228 files changed, 1032 insertions(+), 352 deletions(-)

diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
index 67c664ac6..35af3646e 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -211,7 +213,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 768e7c2b0..666bbe29d 100644
--- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -82,11 +82,11 @@ class TB(object):
             # pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -927,6 +927,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -1031,7 +1033,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
index 7e8dba1de..7a28c796e 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile
@@ -107,6 +107,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index d4b938fde..35f31d0d1 100644
--- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -82,11 +82,11 @@ class TB(object):
             # pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -767,6 +767,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -871,7 +873,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v
index d39a7c11a..583c3a5b8 100644
--- a/fpga/common/rtl/mqnic_core_pcie.v
+++ b/fpga/common/rtl/mqnic_core_pcie.v
@@ -199,6 +199,7 @@ module mqnic_core_pcie #
      * TLP input (request to BAR)
      */
     input  wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_req_tlp_data,
+    input  wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_req_tlp_strb,
     input  wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_req_tlp_hdr,
     input  wire [TLP_SEG_COUNT*3-1:0]                    pcie_rx_req_tlp_bar_id,
     input  wire [TLP_SEG_COUNT*8-1:0]                    pcie_rx_req_tlp_func_num,
@@ -211,6 +212,7 @@ module mqnic_core_pcie #
      * TLP input (completion to DMA)
      */
     input  wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_cpl_tlp_data,
+    input  wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_cpl_tlp_strb,
     input  wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_cpl_tlp_hdr,
     input  wire [TLP_SEG_COUNT*4-1:0]                    pcie_rx_cpl_tlp_error,
     input  wire [TLP_SEG_COUNT-1:0]                      pcie_rx_cpl_tlp_valid,
@@ -266,12 +268,12 @@ module mqnic_core_pcie #
     /*
      * TLP output (MSI-X write request)
      */
-    output wire [TLP_DATA_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_data,
-    output wire [TLP_STRB_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_strb,
-    output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_tx_msix_wr_req_tlp_hdr,
-    output wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_valid,
-    output wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_sop,
-    output wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_eop,
+    output wire [31:0]                                   pcie_tx_msix_wr_req_tlp_data,
+    output wire                                          pcie_tx_msix_wr_req_tlp_strb,
+    output wire [TLP_HDR_WIDTH-1:0]                      pcie_tx_msix_wr_req_tlp_hdr,
+    output wire                                          pcie_tx_msix_wr_req_tlp_valid,
+    output wire                                          pcie_tx_msix_wr_req_tlp_sop,
+    output wire                                          pcie_tx_msix_wr_req_tlp_eop,
     input  wire                                          pcie_tx_msix_wr_req_tlp_ready,
 
     /*
@@ -428,6 +430,7 @@ parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8);
 
 // PCIe connections
 wire [TLP_DATA_WIDTH-1:0]                    pcie_ctrl_rx_req_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                    pcie_ctrl_rx_req_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]       pcie_ctrl_rx_req_tlp_hdr;
 wire [TLP_SEG_COUNT*3-1:0]                   pcie_ctrl_rx_req_tlp_bar_id;
 wire [TLP_SEG_COUNT*8-1:0]                   pcie_ctrl_rx_req_tlp_func_num;
@@ -445,6 +448,7 @@ wire [TLP_SEG_COUNT-1:0]                     pcie_ctrl_tx_cpl_tlp_eop;
 wire                                         pcie_ctrl_tx_cpl_tlp_ready;
 
 wire [TLP_DATA_WIDTH-1:0]                    pcie_app_ctrl_rx_req_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                    pcie_app_ctrl_rx_req_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]       pcie_app_ctrl_rx_req_tlp_hdr;
 wire [TLP_SEG_COUNT*3-1:0]                   pcie_app_ctrl_rx_req_tlp_bar_id;
 wire [TLP_SEG_COUNT*8-1:0]                   pcie_app_ctrl_rx_req_tlp_func_num;
@@ -585,7 +589,9 @@ if (APP_ENABLE) begin : pcie_tlp_mux
         .TLP_DATA_WIDTH(TLP_DATA_WIDTH),
         .TLP_STRB_WIDTH(TLP_STRB_WIDTH),
         .TLP_HDR_WIDTH(TLP_HDR_WIDTH),
-        .TLP_SEG_COUNT(TLP_SEG_COUNT),
+        .IN_TLP_SEG_COUNT(TLP_SEG_COUNT),
+        .OUT_TLP_SEG_COUNT(TLP_SEG_COUNT),
+        .FIFO_ENABLE(0),
         .BAR_BASE(0),
         .BAR_STRIDE(2),
         .BAR_IDS(0)
@@ -598,7 +604,7 @@ if (APP_ENABLE) begin : pcie_tlp_mux
          * TLP input
          */
         .in_tlp_data(pcie_rx_req_tlp_data),
-        .in_tlp_strb(0),
+        .in_tlp_strb(pcie_rx_req_tlp_strb),
         .in_tlp_hdr(pcie_rx_req_tlp_hdr),
         .in_tlp_bar_id(pcie_rx_req_tlp_bar_id),
         .in_tlp_func_num(pcie_rx_req_tlp_func_num),
@@ -612,7 +618,7 @@ if (APP_ENABLE) begin : pcie_tlp_mux
          * TLP output
          */
         .out_tlp_data(    {pcie_app_ctrl_rx_req_tlp_data,     pcie_ctrl_rx_req_tlp_data    }),
-        .out_tlp_strb(),
+        .out_tlp_strb(    {pcie_app_ctrl_rx_req_tlp_strb,     pcie_ctrl_rx_req_tlp_strb    }),
         .out_tlp_hdr(     {pcie_app_ctrl_rx_req_tlp_hdr,      pcie_ctrl_rx_req_tlp_hdr     }),
         .out_tlp_bar_id(  {pcie_app_ctrl_rx_req_tlp_bar_id,   pcie_ctrl_rx_req_tlp_bar_id  }),
         .out_tlp_func_num({pcie_app_ctrl_rx_req_tlp_func_num, pcie_ctrl_rx_req_tlp_func_num}),
@@ -625,7 +631,13 @@ if (APP_ENABLE) begin : pcie_tlp_mux
         /*
          * Control
          */
-        .enable(1'b1)
+        .enable(1'b1),
+
+        /*
+         * Status
+         */
+        .fifo_half_full(),
+        .fifo_watermark()
     );
 
     pcie_tlp_mux #(
@@ -673,6 +685,7 @@ if (APP_ENABLE) begin : pcie_tlp_mux
 end else begin
 
     assign pcie_ctrl_rx_req_tlp_data = pcie_rx_req_tlp_data;
+    assign pcie_ctrl_rx_req_tlp_strb = pcie_rx_req_tlp_strb;
     assign pcie_ctrl_rx_req_tlp_hdr = pcie_rx_req_tlp_hdr;
     assign pcie_ctrl_rx_req_tlp_bar_id = pcie_rx_req_tlp_bar_id;
     assign pcie_ctrl_rx_req_tlp_func_num = pcie_rx_req_tlp_func_num;
@@ -690,6 +703,7 @@ end else begin
     assign pcie_ctrl_tx_cpl_tlp_ready = pcie_tx_cpl_tlp_ready;
 
     assign pcie_app_ctrl_rx_req_tlp_data = 0;
+    assign pcie_app_ctrl_rx_req_tlp_strb = 0;
     assign pcie_app_ctrl_rx_req_tlp_hdr = 0;
     assign pcie_app_ctrl_rx_req_tlp_valid = 0;
     assign pcie_app_ctrl_rx_req_tlp_sop = 0;
@@ -1118,10 +1132,7 @@ pcie_msix #(
     .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
     .AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
     .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
-    .TLP_DATA_WIDTH(TLP_DATA_WIDTH),
-    .TLP_STRB_WIDTH(TLP_STRB_WIDTH),
     .TLP_HDR_WIDTH(TLP_HDR_WIDTH),
-    .TLP_SEG_COUNT(TLP_SEG_COUNT),
     .TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
 )
 pcie_msix_inst (
diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v
index 5bfdaa8f9..105255389 100644
--- a/fpga/common/rtl/mqnic_core_pcie_s10.v
+++ b/fpga/common/rtl/mqnic_core_pcie_s10.v
@@ -361,6 +361,7 @@ parameter TLP_SEG_COUNT = 1;
 parameter TX_SEQ_NUM_COUNT = SEG_COUNT;
 
 wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_req_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_req_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_req_tlp_hdr;
 wire [TLP_SEG_COUNT*3-1:0]                    pcie_rx_req_tlp_bar_id;
 wire [TLP_SEG_COUNT*8-1:0]                    pcie_rx_req_tlp_func_num;
@@ -370,6 +371,7 @@ wire [TLP_SEG_COUNT-1:0]                      pcie_rx_req_tlp_eop;
 wire                                          pcie_rx_req_tlp_ready;
 
 wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_cpl_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_cpl_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_cpl_tlp_hdr;
 wire [TLP_SEG_COUNT*4-1:0]                    pcie_rx_cpl_tlp_error;
 wire [TLP_SEG_COUNT-1:0]                      pcie_rx_cpl_tlp_valid;
@@ -407,12 +409,12 @@ wire [TLP_SEG_COUNT-1:0]                      pcie_tx_cpl_tlp_sop;
 wire [TLP_SEG_COUNT-1:0]                      pcie_tx_cpl_tlp_eop;
 wire                                          pcie_tx_cpl_tlp_ready;
 
-wire [TLP_DATA_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_data;
-wire [TLP_STRB_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_strb;
-wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_tx_msix_wr_req_tlp_hdr;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_valid;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_sop;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_eop;
+wire [31:0]                                   pcie_tx_msix_wr_req_tlp_data;
+wire                                          pcie_tx_msix_wr_req_tlp_strb;
+wire [TLP_HDR_WIDTH-1:0]                      pcie_tx_msix_wr_req_tlp_hdr;
+wire                                          pcie_tx_msix_wr_req_tlp_valid;
+wire                                          pcie_tx_msix_wr_req_tlp_sop;
+wire                                          pcie_tx_msix_wr_req_tlp_eop;
 wire                                          pcie_tx_msix_wr_req_tlp_ready;
 
 wire [7:0]   pcie_tx_fc_ph_av;
@@ -504,6 +506,7 @@ pcie_s10_if_inst (
      * TLP output (request to BAR)
      */
     .rx_req_tlp_data(pcie_rx_req_tlp_data),
+    .rx_req_tlp_strb(pcie_rx_req_tlp_strb),
     .rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
     .rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
     .rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
@@ -516,6 +519,7 @@ pcie_s10_if_inst (
      * TLP output (completion to DMA)
      */
     .rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
+    .rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
     .rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
     .rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
     .rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
@@ -761,6 +765,7 @@ core_pcie_inst (
      * TLP input (request to BAR)
      */
     .pcie_rx_req_tlp_data(pcie_rx_req_tlp_data),
+    .pcie_rx_req_tlp_strb(pcie_rx_req_tlp_strb),
     .pcie_rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
     .pcie_rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
     .pcie_rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
@@ -773,6 +778,7 @@ core_pcie_inst (
      * TLP input (completion to DMA)
      */
     .pcie_rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
+    .pcie_rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
     .pcie_rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
     .pcie_rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
     .pcie_rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v
index 51cc6ea40..30a743279 100644
--- a/fpga/common/rtl/mqnic_core_pcie_us.v
+++ b/fpga/common/rtl/mqnic_core_pcie_us.v
@@ -140,11 +140,15 @@ module mqnic_core_pcie_us #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
     parameter F_COUNT = PF_COUNT+VF_COUNT,
-    parameter PCIE_TAG_COUNT = 256,
+    parameter PCIE_TAG_COUNT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 0,
@@ -417,6 +421,7 @@ parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
 parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
 
 wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_req_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_req_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_req_tlp_hdr;
 wire [TLP_SEG_COUNT*3-1:0]                    pcie_rx_req_tlp_bar_id;
 wire [TLP_SEG_COUNT*8-1:0]                    pcie_rx_req_tlp_func_num;
@@ -426,6 +431,7 @@ wire [TLP_SEG_COUNT-1:0]                      pcie_rx_req_tlp_eop;
 wire                                          pcie_rx_req_tlp_ready;
 
 wire [TLP_DATA_WIDTH-1:0]                     pcie_rx_cpl_tlp_data;
+wire [TLP_STRB_WIDTH-1:0]                     pcie_rx_cpl_tlp_strb;
 wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_rx_cpl_tlp_hdr;
 wire [TLP_SEG_COUNT*4-1:0]                    pcie_rx_cpl_tlp_error;
 wire [TLP_SEG_COUNT-1:0]                      pcie_rx_cpl_tlp_valid;
@@ -463,12 +469,12 @@ wire [TLP_SEG_COUNT-1:0]                      pcie_tx_cpl_tlp_sop;
 wire [TLP_SEG_COUNT-1:0]                      pcie_tx_cpl_tlp_eop;
 wire                                          pcie_tx_cpl_tlp_ready;
 
-wire [TLP_DATA_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_data;
-wire [TLP_STRB_WIDTH-1:0]                     pcie_tx_msix_wr_req_tlp_strb;
-wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0]        pcie_tx_msix_wr_req_tlp_hdr;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_valid;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_sop;
-wire [TLP_SEG_COUNT-1:0]                      pcie_tx_msix_wr_req_tlp_eop;
+wire [31:0]                                   pcie_tx_msix_wr_req_tlp_data;
+wire                                          pcie_tx_msix_wr_req_tlp_strb;
+wire [TLP_HDR_WIDTH-1:0]                      pcie_tx_msix_wr_req_tlp_hdr;
+wire                                          pcie_tx_msix_wr_req_tlp_valid;
+wire                                          pcie_tx_msix_wr_req_tlp_sop;
+wire                                          pcie_tx_msix_wr_req_tlp_eop;
 wire                                          pcie_tx_msix_wr_req_tlp_ready;
 
 wire [7:0]   pcie_tx_fc_ph_av;
@@ -486,6 +492,10 @@ pcie_us_if #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .TLP_DATA_WIDTH(TLP_DATA_WIDTH),
     .TLP_STRB_WIDTH(TLP_STRB_WIDTH),
@@ -612,6 +622,7 @@ pcie_if_inst (
      * TLP output (request to BAR)
      */
     .rx_req_tlp_data(pcie_rx_req_tlp_data),
+    .rx_req_tlp_strb(pcie_rx_req_tlp_strb),
     .rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
     .rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
     .rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
@@ -624,6 +635,7 @@ pcie_if_inst (
      * TLP output (completion to DMA)
      */
     .rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
+    .rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
     .rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
     .rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
     .rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
@@ -868,6 +880,7 @@ core_pcie_inst (
      * TLP input (request to BAR)
      */
     .pcie_rx_req_tlp_data(pcie_rx_req_tlp_data),
+    .pcie_rx_req_tlp_strb(pcie_rx_req_tlp_strb),
     .pcie_rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
     .pcie_rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
     .pcie_rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
@@ -880,6 +893,7 @@ core_pcie_inst (
      * TLP input (completion to DMA)
      */
     .pcie_rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
+    .pcie_rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
     .pcie_rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
     .pcie_rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
     .pcie_rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
index ec1ad8384..26d4d79b0 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile
@@ -105,6 +105,9 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -203,7 +206,7 @@ export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE
 export PARAM_RAM_PIPELINE ?= 2
 
 # PCIe interface configuration
-export PARAM_SEG_COUNT ?= 1
+export PARAM_SEG_COUNT ?= 2
 export PARAM_SEG_DATA_WIDTH ?= 256
 export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
 export PARAM_TX_SEQ_NUM_WIDTH ?= 6
diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
index b8455a4e9..59953f243 100644
--- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
+++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
@@ -607,9 +607,9 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
             (2, 1, 256, 64, 64, 1),
             (1, 2, 256, 64, 64, 1),
             (1, 1, 256, 64, 128, 1),
-            # (1, 1, 512, 64, 64, 1),
-            # (1, 1, 512, 64, 128, 1),
-            # (1, 1, 512, 512, 512, 1),
+            (1, 1, 512, 64, 64, 1),
+            (1, 1, 512, 64, 128, 1),
+            (1, 1, 512, 512, 512, 1),
         ])
 def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
         axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
@@ -685,6 +685,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile
index e2a6a1173..7b4d2c2f4 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile
@@ -105,6 +105,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -208,7 +210,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
index 475e497c5..03f15e904 100644
--- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
@@ -82,11 +82,11 @@ class TB(object):
             # pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -759,6 +759,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -863,7 +865,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
index 5129a2409..9354ba0b8 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
@@ -107,6 +107,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
index 7aea6817b..50326cf10 100644
--- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
+++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
@@ -82,11 +82,11 @@ class TB(object):
             # pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -814,6 +814,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -918,7 +920,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
     parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
index 899aacb82..94e53d7f6 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
@@ -81,6 +81,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
index 0cf1428b5..874a0b7dc 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
index 8f43b9c8e..fc821f4d2 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
@@ -83,6 +83,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
index 5e3cb2681..f4ad640a1 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index 6da304001..b1e54b249 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
index dfcbe48ff..3bdb1bd4e 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1845,6 +1849,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
index 563aa5cf1..fba01a201 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -917,6 +921,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
index e9ac2fe6a..e9a4bf676 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
index 1d3376c81..fd6cc477c 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -686,6 +686,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -789,7 +791,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
index 6221b0417..26a4b0f33 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
index d118f1335..5603af5ce 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
index 6221b0417..26a4b0f33 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
index cd98c9066..9f56d5388 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
index 18fa7c040..6c424b71a 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
@@ -100,6 +100,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
index b3c0fff24..73b370bff 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -177,8 +177,8 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
-dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+dict set params AXIL_CTRL_ADDR_WIDTH "25"
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index 6da304001..b1e54b249 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
index f908f4679..51e6862ac 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1445,6 +1449,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
index bddb47350..e6570feaa 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1189,6 +1193,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
index 2e0af9d81..157e152e0 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
index 6aa2c5a11..f8e2d45b5 100644
--- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -753,6 +753,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -855,7 +857,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
index c899eb077..1807da339 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile
@@ -84,6 +84,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
index c5025970a..b0c167d97 100644
--- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index ad54476a2..be77eac07 100644
--- a/fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
index 06a08c040..83163a0a9 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1978,6 +1982,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
index 68035d4ff..45d91ed2e 100644
--- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -925,6 +929,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
index b7b6241e7..1f7f9befc 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
index 2e8862cc4..a6d619a8b 100644
--- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -686,6 +686,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -789,7 +791,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
index ff79a9f1b..1d3f870ab 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile
@@ -102,6 +102,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
index 6ca05a523..4f27cf7d0 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
index ff79a9f1b..1d3f870ab 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
@@ -102,6 +102,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
index f1e5e0227..65b6a22fd 100644
--- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index ad54476a2..be77eac07 100644
--- a/fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
index 39273b2db..f784f3b5f 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1578,6 +1582,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
index 03f3d3042..fc50dbffd 100644
--- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1198,6 +1202,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
index 2eaf4c217..1a10990f1 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
index f117589f7..f5fdb95f6 100644
--- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -753,6 +753,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -855,7 +857,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
index 3dd7aef56..7c4f5a0ab 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile
@@ -84,6 +84,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
index 1bcb6fe68..7e14522fe 100644
--- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index ae1d6e4b9..4d2909eb6 100644
--- a/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU250/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
index 006c4d22f..c33b8f19f 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1978,6 +1982,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
index d009493c2..576dcb72d 100644
--- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -925,6 +929,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
index b7b6241e7..1f7f9befc 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
index 2e8862cc4..a6d619a8b 100644
--- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -686,6 +686,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -789,7 +791,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
index ee870c2f8..a54dcd880 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile
@@ -102,6 +102,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
index af23d332a..0b2909516 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
index ee870c2f8..a54dcd880 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
@@ -102,6 +102,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
index b5bcd4ff7..9a8b9423e 100644
--- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index ae1d6e4b9..4d2909eb6 100644
--- a/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU250/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
index e2d74687a..f97c64012 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1578,6 +1582,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
index f67749164..645bedb45 100644
--- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1198,6 +1202,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
index 2eaf4c217..1a10990f1 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
index f117589f7..f5fdb95f6 100644
--- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -753,6 +753,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -855,7 +857,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
index 887da0482..4c44b1207 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile
@@ -83,6 +83,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
index 9004cdd63..390f91b6a 100644
--- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
index 7df76db6b..fdfdad424 100644
--- a/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU280/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name p
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
index 1f619bcea..0d28359fe 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1875,6 +1879,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
index 5ac9315aa..a98d48884 100644
--- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -801,6 +805,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
index 6ac8ec869..1ea402c28 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
index c475e7297..a061e21e9 100644
--- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -675,6 +675,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -778,7 +780,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
index 4788fa9fb..06b9c16c4 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile
@@ -101,6 +101,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
index c563cf57e..b2c0093b8 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
index 4788fa9fb..06b9c16c4 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
@@ -101,6 +101,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
index 566c39d29..01358114f 100644
--- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU280/fpga_25g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU280/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
index 7df76db6b..fdfdad424 100644
--- a/fpga/mqnic/AU280/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU280/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name p
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
index 8b2ffdfcf..c9d593c60 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1483,6 +1487,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
index ed2076362..3005f92ce 100644
--- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1074,6 +1078,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
index 47f7f8f0d..b52afe443 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
index ebcfef0aa..523756232 100644
--- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -742,6 +742,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -844,7 +846,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
index 7c075932f..96453015e 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile
@@ -83,6 +83,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
index acfc62709..50d7184c9 100644
--- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
index ac472994c..0d955e872 100644
--- a/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU50/fpga_100g/ip/pcie4c_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name p
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
index 1d498c653..3d50675ba 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1440,6 +1444,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
index 718faa7fb..cb665f7ac 100644
--- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -791,6 +795,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
index 3b5a5392e..02428c7ae 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
index ed2a8e61c..533959b38 100644
--- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -635,6 +635,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -738,7 +740,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
index 988b0d4ae..2a7a5ecb8 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile
@@ -101,6 +101,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
index 679e25a89..94ee22984 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
index 988b0d4ae..2a7a5ecb8 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
@@ -101,6 +101,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
index bc8ec7f7b..7558165b2 100644
--- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl b/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
index ac472994c..0d955e872 100644
--- a/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
+++ b/fpga/mqnic/AU50/fpga_25g/ip/pcie4c_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name p
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
index 35d2ae350..6a454e51a 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
@@ -136,10 +136,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1243,6 +1247,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
index 839c70224..791c02ab2 100644
--- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -983,6 +987,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
index f8393ed19..03842a909 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
index ce7a5af66..c2a22b176 100644
--- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -662,6 +662,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -764,7 +766,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
index 7045bcb3d..c57f4be34 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
index 7ffff0133..bf401410e 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
@@ -169,7 +169,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
index cf9297045..ad7b182a3 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
index 9af30bf1f..e3a1467fd 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
@@ -169,7 +169,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl
index c559c5264..1b6e5ed0a 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/pcie3_ultrascale_0.tcl
@@ -4,7 +4,7 @@ create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pci
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
index c9eb1976f..ce98d8bc5 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
@@ -133,6 +133,10 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1431,6 +1435,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
index 46d209dfb..6a7bf4729 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
@@ -143,6 +143,10 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1217,6 +1221,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
index 5e4e79a44..7b0fd0e1d 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
index 21c33af01..493fc02ad 100644
--- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
@@ -81,7 +81,7 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            rc_straddle=False,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -717,6 +717,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
index 9eadc55b4..fdf639fd9 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
@@ -97,6 +97,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
index 97b2d1744..09bea28ac 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/ip/pcie3_7x_0.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/ip/pcie3_7x_0.tcl
index b4ef44e9f..1bde475fb 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/ip/pcie3_7x_0.tcl
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/ip/pcie3_7x_0.tcl
@@ -6,7 +6,7 @@ set_property -dict [list \
     CONFIG.pcie_blk_locn {X0Y1} \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {false} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
index d203d9f17..34091a6e2 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
@@ -130,6 +130,10 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1386,6 +1390,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
index c715dd778..78c6c9f67 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
@@ -140,6 +140,10 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -819,6 +823,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
index 943b6f02d..3ef82075d 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
@@ -115,6 +115,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index 3638756f3..517961a32 100644
--- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -81,7 +81,7 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            rc_straddle=False,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -639,6 +639,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile
index cce005808..0cebef3a0 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile
+++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl
index 123095365..b5b9a314f 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl
+++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/ip/pcie3_ultrascale_0.tcl b/fpga/mqnic/Nexus_K35_S/fpga/ip/pcie3_ultrascale_0.tcl
index 2246b6641..7cb740552 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/ip/pcie3_ultrascale_0.tcl
+++ b/fpga/mqnic/Nexus_K35_S/fpga/ip/pcie3_ultrascale_0.tcl
@@ -4,7 +4,7 @@ create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pci
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
index d224fee00..399b10f64 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
+++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
@@ -130,6 +130,10 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1101,6 +1105,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
index 823f2edd0..86142710b 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
@@ -140,6 +140,10 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -973,6 +977,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
index 545016151..aa09c6aed 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
index 98264162f..314120c9c 100644
--- a/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
@@ -81,7 +81,7 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            rc_straddle=False,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -628,6 +628,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
index 7132bbd54..f7beba9ae 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
index fbee8001c..9fccf1798 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
index 7132bbd54..f7beba9ae 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
index 825c37675..8566c7aad 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index 7485c5677..716532cd8 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,7 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
index 1bd3fba87..1f9232648 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1373,6 +1377,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
index 37ba4061d..c9d011899 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1253,6 +1257,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
index 853c3ce64..74159051d 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
index 549c380b6..9ea449e8c 100644
--- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -757,6 +757,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -859,7 +861,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 256
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile
index 7132bbd54..f7beba9ae 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl
index 510d03dba..d5a8e7cd2 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile
index 7132bbd54..f7beba9ae 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl
index d0e49390b..a56e7761b 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index 3856af642..64705b331 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,7 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
index 69f44d9d8..78a8e3286 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1142,6 +1146,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
index 3224e83ff..78f667de2 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1071,6 +1075,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
index 853c3ce64..74159051d 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
index 5d8454b53..e24eb823f 100644
--- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -657,6 +657,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -759,7 +761,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 256
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
index 0b972535d..e052d689a 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
@@ -97,6 +97,9 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
index 7e5fe8c73..71e70e965 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
@@ -97,6 +97,9 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
index f541f95c0..ba6732f5e 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
@@ -115,6 +115,9 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
index e2956afa7..6bfb7dd58 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -662,6 +662,9 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
index 82a218d16..bd525e022 100644
--- a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
index cb77d6540..213c7c7ca 100644
--- a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
+++ b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl
@@ -169,7 +169,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU108/fpga_10g/ip/pcie3_ultrascale_0.tcl b/fpga/mqnic/VCU108/fpga_10g/ip/pcie3_ultrascale_0.tcl
index d842c854c..d5aa67ced 100644
--- a/fpga/mqnic/VCU108/fpga_10g/ip/pcie3_ultrascale_0.tcl
+++ b/fpga/mqnic/VCU108/fpga_10g/ip/pcie3_ultrascale_0.tcl
@@ -4,7 +4,7 @@ create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pci
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
-    CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
     CONFIG.axisten_if_width {256_bit} \
     CONFIG.extended_tag_field {true} \
     CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
index 8a1702dc7..14efe28f8 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v
@@ -133,6 +133,10 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1203,6 +1207,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
index b06994b25..4e249e02b 100644
--- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
@@ -143,6 +143,10 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
     parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
     parameter AXIS_PCIE_CC_USER_WIDTH = 33,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = 4,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
@@ -1023,6 +1027,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
index d2611bfe6..7bbfc04d0 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
index a6115bfbe..77f7a42d6 100644
--- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -81,7 +81,7 @@ class TB(object):
             pcie_link_width=8,
             user_clk_frequency=250e6,
             alignment="dword",
-            rc_straddle=False,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -649,6 +649,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
index 8be064c1b..4fecdd07a 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
@@ -81,6 +81,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
index b9b346a99..651fc9be5 100644
--- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU118/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU118/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index efa55b8bd..7400305e6 100644
--- a/fpga/mqnic/VCU118/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/VCU118/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
index f856153d6..35a63327b 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1832,6 +1836,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
index 9fbe210ab..8f7673bdf 100644
--- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -893,6 +897,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
index a55d155cb..194679b71 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
index 539020a2e..bdb0fd4e6 100644
--- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -690,6 +690,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -793,7 +795,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
index e81a54b78..aebfc96be 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
index cc40facc6..235759b89 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
index e81a54b78..aebfc96be 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
index 1f47f435a..95dd3192b 100644
--- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU118/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU118/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index efa55b8bd..7400305e6 100644
--- a/fpga/mqnic/VCU118/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/VCU118/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
index 86d820e7a..cd123131c 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1431,6 +1435,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
index 980812626..9d493dbd9 100644
--- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1166,6 +1170,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
index 39a800c0c..0f60f4f26 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
index 086b97ad1..ed2010fbb 100644
--- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -757,6 +757,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -859,7 +861,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
index 2432df181..f2a24f8e9 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
@@ -81,6 +81,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
index e8280b654..7523898f0 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index b218a3648..f01c3746f 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/VCU1525/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
index 94eaa58d2..438eaf2a1 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1823,6 +1827,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
index ef177c19b..cda6fa500 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -848,6 +852,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
index b7b6241e7..1f7f9befc 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
index 7c3668edd..f5bbe40d3 100644
--- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -684,6 +684,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -787,7 +789,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
index 14de5ba5e..e0c8907d2 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
index fba43c6c0..fa74c7c18 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
index 14de5ba5e..e0c8907d2 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
index e70f90a2d..625c3995d 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index b218a3648..f01c3746f 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/VCU1525/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
index 309de83d0..22e84a04b 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1423,6 +1427,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
index f81c3ed43..b034026c3 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1121,6 +1125,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
index 2eaf4c217..1a10990f1 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
index 675c6f770..16e731b6b 100644
--- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -751,6 +751,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -853,7 +855,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
index 7de147c1d..1521f1598 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
@@ -80,6 +80,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
index ac124c139..6678966a2 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -166,7 +166,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "25"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "25"
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/XUPP3R/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index 35c04eeca..7b0e7086f 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
index f1aafc883..157ba2187 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -2758,6 +2762,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
index 441167013..c9291b060 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1104,6 +1108,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
index 83ba80f0b..9305266ef 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
@@ -108,6 +108,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -210,7 +212,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
index 5f9566bf8..7143f4ed9 100644
--- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -754,6 +754,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -857,7 +859,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
index 963452754..1bb6b65ba 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
index fa9677e0d..838dd681f 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "25"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "25"
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
index 963452754..1bb6b65ba 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
@@ -98,6 +98,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
index c6548d907..418cc3ae8 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -178,7 +178,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "25"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "25"
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index 35c04eeca..7b0e7086f 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/XUPP3R/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
index 3f66daf4f..350e72444 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1958,6 +1962,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
index 032586c9b..3634b0725 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1540,6 +1544,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
index 8184f84eb..7aa1e2582 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
index 99203cae0..fb610afcf 100644
--- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -901,6 +901,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -1003,7 +1005,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
index 4a9ec170a..6b0d8a0aa 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
@@ -99,6 +99,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
index ce18728b8..ee57dbdf1 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
+++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl
@@ -155,7 +155,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -169,7 +169,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
 dict set params AXIL_CTRL_ADDR_WIDTH "24"
- 
+
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
 dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
index 79e78b915..9653255fd 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
index 83ee12e3b..0ba2037c6 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
+++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
index 6271b1d2e..89f0f63c1 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
@@ -116,6 +116,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -217,7 +219,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 128
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
index 7a8839836..0d4240634 100644
--- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=4,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -651,6 +651,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -753,7 +755,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 128
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
index cc563f532..ccadce3e7 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
@@ -82,6 +82,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
index fcf673374..f2a723f07 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
index c5864c936..0244630ab 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
@@ -83,6 +83,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
index 4bac4e819..6ebcecfa6 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -159,7 +159,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
index 596aed31f..70682e42a 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile
@@ -86,6 +86,9 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
index 35e3ee022..2f6f15494 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
index 1efe0dd67..544f42a01 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile
@@ -84,6 +84,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
index 64031adb4..6de71a013 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl
@@ -152,7 +152,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/fb2CG/fpga_100g/ip/pcie4_uscale_plus_0.tcl
index 068926f8e..be518e89f 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/fb2CG/fpga_100g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
index 003b506cf..8e49ab186 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
@@ -130,10 +130,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1861,6 +1865,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
index 4d6605ca4..2763e3073 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
@@ -136,10 +136,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -950,6 +954,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
index 6950f94ac..ab11d90fe 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile
@@ -109,6 +109,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -211,7 +213,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
index 8e6d409b3..7697cf8c8 100644
--- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -691,6 +691,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -794,7 +796,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
index 923ddcabc..64c384247 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile
@@ -100,6 +100,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
index 118994ef7..948a0b23f 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
index 923ddcabc..64c384247 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile
@@ -100,6 +100,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
index 721f33b55..b8b1a8fba 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
index 22d20db07..9c45fbbd4 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile
@@ -101,6 +101,8 @@ SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
 SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
 SYN_FILES += lib/pcie/rtl/pcie_msix.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
 SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
index f44c10574..178d82b95 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl
@@ -164,7 +164,7 @@ dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_S
 dict set params RAM_PIPELINE "2"
 
 # PCIe interface configuration
-dict set params PCIE_TAG_COUNT "64"
+dict set params PCIE_TAG_COUNT "256"
 dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
 dict set params PCIE_DMA_READ_TX_LIMIT "16"
 dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
@@ -177,7 +177,7 @@ dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
 
 # AXI lite interface configuration (control)
 dict set params AXIL_CTRL_DATA_WIDTH "32"
-dict set params AXIL_CTRL_ADDR_WIDTH "24"
+dict set params AXIL_CTRL_ADDR_WIDTH "25"
 
 # AXI lite interface configuration (application control)
 dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
diff --git a/fpga/mqnic/fb2CG/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/fb2CG/fpga_25g/ip/pcie4_uscale_plus_0.tcl
index 068926f8e..be518e89f 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/ip/pcie4_uscale_plus_0.tcl
+++ b/fpga/mqnic/fb2CG/fpga_25g/ip/pcie4_uscale_plus_0.tcl
@@ -4,7 +4,9 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc
 set_property -dict [list \
     CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
     CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
-    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \
+    CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \
     CONFIG.axisten_if_enable_client_tag {true} \
     CONFIG.axisten_if_width {512_bit} \
     CONFIG.extended_tag_field {true} \
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
index b83cbec21..f3f381004 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
@@ -133,10 +133,14 @@ module fpga #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1473,6 +1477,10 @@ fpga_core #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
index 806369ca9..6d45906c3 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
@@ -143,10 +143,14 @@ module fpga_core #
     parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137,
     parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
     parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256,
+    parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
+    parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512,
     parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
     parameter PF_COUNT = 1,
     parameter VF_COUNT = 0,
-    parameter PCIE_TAG_COUNT = 64,
+    parameter PCIE_TAG_COUNT = 256,
     parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
     parameter PCIE_DMA_READ_TX_LIMIT = 16,
     parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
@@ -1222,6 +1226,10 @@ mqnic_core_pcie_us #(
     .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
     .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
     .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RC_STRADDLE(RC_STRADDLE),
+    .RQ_STRADDLE(RQ_STRADDLE),
+    .CQ_STRADDLE(CQ_STRADDLE),
+    .CC_STRADDLE(CC_STRADDLE),
     .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
     .PF_COUNT(PF_COUNT),
     .VF_COUNT(VF_COUNT),
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
index 3df07e7cd..b7299ccaf 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile
@@ -117,6 +117,8 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
 VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
@@ -218,7 +220,7 @@ export PARAM_RAM_PIPELINE ?= 2
 export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
 export PARAM_PF_COUNT ?= 1
 export PARAM_VF_COUNT ?= 0
-export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_PCIE_TAG_COUNT ?= 256
 export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
 export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
 export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
index 8cd7c32e2..1d5dc7ced 100644
--- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -81,11 +81,11 @@ class TB(object):
             pcie_link_width=16,
             user_clk_frequency=250e6,
             alignment="dword",
-            cq_straddle=False,
-            cc_straddle=False,
-            rq_straddle=False,
-            rc_straddle=False,
-            rc_4tlp_straddle=False,
+            cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1,
+            cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1,
+            rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1,
+            rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1,
+            rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2,
             pf_count=1,
             max_payload_size=1024,
             enable_client_tag=True,
@@ -756,6 +756,8 @@ def test_fpga_core(request):
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
         os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
         os.path.join(pcie_rtl_dir, "pcie_msix.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
         os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
@@ -858,7 +860,7 @@ def test_fpga_core(request):
     parameters['AXIS_PCIE_DATA_WIDTH'] = 512
     parameters['PF_COUNT'] = 1
     parameters['VF_COUNT'] = 0
-    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['PCIE_TAG_COUNT'] = 256
     parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
     parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
     parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
diff --git a/tox.ini b/tox.ini
index c59708d20..a4cbdc0df 100644
--- a/tox.ini
+++ b/tox.ini
@@ -18,7 +18,7 @@ deps =
     cocotb-test == 0.2.1
     cocotbext-axi == 0.1.18
     cocotbext-eth == 0.1.18
-    cocotbext-pcie == 0.2.2
+    cocotbext-pcie == 0.2.6
     scapy == 2.4.5
 
 commands =