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Use quad wrappers in AU50 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
66987c8f62
commit
72de6c653a
@ -90,22 +90,22 @@ set_output_delay 0 [get_ports {hbm_cattrip}]
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#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
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# QSFP28 Interfaces
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set_property -dict {LOC J45 } [get_ports qsfp_rx1_p] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC J46 } [get_ports qsfp_rx1_n] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC D42 } [get_ports qsfp_tx1_p] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC D43 } [get_ports qsfp_tx1_n] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC G45 } [get_ports qsfp_rx2_p] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC G46 } [get_ports qsfp_rx2_n] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC C40 } [get_ports qsfp_tx2_p] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC C41 } [get_ports qsfp_tx2_n] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC F43 } [get_ports qsfp_rx3_p] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC F44 } [get_ports qsfp_rx3_n] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC B42 } [get_ports qsfp_tx3_p] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC B43 } [get_ports qsfp_tx3_n] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC E45 } [get_ports qsfp_rx4_p] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC E46 } [get_ports qsfp_rx4_n] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC A40 } [get_ports qsfp_tx4_p] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC A41 } [get_ports qsfp_tx4_n] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC J45 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC J46 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC D42 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC D43 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC G45 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC G46 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC C40 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC C41 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC F43 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC F44 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC B42 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC B43 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC E45 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC E46 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC A40 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC A41 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
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set_property -dict {LOC N36 } [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_131 from SI5394 OUT0
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set_property -dict {LOC N37 } [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_131 from SI5394 OUT0
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#set_property -dict {LOC M38 } [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_131 from SI5394 OUT2
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@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus
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SYN_FILES = rtl/fpga.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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395
example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
395
example/AU50/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
@ -0,0 +1,395 @@
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/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Transceiver and PHY quad wrapper
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*/
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module eth_xcvr_phy_quad_wrapper #
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(
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parameter COUNT = 4,
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parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter HDR_WIDTH = 2,
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parameter PRBS31_ENABLE = 0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 1,
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parameter BITSLIP_LOW_CYCLES = 8,
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parameter COUNT_125US = 125000/6.4
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)
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(
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input wire xcvr_ctrl_clk,
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input wire xcvr_ctrl_rst,
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/*
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* Common
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*/
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output wire xcvr_gtpowergood_out,
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/*
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* PLL
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*/
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input wire xcvr_gtrefclk00_in,
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/*
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* Serial data
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*/
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output wire [COUNT-1:0] xcvr_txp,
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output wire [COUNT-1:0] xcvr_txn,
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input wire [COUNT-1:0] xcvr_rxp,
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input wire [COUNT-1:0] xcvr_rxn,
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/*
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* PHY connections
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*/
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output wire phy_1_tx_clk,
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output wire phy_1_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
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output wire phy_1_rx_clk,
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output wire phy_1_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
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output wire phy_1_tx_bad_block,
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output wire [6:0] phy_1_rx_error_count,
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output wire phy_1_rx_bad_block,
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output wire phy_1_rx_sequence_error,
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output wire phy_1_rx_block_lock,
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output wire phy_1_rx_high_ber,
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output wire phy_1_rx_status,
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input wire phy_1_cfg_tx_prbs31_enable,
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input wire phy_1_cfg_rx_prbs31_enable,
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output wire phy_2_tx_clk,
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output wire phy_2_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
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output wire phy_2_rx_clk,
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output wire phy_2_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
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output wire phy_2_tx_bad_block,
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output wire [6:0] phy_2_rx_error_count,
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output wire phy_2_rx_bad_block,
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output wire phy_2_rx_sequence_error,
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output wire phy_2_rx_block_lock,
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output wire phy_2_rx_high_ber,
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output wire phy_2_rx_status,
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input wire phy_2_cfg_tx_prbs31_enable,
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input wire phy_2_cfg_rx_prbs31_enable,
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output wire phy_3_tx_clk,
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output wire phy_3_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
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output wire phy_3_rx_clk,
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output wire phy_3_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
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output wire phy_3_tx_bad_block,
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output wire [6:0] phy_3_rx_error_count,
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output wire phy_3_rx_bad_block,
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output wire phy_3_rx_sequence_error,
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output wire phy_3_rx_block_lock,
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output wire phy_3_rx_high_ber,
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output wire phy_3_rx_status,
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input wire phy_3_cfg_tx_prbs31_enable,
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input wire phy_3_cfg_rx_prbs31_enable,
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output wire phy_4_tx_clk,
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output wire phy_4_tx_rst,
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input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
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input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
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output wire phy_4_rx_clk,
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output wire phy_4_rx_rst,
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output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
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output wire phy_4_tx_bad_block,
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output wire [6:0] phy_4_rx_error_count,
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output wire phy_4_rx_bad_block,
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output wire phy_4_rx_sequence_error,
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output wire phy_4_rx_block_lock,
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output wire phy_4_rx_high_ber,
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output wire phy_4_rx_status,
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input wire phy_4_cfg_tx_prbs31_enable,
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input wire phy_4_cfg_rx_prbs31_enable
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);
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generate
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wire xcvr_qpll0lock;
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wire xcvr_qpll0clk;
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wire xcvr_qpll0refclk;
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if (COUNT > 0) begin : phy1
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_1 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
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// PLL out
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.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
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.xcvr_qpll0lock_out(xcvr_qpll0lock),
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.xcvr_qpll0clk_out(xcvr_qpll0clk),
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.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(xcvr_txp[0]),
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.xcvr_txn(xcvr_txn[0]),
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.xcvr_rxp(xcvr_rxp[0]),
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.xcvr_rxn(xcvr_rxn[0]),
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// PHY connections
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.phy_tx_clk(phy_1_tx_clk),
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.phy_tx_rst(phy_1_tx_rst),
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.phy_xgmii_txd(phy_1_xgmii_txd),
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.phy_xgmii_txc(phy_1_xgmii_txc),
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.phy_rx_clk(phy_1_rx_clk),
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.phy_rx_rst(phy_1_rx_rst),
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.phy_xgmii_rxd(phy_1_xgmii_rxd),
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.phy_xgmii_rxc(phy_1_xgmii_rxc),
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.phy_tx_bad_block(phy_1_tx_bad_block),
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.phy_rx_error_count(phy_1_rx_error_count),
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.phy_rx_bad_block(phy_1_rx_bad_block),
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.phy_rx_sequence_error(phy_1_rx_sequence_error),
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.phy_rx_block_lock(phy_1_rx_block_lock),
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.phy_rx_high_ber(phy_1_rx_high_ber),
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.phy_rx_status(phy_1_rx_status),
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.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
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.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
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);
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end
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if (COUNT > 1) begin : phy2
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0),
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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eth_xcvr_phy_2 (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(xcvr_qpll0lock),
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.xcvr_qpll0clk_in(xcvr_qpll0clk),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
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// Serial data
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.xcvr_txp(xcvr_txp[1]),
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.xcvr_txn(xcvr_txn[1]),
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.xcvr_rxp(xcvr_rxp[1]),
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.xcvr_rxn(xcvr_rxn[1]),
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// PHY connections
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.phy_tx_clk(phy_2_tx_clk),
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.phy_tx_rst(phy_2_tx_rst),
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.phy_xgmii_txd(phy_2_xgmii_txd),
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.phy_xgmii_txc(phy_2_xgmii_txc),
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.phy_rx_clk(phy_2_rx_clk),
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.phy_rx_rst(phy_2_rx_rst),
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.phy_xgmii_rxd(phy_2_xgmii_rxd),
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.phy_xgmii_rxc(phy_2_xgmii_rxc),
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.phy_tx_bad_block(phy_2_tx_bad_block),
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.phy_rx_error_count(phy_2_rx_error_count),
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.phy_rx_bad_block(phy_2_rx_bad_block),
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.phy_rx_sequence_error(phy_2_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_2_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_2_rx_high_ber),
|
||||
.phy_rx_status(phy_2_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (COUNT > 2) begin : phy3
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_3 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[2]),
|
||||
.xcvr_txn(xcvr_txn[2]),
|
||||
.xcvr_rxp(xcvr_rxp[2]),
|
||||
.xcvr_rxn(xcvr_rxn[2]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_3_tx_clk),
|
||||
.phy_tx_rst(phy_3_tx_rst),
|
||||
.phy_xgmii_txd(phy_3_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_3_xgmii_txc),
|
||||
.phy_rx_clk(phy_3_rx_clk),
|
||||
.phy_rx_rst(phy_3_rx_rst),
|
||||
.phy_xgmii_rxd(phy_3_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_3_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_3_tx_bad_block),
|
||||
.phy_rx_error_count(phy_3_rx_error_count),
|
||||
.phy_rx_bad_block(phy_3_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_3_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_3_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_3_rx_high_ber),
|
||||
.phy_rx_status(phy_3_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (COUNT > 3) begin : phy4
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_4 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[3]),
|
||||
.xcvr_txn(xcvr_txn[3]),
|
||||
.xcvr_rxp(xcvr_rxp[3]),
|
||||
.xcvr_rxn(xcvr_rxn[3]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_4_tx_clk),
|
||||
.phy_tx_rst(phy_4_tx_rst),
|
||||
.phy_xgmii_txd(phy_4_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_4_xgmii_txc),
|
||||
.phy_rx_clk(phy_4_rx_clk),
|
||||
.phy_rx_rst(phy_4_rx_rst),
|
||||
.phy_xgmii_rxd(phy_4_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_4_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_4_tx_bad_block),
|
||||
.phy_rx_error_count(phy_4_rx_error_count),
|
||||
.phy_rx_bad_block(phy_4_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_4_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_4_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_4_rx_high_ber),
|
||||
.phy_rx_status(phy_4_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
Copyright (c) 2021-2023 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper #
|
||||
*/
|
||||
input wire xcvr_gtrefclk00_in,
|
||||
output wire xcvr_qpll0lock_out,
|
||||
output wire xcvr_qpll0outclk_out,
|
||||
output wire xcvr_qpll0outrefclk_out,
|
||||
output wire xcvr_qpll0clk_out,
|
||||
output wire xcvr_qpll0refclk_out,
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper #
|
||||
output wire phy_rx_sequence_error,
|
||||
output wire phy_rx_block_lock,
|
||||
output wire phy_rx_high_ber,
|
||||
output wire phy_rx_status,
|
||||
input wire phy_cfg_tx_prbs31_enable,
|
||||
input wire phy_cfg_rx_prbs31_enable
|
||||
);
|
||||
@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr
|
||||
// PLL
|
||||
.gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.qpll0outclk_out(xcvr_qpll0outclk_out),
|
||||
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
|
||||
.qpll0outclk_out(xcvr_qpll0clk_out),
|
||||
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
|
||||
|
||||
// Serial data
|
||||
.gtytxp_out(xcvr_txp),
|
||||
@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
assign xcvr_qpll0reset_out = 1'b0;
|
||||
|
||||
end else begin : xcvr
|
||||
|
||||
eth_xcvr_gt_channel
|
||||
@ -234,6 +237,10 @@ end else begin : xcvr
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
assign xcvr_qpll0lock_out = 1'b0;
|
||||
assign xcvr_qpll0clk_out = 1'b0;
|
||||
assign xcvr_qpll0refclk_out = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
@ -290,6 +297,7 @@ phy_inst (
|
||||
.rx_sequence_error(phy_rx_sequence_error),
|
||||
.rx_block_lock(phy_rx_block_lock),
|
||||
.rx_high_ber(phy_rx_high_ber),
|
||||
.rx_status(phy_rx_status),
|
||||
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
@ -43,22 +43,10 @@ module fpga (
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire [3:0] qsfp_tx_p,
|
||||
output wire [3:0] qsfp_tx_n,
|
||||
input wire [3:0] qsfp_rx_p,
|
||||
input wire [3:0] qsfp_rx_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
@ -226,196 +214,103 @@ BUFG_GT bufg_gt_refclk_inst (
|
||||
.O (qsfp_mgt_refclk_0_bufg)
|
||||
);
|
||||
|
||||
wire qsfp_qpll0lock;
|
||||
wire qsfp_qpll0outclk;
|
||||
wire qsfp_qpll0outrefclk;
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(1)
|
||||
eth_xcvr_phy_quad_wrapper #(
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp_phy_1_inst (
|
||||
qsfp_phy_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood),
|
||||
|
||||
// PLL out
|
||||
/*
|
||||
* PLL
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
|
||||
.xcvr_qpll0lock_out(qsfp_qpll0lock),
|
||||
.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(1'b0),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(1'b0),
|
||||
.xcvr_qpll0refclk_in(1'b0),
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx1_p),
|
||||
.xcvr_txn(qsfp_tx1_n),
|
||||
.xcvr_rxp(qsfp_rx1_p),
|
||||
.xcvr_rxn(qsfp_rx1_n),
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
.phy_1_tx_clk(qsfp_tx_clk_1_int),
|
||||
.phy_1_tx_rst(qsfp_tx_rst_1_int),
|
||||
.phy_1_xgmii_txd(qsfp_txd_1_int),
|
||||
.phy_1_xgmii_txc(qsfp_txc_1_int),
|
||||
.phy_1_rx_clk(qsfp_rx_clk_1_int),
|
||||
.phy_1_rx_rst(qsfp_rx_rst_1_int),
|
||||
.phy_1_xgmii_rxd(qsfp_rxd_1_int),
|
||||
.phy_1_xgmii_rxc(qsfp_rxc_1_int),
|
||||
.phy_1_tx_bad_block(),
|
||||
.phy_1_rx_error_count(),
|
||||
.phy_1_rx_bad_block(),
|
||||
.phy_1_rx_sequence_error(),
|
||||
.phy_1_rx_block_lock(qsfp_rx_block_lock_1),
|
||||
.phy_1_rx_status(),
|
||||
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_1_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_1_int),
|
||||
.phy_xgmii_txd(qsfp_txd_1_int),
|
||||
.phy_xgmii_txc(qsfp_txc_1_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_1_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_1_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_1_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_1_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_1),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
.phy_2_tx_clk(qsfp_tx_clk_2_int),
|
||||
.phy_2_tx_rst(qsfp_tx_rst_2_int),
|
||||
.phy_2_xgmii_txd(qsfp_txd_2_int),
|
||||
.phy_2_xgmii_txc(qsfp_txc_2_int),
|
||||
.phy_2_rx_clk(qsfp_rx_clk_2_int),
|
||||
.phy_2_rx_rst(qsfp_rx_rst_2_int),
|
||||
.phy_2_xgmii_rxd(qsfp_rxd_2_int),
|
||||
.phy_2_xgmii_rxc(qsfp_rxc_2_int),
|
||||
.phy_2_tx_bad_block(),
|
||||
.phy_2_rx_error_count(),
|
||||
.phy_2_rx_bad_block(),
|
||||
.phy_2_rx_sequence_error(),
|
||||
.phy_2_rx_block_lock(qsfp_rx_block_lock_2),
|
||||
.phy_2_rx_status(),
|
||||
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_2_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_2_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
.phy_3_tx_clk(qsfp_tx_clk_3_int),
|
||||
.phy_3_tx_rst(qsfp_tx_rst_3_int),
|
||||
.phy_3_xgmii_txd(qsfp_txd_3_int),
|
||||
.phy_3_xgmii_txc(qsfp_txc_3_int),
|
||||
.phy_3_rx_clk(qsfp_rx_clk_3_int),
|
||||
.phy_3_rx_rst(qsfp_rx_rst_3_int),
|
||||
.phy_3_xgmii_rxd(qsfp_rxd_3_int),
|
||||
.phy_3_xgmii_rxc(qsfp_rxc_3_int),
|
||||
.phy_3_tx_bad_block(),
|
||||
.phy_3_rx_error_count(),
|
||||
.phy_3_rx_bad_block(),
|
||||
.phy_3_rx_sequence_error(),
|
||||
.phy_3_rx_block_lock(qsfp_rx_block_lock_3),
|
||||
.phy_3_rx_status(),
|
||||
.phy_3_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_3_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx2_p),
|
||||
.xcvr_txn(qsfp_tx2_n),
|
||||
.xcvr_rxp(qsfp_rx2_p),
|
||||
.xcvr_rxn(qsfp_rx2_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_2_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_2_int),
|
||||
.phy_xgmii_txd(qsfp_txd_2_int),
|
||||
.phy_xgmii_txc(qsfp_txc_2_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_2_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_2_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_2_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_2_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_2),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_3_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx3_p),
|
||||
.xcvr_txn(qsfp_tx3_n),
|
||||
.xcvr_rxp(qsfp_rx3_p),
|
||||
.xcvr_rxn(qsfp_rx3_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_3_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_3_int),
|
||||
.phy_xgmii_txd(qsfp_txd_3_int),
|
||||
.phy_xgmii_txc(qsfp_txc_3_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_3_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_3_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_3_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_3_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_3),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_4_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx4_p),
|
||||
.xcvr_txn(qsfp_tx4_n),
|
||||
.xcvr_rxp(qsfp_rx4_p),
|
||||
.xcvr_rxn(qsfp_rx4_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_4_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_4_int),
|
||||
.phy_xgmii_txd(qsfp_txd_4_int),
|
||||
.phy_xgmii_txc(qsfp_txc_4_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_4_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_4_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_4_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_4_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_4),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
.phy_4_tx_clk(qsfp_tx_clk_4_int),
|
||||
.phy_4_tx_rst(qsfp_tx_rst_4_int),
|
||||
.phy_4_xgmii_txd(qsfp_txd_4_int),
|
||||
.phy_4_xgmii_txc(qsfp_txc_4_int),
|
||||
.phy_4_rx_clk(qsfp_rx_clk_4_int),
|
||||
.phy_4_rx_rst(qsfp_rx_rst_4_int),
|
||||
.phy_4_xgmii_rxd(qsfp_rxd_4_int),
|
||||
.phy_4_xgmii_rxc(qsfp_rxc_4_int),
|
||||
.phy_4_tx_bad_block(),
|
||||
.phy_4_rx_error_count(),
|
||||
.phy_4_rx_bad_block(),
|
||||
.phy_4_rx_sequence_error(),
|
||||
.phy_4_rx_block_lock(qsfp_rx_block_lock_4),
|
||||
.phy_4_rx_status(),
|
||||
.phy_4_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_4_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
fpga_core
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user