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Adjust testbench timeouts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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28916a56cd
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@ -215,7 +215,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
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tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
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tb.log.debug("read data: %s", val)
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@ -172,7 +172,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
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tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
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tb.log.debug("read data: %s", val)
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@ -246,7 +246,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
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tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
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tb.log.debug("read data: %s", val)
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@ -201,7 +201,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
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tb.log.debug("%s", tb.axi_ram.hexdump_str((pcie_addr & ~0xf)-16, (((pcie_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=1000, timeout_unit='ns')
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val = await dev_bar0.read(pcie_addr, len(test_data), timeout=10000, timeout_unit='ns')
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tb.log.debug("read data: %s", val)
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