From 75126f133318b31f226ae13ebc46a40eb52cf3ac Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 23 Jun 2023 22:38:06 -0700 Subject: [PATCH] Configure RC model to split on all RCB boundaries during RX completion buffer tests Signed-off-by: Alex Forencich --- .../example_core_pcie_ptile/test_example_core_pcie_ptile.py | 4 ++++ .../tb/example_core_pcie_s10/test_example_core_pcie_s10.py | 4 ++++ .../tb/example_core_pcie_us/test_example_core_pcie_us.py | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py b/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py index b32fb3a70..42cce8133 100644 --- a/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py +++ b/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py @@ -580,6 +580,8 @@ async def run_test(dut): tb.log.info("Test RX completion buffer (CPLH, 8)") + tb.rc.split_on_all_rcb = True + size = 8 stride = size for count in range(32, 256+1, 8): @@ -599,6 +601,8 @@ async def run_test(dut): for count in range(8, 256+1, 8): await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000) + tb.rc.split_on_all_rcb = False + tb.log.info("Test RX completion buffer (CPLD)") size = 512 diff --git a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py index eb5a2385b..d6cfac5d0 100644 --- a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py +++ b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py @@ -528,6 +528,8 @@ async def run_test(dut): tb.log.info("Test RX completion buffer (CPLH, 8)") + tb.rc.split_on_all_rcb = True + size = 8 stride = size for count in range(32, 256+1, 8): @@ -547,6 +549,8 @@ async def run_test(dut): for count in range(8, 256+1, 8): await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000) + tb.rc.split_on_all_rcb = False + tb.log.info("Test RX completion buffer (CPLD)") size = 512 diff --git a/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py b/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py index 248c279e4..b20144336 100644 --- a/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py +++ b/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py @@ -621,6 +621,8 @@ async def run_test(dut): tb.log.info("Test RX completion buffer (CPLH, 8)") + tb.rc.split_on_all_rcb = True + size = 8 stride = size for count in range(32, 256+1, 8): @@ -640,6 +642,8 @@ async def run_test(dut): for count in range(8, 256+1, 8): await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000) + tb.rc.split_on_all_rcb = False + tb.log.info("Test RX completion buffer (CPLD)") size = 512