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Add 10G mqnic design for Stratix 10 MX dev kit
This commit is contained in:
Alex Forencich
parent
bd8a0513ed
commit
76e18d2af8
@ -25,6 +25,7 @@ Corundum currently supports Xilinx Virtex 7, UltraScale, and UltraScale+ series
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* Exablaze ExaNIC X25/Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
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* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
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* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
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* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)
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* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
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* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)
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* Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250)
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18
fpga/mqnic/S10MX_DK/fpga_10g/README.md
Normal file
18
fpga/mqnic/S10MX_DK/fpga_10g/README.md
Normal file
@ -0,0 +1,18 @@
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# Corundum mqnic for Stratix 10 MX
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## Introduction
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This design targets the Intel Stratix 10 MX FPGA development board.
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* FPGA: 1SM21BHU2F53E1VG (8 GB HBM2) or 1SM21CHU1F53E1VG (16 GB HBM2)
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* PHY: Transceiver in 10G BASE-R native mode
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## How to build
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Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.
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1
fpga/mqnic/S10MX_DK/fpga_10g/app
Symbolic link
1
fpga/mqnic/S10MX_DK/fpga_10g/app
Symbolic link
@ -0,0 +1 @@
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../../../app/
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188
fpga/mqnic/S10MX_DK/fpga_10g/common/quartus_pro.mk
Normal file
188
fpga/mqnic/S10MX_DK/fpga_10g/common/quartus_pro.mk
Normal file
@ -0,0 +1,188 @@
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###################################################################
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#
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# Makefile for Intel Quartus Prime Pro
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#
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# Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX)
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# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG)
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# SYN_FILES - space-separated list of source files
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# IP_FILES - space-separated list of IP files
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# IP_TCL_FILES - space-separated list of TCL files for qsys-script
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# QSF_FILES - space-separated list of settings files
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# SDC_FILES - space-separated list of timing constraint files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = "Stratix 10 DX"
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# FPGA_DEVICE = 1SD280PT2F55E1VG
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# SYN_FILES = rtl/fpga.v
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# QSF_FILES = fpga.qsf
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# SDC_FILES = fpga.sdc
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# include ../common/quartus_pro.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# output files to hang on to
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.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt
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.SECONDARY:
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# any project specific settings
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
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IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES))
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IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES)))
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IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
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IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES)))
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IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES)))
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CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
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ifdef QSF_FILES
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QSF_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(QSF_FILES))) $(filter /% ./%,$(QSF_FILES))
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else
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QSF_FILES_REL = ../$(FPGA_TOP).qsf
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endif
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SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES))
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ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and database
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).sof
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quartus: $(FPGA_TOP).qpf
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quartus $(FPGA_TOP).qpf
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tmpclean::
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-rm -rf defines.v
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-rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp
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-rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit
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-rm -rf create_project.tcl update_config.tcl update_ip_*.tcl
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clean:: tmpclean
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-rm -rf *.sof *.pof *.jdi *.jic *.map
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distclean:: clean
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-rm -rf rev
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syn: smart.log output_files/$(PROJECT).syn.rpt
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fit: smart.log output_files/$(PROJECT).fit.rpt
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asm: smart.log output_files/$(PROJECT).asm.rpt
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sta: smart.log output_files/$(PROJECT).sta.rpt
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smart: smart.log
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###################################################################
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# Executable Configuration
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###################################################################
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IP_ARGS = --run_default_mode_op
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SYN_ARGS = --read_settings_files=on --write_settings_files=off
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FIT_ARGS = --read_settings_files=on --write_settings_files=off
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ASM_ARGS = --read_settings_files=on --write_settings_files=off
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STA_ARGS =
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###################################################################
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# Target implementations
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###################################################################
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STAMP = echo done >
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define COPY_IP_RULE
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$(patsubst %, ip/%, $(notdir $(1))): $(1)
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@mkdir -p ip
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@cp -pv $(1) ip/
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endef
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$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l))))
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define TCL_IP_GEN_RULE
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$(patsubst %.tcl,%.ip,$(1)): $(1)
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cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf}
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cd ip && qsys-script --script=$(notdir $(1))
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endef
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$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l))))
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%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
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quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP)
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%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL)
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quartus_syn $(SYN_ARGS) $(FPGA_TOP)
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%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL)
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quartus_fit $(FIT_ARGS) $(FPGA_TOP)
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%.sta.rpt: sta.chg %.fit.rpt
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quartus_sta $(STA_ARGS) $(FPGA_TOP)
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%.asm.rpt: asm.chg %.sta.rpt
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quartus_asm $(ASM_ARGS) $(FPGA_TOP)
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mkdir -p rev
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EXT=sof; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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%.sof: smart.log %.asm.rpt
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smart.log: $(ASSIGNMENT_FILES)
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quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
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###################################################################
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# Project initialization
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###################################################################
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create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
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rm -f update_config.tcl
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echo "project_new $(FPGA_TOP) -overwrite" > $@
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echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
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echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@
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for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \
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case $${x##*.} in \
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v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\
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vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\
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qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\
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ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\
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*) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\
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esac; \
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done
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for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done
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for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL)
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echo "project_open $(FPGA_TOP)" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done
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$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl
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for x in $?; do quartus_sh -t "$$x"; done
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touch -c $(ASSIGNMENT_FILES)
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syn.chg:
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$(STAMP) syn.chg
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fit.chg:
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$(STAMP) fit.chg
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sta.chg:
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$(STAMP) sta.chg
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asm.chg:
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$(STAMP) asm.chg
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660
fpga/mqnic/S10MX_DK/fpga_10g/fpga.qsf
Normal file
660
fpga/mqnic/S10MX_DK/fpga_10g/fpga.qsf
Normal file
@ -0,0 +1,660 @@
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# I/O constraints for the Intel Stratix 10 MX FPGA development board
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# part: 1SM21BHU2F53E1VG (DK-DEV-1SMX-H-A with 8 GB HBM2)
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# part: 1SM21CHU1F53E1VG (DK-DEV-1SMC-H-A with 16 GB HBM2)
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set_global_assignment -name USE_CONF_DONE SDM_IO16
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set_global_assignment -name USE_INIT_DONE SDM_IO0
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set_global_assignment -name USE_CVP_CONFDONE SDM_IO15
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set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
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set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
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set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
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set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
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set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47
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set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
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set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
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set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
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set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
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set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
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set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name USE_CHECKSUM_AS_USERCODE ON
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set_global_assignment -name GENERATE_PR_RBF_FILE ON
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set_global_assignment -name ENABLE_ED_CRC_CHECK ON
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name MINIMUM_SEU_INTERVAL 10969
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
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set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
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# Clock and reset
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set_location_assignment PIN_BE17 -to "clk_sys_50m_p"
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set_location_assignment PIN_BD17 -to "clk_sys_50m_n"
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set_location_assignment PIN_AU17 -to "clk_sys_100m_p"
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set_location_assignment PIN_AU16 -to "clk_sys_100m_n"
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set_location_assignment PIN_AT13 -to "clk_core_bak_p"
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set_location_assignment PIN_AU13 -to "clk_core_bak_n"
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set_location_assignment PIN_AR26 -to "clk_uib0_p"
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set_location_assignment PIN_AP26 -to "clk_uib0_n"
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set_location_assignment PIN_P27 -to "clk_uib1_p"
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set_location_assignment PIN_R27 -to "clk_uib1_n"
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set_location_assignment PIN_AU31 -to "clk_esram0_p"
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set_location_assignment PIN_AU32 -to "clk_esram0_n"
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set_location_assignment PIN_V31 -to "clk_esram1_p"
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set_location_assignment PIN_U31 -to "clk_esram1_n"
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set_location_assignment PIN_A42 -to "clk_ddr4_comp_p"
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set_location_assignment PIN_B41 -to "clk_ddr4_comp_n"
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set_location_assignment PIN_B18 -to "clk_ddr4_dimm_p"
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set_location_assignment PIN_C18 -to "clk_ddr4_dimm_n"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_sys_50m_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_sys_100m_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_core_bak_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_uib0_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_uib1_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_esram0_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_esram1_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_ddr4_comp_p"
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set_instance_assignment -name IO_STANDARD LVDS -to "clk_ddr4_dimm_p"
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# Switches, buttons, LEDs
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set_location_assignment PIN_BL14 -to "cpu_resetn"
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set_location_assignment PIN_BH11 -to "user_led[3]"
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set_location_assignment PIN_BG11 -to "user_led[2]"
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set_location_assignment PIN_BF12 -to "user_led[1]"
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set_location_assignment PIN_BG12 -to "user_led[0]"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "user_led[*]"
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# I2C
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set_location_assignment PIN_BE14 -to "main_i2c_scl"
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set_location_assignment PIN_BF13 -to "main_i2c_sda"
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set_location_assignment PIN_D29 -to "ddr4_dimm_sda"
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set_location_assignment PIN_H30 -to "ddr4_dimm_scl"
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set_location_assignment PIN_BH14 -to "pcie_ep_i2c_sda"
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set_location_assignment PIN_BH15 -to "pcie_ep_i2c_scl"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "main_i2c_scl"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "main_i2c_sda"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "ddr4_dimm_sda"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "ddr4_dimm_scl"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_ep_i2c_sda"
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set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_ep_i2c_scl"
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# PCIe EP
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set_location_assignment PIN_BH45 -to "pcie_ep_tx_p[0]"
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set_location_assignment PIN_BH44 -to "pcie_ep_tx_n[0]"
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set_location_assignment PIN_BL47 -to "pcie_ep_rx_p[0]"
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set_location_assignment PIN_BL46 -to "pcie_ep_rx_n[0]"
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set_location_assignment PIN_BJ47 -to "pcie_ep_tx_p[1]"
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set_location_assignment PIN_BJ46 -to "pcie_ep_tx_n[1]"
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set_location_assignment PIN_BK49 -to "pcie_ep_rx_p[1]"
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set_location_assignment PIN_BK48 -to "pcie_ep_rx_n[1]"
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set_location_assignment PIN_BG47 -to "pcie_ep_tx_p[2]"
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set_location_assignment PIN_BG46 -to "pcie_ep_tx_n[2]"
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set_location_assignment PIN_BH49 -to "pcie_ep_rx_p[2]"
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set_location_assignment PIN_BH48 -to "pcie_ep_rx_n[2]"
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set_location_assignment PIN_BF45 -to "pcie_ep_tx_p[3]"
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set_location_assignment PIN_BF44 -to "pcie_ep_tx_n[3]"
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set_location_assignment PIN_BG51 -to "pcie_ep_rx_p[3]"
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set_location_assignment PIN_BG50 -to "pcie_ep_rx_n[3]"
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set_location_assignment PIN_BE47 -to "pcie_ep_tx_p[4]"
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set_location_assignment PIN_BE46 -to "pcie_ep_tx_n[4]"
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set_location_assignment PIN_BF49 -to "pcie_ep_rx_p[4]"
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set_location_assignment PIN_BF48 -to "pcie_ep_rx_n[4]"
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set_location_assignment PIN_BD45 -to "pcie_ep_tx_p[5]"
|
||||
set_location_assignment PIN_BD44 -to "pcie_ep_tx_n[5]"
|
||||
set_location_assignment PIN_BE51 -to "pcie_ep_rx_p[5]"
|
||||
set_location_assignment PIN_BE50 -to "pcie_ep_rx_n[5]"
|
||||
set_location_assignment PIN_BB45 -to "pcie_ep_tx_p[6]"
|
||||
set_location_assignment PIN_BB44 -to "pcie_ep_tx_n[6]"
|
||||
set_location_assignment PIN_BD49 -to "pcie_ep_rx_p[6]"
|
||||
set_location_assignment PIN_BD48 -to "pcie_ep_rx_n[6]"
|
||||
set_location_assignment PIN_BC47 -to "pcie_ep_tx_p[7]"
|
||||
set_location_assignment PIN_BC46 -to "pcie_ep_tx_n[7]"
|
||||
set_location_assignment PIN_BC51 -to "pcie_ep_rx_p[7]"
|
||||
set_location_assignment PIN_BC50 -to "pcie_ep_rx_n[7]"
|
||||
set_location_assignment PIN_BA47 -to "pcie_ep_tx_p[8]"
|
||||
set_location_assignment PIN_BA46 -to "pcie_ep_tx_n[8]"
|
||||
set_location_assignment PIN_BB49 -to "pcie_ep_rx_p[8]"
|
||||
set_location_assignment PIN_BB48 -to "pcie_ep_rx_n[8]"
|
||||
set_location_assignment PIN_AY45 -to "pcie_ep_tx_p[9]"
|
||||
set_location_assignment PIN_AY44 -to "pcie_ep_tx_n[9]"
|
||||
set_location_assignment PIN_BA51 -to "pcie_ep_rx_p[9]"
|
||||
set_location_assignment PIN_BA50 -to "pcie_ep_rx_n[9]"
|
||||
set_location_assignment PIN_AW47 -to "pcie_ep_tx_p[10]"
|
||||
set_location_assignment PIN_AW46 -to "pcie_ep_tx_n[10]"
|
||||
set_location_assignment PIN_AY49 -to "pcie_ep_rx_p[10]"
|
||||
set_location_assignment PIN_AY48 -to "pcie_ep_rx_n[10]"
|
||||
set_location_assignment PIN_AV45 -to "pcie_ep_tx_p[11]"
|
||||
set_location_assignment PIN_AV44 -to "pcie_ep_tx_n[11]"
|
||||
set_location_assignment PIN_AW51 -to "pcie_ep_rx_p[11]"
|
||||
set_location_assignment PIN_AW50 -to "pcie_ep_rx_n[11]"
|
||||
set_location_assignment PIN_AU47 -to "pcie_ep_tx_p[12]"
|
||||
set_location_assignment PIN_AU46 -to "pcie_ep_tx_n[12]"
|
||||
set_location_assignment PIN_AV49 -to "pcie_ep_rx_p[12]"
|
||||
set_location_assignment PIN_AV48 -to "pcie_ep_rx_n[12]"
|
||||
set_location_assignment PIN_AT45 -to "pcie_ep_tx_p[13]"
|
||||
set_location_assignment PIN_AT44 -to "pcie_ep_tx_n[13]"
|
||||
set_location_assignment PIN_AU51 -to "pcie_ep_rx_p[13]"
|
||||
set_location_assignment PIN_AU50 -to "pcie_ep_rx_n[13]"
|
||||
set_location_assignment PIN_AR47 -to "pcie_ep_tx_p[14]"
|
||||
set_location_assignment PIN_AR46 -to "pcie_ep_tx_n[14]"
|
||||
set_location_assignment PIN_AT49 -to "pcie_ep_rx_p[14]"
|
||||
set_location_assignment PIN_AT48 -to "pcie_ep_rx_n[14]"
|
||||
set_location_assignment PIN_AP45 -to "pcie_ep_tx_p[15]"
|
||||
set_location_assignment PIN_AP44 -to "pcie_ep_tx_n[15]"
|
||||
set_location_assignment PIN_AR51 -to "pcie_ep_rx_p[15]"
|
||||
set_location_assignment PIN_AR50 -to "pcie_ep_rx_n[15]"
|
||||
|
||||
set_location_assignment PIN_AW43 -to "refclk_pcie_ep_p"
|
||||
set_location_assignment PIN_AW42 -to "refclk_pcie_ep_n"
|
||||
|
||||
set_location_assignment PIN_AR43 -to "refclk_pcie_ep_edge_p"
|
||||
set_location_assignment PIN_AR42 -to "refclk_pcie_ep_edge_n"
|
||||
|
||||
set_location_assignment PIN_BA43 -to "refclk_pcie_ep1_p"
|
||||
set_location_assignment PIN_BA42 -to "refclk_pcie_ep1_n"
|
||||
|
||||
set_location_assignment PIN_BH16 -to "pcie_ep_waken"
|
||||
|
||||
set_location_assignment PIN_AH39 -to "s10_pcie_perstn0"
|
||||
set_location_assignment PIN_BL10 -to "s10_pcie_perstn1"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_ep_tx_p[*]"
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_ep_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_ep_tx_p[*]"
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_ep_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HCSL" -to "refclk_pcie_ep_p"
|
||||
set_instance_assignment -name IO_STANDARD "HCSL" -to "refclk_pcie_ep_edge_p"
|
||||
set_instance_assignment -name IO_STANDARD "HCSL" -to "refclk_pcie_ep1_p"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_ep_waken"
|
||||
set_instance_assignment -name USE_AS_3V_GPIO ON -to "s10_pcie_perstn0"
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to "s10_pcie_perstn0"
|
||||
set_instance_assignment -name USE_AS_3V_GPIO ON -to "s10_pcie_perstn1"
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to "s10_pcie_perstn1"
|
||||
|
||||
# PCIe RP
|
||||
set_location_assignment PIN_BL5 -to "pcie_rp_tx_p[0]"
|
||||
set_location_assignment PIN_BL6 -to "pcie_rp_tx_n[0]"
|
||||
set_location_assignment PIN_BH7 -to "pcie_rp_rx_p[0]"
|
||||
set_location_assignment PIN_BH8 -to "pcie_rp_rx_n[0]"
|
||||
set_location_assignment PIN_BK3 -to "pcie_rp_tx_p[1]"
|
||||
set_location_assignment PIN_BK4 -to "pcie_rp_tx_n[1]"
|
||||
set_location_assignment PIN_BJ5 -to "pcie_rp_rx_p[1]"
|
||||
set_location_assignment PIN_BJ6 -to "pcie_rp_rx_n[1]"
|
||||
set_location_assignment PIN_BH3 -to "pcie_rp_tx_p[2]"
|
||||
set_location_assignment PIN_BH4 -to "pcie_rp_tx_n[2]"
|
||||
set_location_assignment PIN_BG6 -to "pcie_rp_rx_n[2]"
|
||||
set_location_assignment PIN_BG5 -to "pcie_rp_rx_p[2]"
|
||||
set_location_assignment PIN_BG1 -to "pcie_rp_tx_p[3]"
|
||||
set_location_assignment PIN_BG2 -to "pcie_rp_tx_n[3]"
|
||||
set_location_assignment PIN_BF8 -to "pcie_rp_rx_n[3]"
|
||||
set_location_assignment PIN_BF7 -to "pcie_rp_rx_p[3]"
|
||||
set_location_assignment PIN_BF3 -to "pcie_rp_tx_p[4]"
|
||||
set_location_assignment PIN_BF4 -to "pcie_rp_tx_n[4]"
|
||||
set_location_assignment PIN_BE6 -to "pcie_rp_rx_n[4]"
|
||||
set_location_assignment PIN_BE5 -to "pcie_rp_rx_p[4]"
|
||||
set_location_assignment PIN_BE1 -to "pcie_rp_tx_p[5]"
|
||||
set_location_assignment PIN_BE2 -to "pcie_rp_tx_n[5]"
|
||||
set_location_assignment PIN_BD8 -to "pcie_rp_rx_n[5]"
|
||||
set_location_assignment PIN_BD7 -to "pcie_rp_rx_p[5]"
|
||||
set_location_assignment PIN_BD3 -to "pcie_rp_tx_p[6]"
|
||||
set_location_assignment PIN_BD4 -to "pcie_rp_tx_n[6]"
|
||||
set_location_assignment PIN_BB8 -to "pcie_rp_rx_n[6]"
|
||||
set_location_assignment PIN_BB7 -to "pcie_rp_rx_p[6]"
|
||||
set_location_assignment PIN_BC1 -to "pcie_rp_tx_p[7]"
|
||||
set_location_assignment PIN_BC2 -to "pcie_rp_tx_n[7]"
|
||||
set_location_assignment PIN_BC5 -to "pcie_rp_rx_p[7]"
|
||||
set_location_assignment PIN_BC6 -to "pcie_rp_rx_n[7]"
|
||||
set_location_assignment PIN_BB3 -to "pcie_rp_tx_p[8]"
|
||||
set_location_assignment PIN_BB4 -to "pcie_rp_tx_n[8]"
|
||||
set_location_assignment PIN_BA5 -to "pcie_rp_rx_p[8]"
|
||||
set_location_assignment PIN_BA6 -to "pcie_rp_rx_n[8]"
|
||||
set_location_assignment PIN_BA1 -to "pcie_rp_tx_p[9]"
|
||||
set_location_assignment PIN_BA2 -to "pcie_rp_tx_n[9]"
|
||||
set_location_assignment PIN_AY7 -to "pcie_rp_rx_p[9]"
|
||||
set_location_assignment PIN_AY8 -to "pcie_rp_rx_n[9]"
|
||||
set_location_assignment PIN_AY3 -to "pcie_rp_tx_p[10]"
|
||||
set_location_assignment PIN_AY4 -to "pcie_rp_tx_n[10]"
|
||||
set_location_assignment PIN_AW5 -to "pcie_rp_rx_p[10]"
|
||||
set_location_assignment PIN_AW6 -to "pcie_rp_rx_n[10]"
|
||||
set_location_assignment PIN_AW1 -to "pcie_rp_tx_p[11]"
|
||||
set_location_assignment PIN_AW2 -to "pcie_rp_tx_n[11]"
|
||||
set_location_assignment PIN_AV7 -to "pcie_rp_rx_p[11]"
|
||||
set_location_assignment PIN_AV8 -to "pcie_rp_rx_n[11]"
|
||||
set_location_assignment PIN_AV3 -to "pcie_rp_tx_p[12]"
|
||||
set_location_assignment PIN_AV4 -to "pcie_rp_tx_n[12]"
|
||||
set_location_assignment PIN_AU5 -to "pcie_rp_rx_p[12]"
|
||||
set_location_assignment PIN_AU6 -to "pcie_rp_rx_n[12]"
|
||||
set_location_assignment PIN_AU1 -to "pcie_rp_tx_p[13]"
|
||||
set_location_assignment PIN_AU2 -to "pcie_rp_tx_n[13]"
|
||||
set_location_assignment PIN_AT7 -to "pcie_rp_rx_p[13]"
|
||||
set_location_assignment PIN_AT8 -to "pcie_rp_rx_n[13]"
|
||||
set_location_assignment PIN_AT3 -to "pcie_rp_tx_p[14]"
|
||||
set_location_assignment PIN_AT4 -to "pcie_rp_tx_n[14]"
|
||||
set_location_assignment PIN_AR5 -to "pcie_rp_rx_p[14]"
|
||||
set_location_assignment PIN_AR6 -to "pcie_rp_rx_n[14]"
|
||||
set_location_assignment PIN_AR1 -to "pcie_rp_tx_p[15]"
|
||||
set_location_assignment PIN_AR2 -to "pcie_rp_tx_n[15]"
|
||||
set_location_assignment PIN_AP7 -to "pcie_rp_rx_p[15]"
|
||||
set_location_assignment PIN_AP8 -to "pcie_rp_rx_n[15]"
|
||||
|
||||
set_location_assignment PIN_AW9 -to "refclk_pcie_rp_p"
|
||||
set_location_assignment PIN_AW10 -to "refclk_pcie_rp_n"
|
||||
|
||||
set_location_assignment PIN_BB17 -to "pcie_rp_s10_perstn"
|
||||
set_location_assignment PIN_BG15 -to "pcie_rp_s10_waken"
|
||||
set_location_assignment PIN_BG16 -to "pcie_rp_s10_prsnt2n"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_rp_tx_p[*]"
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "pcie_rp_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_rp_tx_p[*]"
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "pcie_rp_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HCSL" -to "refclk_pcie_rp_p"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_rp_s10_perstn"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_rp_s10_waken"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "pcie_rp_s10_prsnt2n"
|
||||
|
||||
# QSFP
|
||||
set_location_assignment PIN_AN51 -to "qsfp0_tx_p[0]"
|
||||
set_location_assignment PIN_AN50 -to "qsfp0_tx_n[0]"
|
||||
set_location_assignment PIN_AM45 -to "qsfp0_rx_p[0]"
|
||||
set_location_assignment PIN_AM44 -to "qsfp0_rx_n[0]"
|
||||
set_location_assignment PIN_AL51 -to "qsfp0_tx_p[1]"
|
||||
set_location_assignment PIN_AL50 -to "qsfp0_tx_n[1]"
|
||||
set_location_assignment PIN_AK45 -to "qsfp0_rx_p[1]"
|
||||
set_location_assignment PIN_AK44 -to "qsfp0_rx_n[1]"
|
||||
set_location_assignment PIN_AG51 -to "qsfp0_tx_p[2]"
|
||||
set_location_assignment PIN_AG50 -to "qsfp0_tx_n[2]"
|
||||
set_location_assignment PIN_AF45 -to "qsfp0_rx_p[2]"
|
||||
set_location_assignment PIN_AF44 -to "qsfp0_rx_n[2]"
|
||||
set_location_assignment PIN_AJ51 -to "qsfp0_tx_p[3]"
|
||||
set_location_assignment PIN_AJ50 -to "qsfp0_tx_n[3]"
|
||||
set_location_assignment PIN_AH45 -to "qsfp0_rx_p[3]"
|
||||
set_location_assignment PIN_AH44 -to "qsfp0_rx_n[3]"
|
||||
set_location_assignment PIN_AJ43 -to "refclk_qsfp0_p"
|
||||
set_location_assignment PIN_AJ42 -to "refclk_qsfp0_n"
|
||||
|
||||
set_location_assignment PIN_AM3 -to "qsfp1_tx_p[0]"
|
||||
set_location_assignment PIN_AM4 -to "qsfp1_tx_n[0]"
|
||||
set_location_assignment PIN_AL5 -to "qsfp1_rx_p[0]"
|
||||
set_location_assignment PIN_AL6 -to "qsfp1_rx_n[0]"
|
||||
set_location_assignment PIN_AL1 -to "qsfp1_tx_p[1]"
|
||||
set_location_assignment PIN_AL2 -to "qsfp1_tx_n[1]"
|
||||
set_location_assignment PIN_AK7 -to "qsfp1_rx_p[1]"
|
||||
set_location_assignment PIN_AK8 -to "qsfp1_rx_n[1]"
|
||||
set_location_assignment PIN_AJ1 -to "qsfp1_tx_p[2]"
|
||||
set_location_assignment PIN_AJ2 -to "qsfp1_tx_n[2]"
|
||||
set_location_assignment PIN_AH7 -to "qsfp1_rx_p[2]"
|
||||
set_location_assignment PIN_AH8 -to "qsfp1_rx_n[2]"
|
||||
set_location_assignment PIN_AH3 -to "qsfp1_tx_p[3]"
|
||||
set_location_assignment PIN_AH4 -to "qsfp1_tx_n[3]"
|
||||
set_location_assignment PIN_AG5 -to "qsfp1_rx_p[3]"
|
||||
set_location_assignment PIN_AG6 -to "qsfp1_rx_n[3]"
|
||||
set_location_assignment PIN_AJ9 -to "refclk_qsfp1_p"
|
||||
set_location_assignment PIN_AJ10 -to "refclk_qsfp1_n"
|
||||
|
||||
set_location_assignment PIN_AW17 -to "qsfp0_modsel_l"
|
||||
set_location_assignment PIN_AV16 -to "qsfp0_reset_l"
|
||||
set_location_assignment PIN_AW16 -to "qsfp0_modprs_l"
|
||||
set_location_assignment PIN_BC16 -to "qsfp0_lpmode"
|
||||
set_location_assignment PIN_BB16 -to "qsfp0_int_l"
|
||||
|
||||
set_location_assignment PIN_BA17 -to "qsfp1_modsel_l"
|
||||
set_location_assignment PIN_AY16 -to "qsfp1_reset_l"
|
||||
set_location_assignment PIN_AY15 -to "qsfp1_modprs_l"
|
||||
set_location_assignment PIN_BE15 -to "qsfp1_lpmode"
|
||||
set_location_assignment PIN_BF15 -to "qsfp1_int_l"
|
||||
|
||||
set_location_assignment PIN_BD16 -to "qsfp_s10_i2c_sda"
|
||||
set_location_assignment PIN_BJ16 -to "qsfp_s10_i2c_scl"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_tx_p[*]"
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp0_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_tx_p[*]"
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp0_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_tx_p[*]"
|
||||
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to "qsfp1_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_tx_p[*]"
|
||||
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_1V -to "qsfp1_rx_p[*]"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp0_modsel_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp0_reset_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp0_modprs_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp0_lpmode"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp0_int_l"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_modsel_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_reset_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_modprs_l"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_lpmode"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp1_int_l"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_s10_i2c_sda"
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to "qsfp_s10_i2c_scl"
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to "refclk_qsfp0_p"
|
||||
set_instance_assignment -name IO_STANDARD "Differential LVPECL" -to "refclk_qsfp1_p"
|
||||
|
||||
# DDR4 COMP
|
||||
set_location_assignment PIN_A40 -to "ddr4_comp_rzq"
|
||||
|
||||
set_location_assignment PIN_A38 -to "ddr4_comp_alert_n"
|
||||
set_location_assignment PIN_F35 -to "ddr4_comp_reset_n"
|
||||
set_location_assignment PIN_A39 -to "ddr4_comp_par"
|
||||
|
||||
set_location_assignment PIN_H34 -to "ddr4_comp_a[0]"
|
||||
set_location_assignment PIN_J34 -to "ddr4_comp_a[1]"
|
||||
set_location_assignment PIN_G35 -to "ddr4_comp_a[2]"
|
||||
set_location_assignment PIN_H35 -to "ddr4_comp_a[3]"
|
||||
set_location_assignment PIN_L35 -to "ddr4_comp_a[4]"
|
||||
set_location_assignment PIN_K35 -to "ddr4_comp_a[5]"
|
||||
set_location_assignment PIN_L34 -to "ddr4_comp_a[6]"
|
||||
set_location_assignment PIN_K34 -to "ddr4_comp_a[7]"
|
||||
set_location_assignment PIN_N34 -to "ddr4_comp_a[8]"
|
||||
set_location_assignment PIN_P34 -to "ddr4_comp_a[9]"
|
||||
set_location_assignment PIN_M35 -to "ddr4_comp_a[10]"
|
||||
set_location_assignment PIN_N35 -to "ddr4_comp_a[11]"
|
||||
set_location_assignment PIN_B40 -to "ddr4_comp_a[12]"
|
||||
set_location_assignment PIN_C39 -to "ddr4_comp_a[13]"
|
||||
set_location_assignment PIN_D39 -to "ddr4_comp_a[14]"
|
||||
set_location_assignment PIN_D38 -to "ddr4_comp_a[15]"
|
||||
set_location_assignment PIN_C38 -to "ddr4_comp_a[16]"
|
||||
set_location_assignment PIN_G37 -to "ddr4_comp_bg[0]"
|
||||
set_location_assignment PIN_F34 -to "ddr4_comp_bg[1]"
|
||||
set_location_assignment PIN_E35 -to "ddr4_comp_act_n"
|
||||
set_location_assignment PIN_C36 -to "ddr4_comp_odt"
|
||||
set_location_assignment PIN_B37 -to "ddr4_comp_clk_p"
|
||||
set_location_assignment PIN_B38 -to "ddr4_comp_clk_n"
|
||||
set_location_assignment PIN_E36 -to "ddr4_comp_cs_n"
|
||||
set_location_assignment PIN_B36 -to "ddr4_comp_cke"
|
||||
set_location_assignment PIN_D37 -to "ddr4_comp_ba[0]"
|
||||
set_location_assignment PIN_F37 -to "ddr4_comp_ba[1]"
|
||||
|
||||
set_location_assignment PIN_R34 -to "ddr4_comp_dbi_n[0]"
|
||||
set_location_assignment PIN_J37 -to "ddr4_comp_dbi_n[1]"
|
||||
set_location_assignment PIN_K39 -to "ddr4_comp_dbi_n[2]"
|
||||
set_location_assignment PIN_F32 -to "ddr4_comp_dbi_n[3]"
|
||||
set_location_assignment PIN_P31 -to "ddr4_comp_dbi_n[4]"
|
||||
set_location_assignment PIN_N39 -to "ddr4_comp_dbi_n[5]"
|
||||
set_location_assignment PIN_C41 -to "ddr4_comp_dbi_n[6]"
|
||||
set_location_assignment PIN_M32 -to "ddr4_comp_dbi_n[7]"
|
||||
set_location_assignment PIN_A33 -to "ddr4_comp_dbi_n[8]"
|
||||
|
||||
set_location_assignment PIN_M36 -to "ddr4_comp_dqs_p[0]"
|
||||
set_location_assignment PIN_N36 -to "ddr4_comp_dqs_n[0]"
|
||||
set_location_assignment PIN_H38 -to "ddr4_comp_dqs_p[1]"
|
||||
set_location_assignment PIN_J38 -to "ddr4_comp_dqs_n[1]"
|
||||
set_location_assignment PIN_E42 -to "ddr4_comp_dqs_p[2]"
|
||||
set_location_assignment PIN_F42 -to "ddr4_comp_dqs_n[2]"
|
||||
set_location_assignment PIN_D32 -to "ddr4_comp_dqs_p[3]"
|
||||
set_location_assignment PIN_E32 -to "ddr4_comp_dqs_n[3]"
|
||||
set_location_assignment PIN_M31 -to "ddr4_comp_dqs_p[4]"
|
||||
set_location_assignment PIN_N31 -to "ddr4_comp_dqs_n[4]"
|
||||
set_location_assignment PIN_U37 -to "ddr4_comp_dqs_p[5]"
|
||||
set_location_assignment PIN_T37 -to "ddr4_comp_dqs_n[5]"
|
||||
set_location_assignment PIN_E41 -to "ddr4_comp_dqs_p[6]"
|
||||
set_location_assignment PIN_E40 -to "ddr4_comp_dqs_n[6]"
|
||||
set_location_assignment PIN_G33 -to "ddr4_comp_dqs_p[7]"
|
||||
set_location_assignment PIN_F33 -to "ddr4_comp_dqs_n[7]"
|
||||
set_location_assignment PIN_B31 -to "ddr4_comp_dqs_p[8]"
|
||||
set_location_assignment PIN_A32 -to "ddr4_comp_dqs_n[8]"
|
||||
|
||||
set_location_assignment PIN_K36 -to "ddr4_comp_dq[0]"
|
||||
set_location_assignment PIN_H36 -to "ddr4_comp_dq[1]"
|
||||
set_location_assignment PIN_P36 -to "ddr4_comp_dq[2]"
|
||||
set_location_assignment PIN_T35 -to "ddr4_comp_dq[3]"
|
||||
set_location_assignment PIN_J36 -to "ddr4_comp_dq[4]"
|
||||
set_location_assignment PIN_G36 -to "ddr4_comp_dq[5]"
|
||||
set_location_assignment PIN_R36 -to "ddr4_comp_dq[6]"
|
||||
set_location_assignment PIN_T34 -to "ddr4_comp_dq[7]"
|
||||
set_location_assignment PIN_K37 -to "ddr4_comp_dq[8]"
|
||||
set_location_assignment PIN_G38 -to "ddr4_comp_dq[9]"
|
||||
set_location_assignment PIN_M37 -to "ddr4_comp_dq[10]"
|
||||
set_location_assignment PIN_P38 -to "ddr4_comp_dq[11]"
|
||||
set_location_assignment PIN_L37 -to "ddr4_comp_dq[12]"
|
||||
set_location_assignment PIN_P37 -to "ddr4_comp_dq[13]"
|
||||
set_location_assignment PIN_N38 -to "ddr4_comp_dq[14]"
|
||||
set_location_assignment PIN_R37 -to "ddr4_comp_dq[15]"
|
||||
set_location_assignment PIN_G42 -to "ddr4_comp_dq[16]"
|
||||
set_location_assignment PIN_J39 -to "ddr4_comp_dq[17]"
|
||||
set_location_assignment PIN_H42 -to "ddr4_comp_dq[18]"
|
||||
set_location_assignment PIN_G40 -to "ddr4_comp_dq[19]"
|
||||
set_location_assignment PIN_H41 -to "ddr4_comp_dq[20]"
|
||||
set_location_assignment PIN_L39 -to "ddr4_comp_dq[21]"
|
||||
set_location_assignment PIN_H40 -to "ddr4_comp_dq[22]"
|
||||
set_location_assignment PIN_G41 -to "ddr4_comp_dq[23]"
|
||||
set_location_assignment PIN_B32 -to "ddr4_comp_dq[24]"
|
||||
set_location_assignment PIN_G32 -to "ddr4_comp_dq[25]"
|
||||
set_location_assignment PIN_C33 -to "ddr4_comp_dq[26]"
|
||||
set_location_assignment PIN_J31 -to "ddr4_comp_dq[27]"
|
||||
set_location_assignment PIN_B33 -to "ddr4_comp_dq[28]"
|
||||
set_location_assignment PIN_H31 -to "ddr4_comp_dq[29]"
|
||||
set_location_assignment PIN_D33 -to "ddr4_comp_dq[30]"
|
||||
set_location_assignment PIN_K31 -to "ddr4_comp_dq[31]"
|
||||
set_location_assignment PIN_M33 -to "ddr4_comp_dq[32]"
|
||||
set_location_assignment PIN_R31 -to "ddr4_comp_dq[33]"
|
||||
set_location_assignment PIN_N33 -to "ddr4_comp_dq[34]"
|
||||
set_location_assignment PIN_R32 -to "ddr4_comp_dq[35]"
|
||||
set_location_assignment PIN_L33 -to "ddr4_comp_dq[36]"
|
||||
set_location_assignment PIN_T32 -to "ddr4_comp_dq[37]"
|
||||
set_location_assignment PIN_P33 -to "ddr4_comp_dq[38]"
|
||||
set_location_assignment PIN_T33 -to "ddr4_comp_dq[39]"
|
||||
set_location_assignment PIN_P39 -to "ddr4_comp_dq[40]"
|
||||
set_location_assignment PIN_T39 -to "ddr4_comp_dq[41]"
|
||||
set_location_assignment PIN_T38 -to "ddr4_comp_dq[42]"
|
||||
set_location_assignment PIN_V39 -to "ddr4_comp_dq[43]"
|
||||
set_location_assignment PIN_M38 -to "ddr4_comp_dq[44]"
|
||||
set_location_assignment PIN_V38 -to "ddr4_comp_dq[45]"
|
||||
set_location_assignment PIN_U38 -to "ddr4_comp_dq[46]"
|
||||
set_location_assignment PIN_W39 -to "ddr4_comp_dq[47]"
|
||||
set_location_assignment PIN_C40 -to "ddr4_comp_dq[48]"
|
||||
set_location_assignment PIN_E39 -to "ddr4_comp_dq[49]"
|
||||
set_location_assignment PIN_B42 -to "ddr4_comp_dq[50]"
|
||||
set_location_assignment PIN_F39 -to "ddr4_comp_dq[51]"
|
||||
set_location_assignment PIN_D41 -to "ddr4_comp_dq[52]"
|
||||
set_location_assignment PIN_F38 -to "ddr4_comp_dq[53]"
|
||||
set_location_assignment PIN_D42 -to "ddr4_comp_dq[54]"
|
||||
set_location_assignment PIN_F40 -to "ddr4_comp_dq[55]"
|
||||
set_location_assignment PIN_C34 -to "ddr4_comp_dq[56]"
|
||||
set_location_assignment PIN_H33 -to "ddr4_comp_dq[57]"
|
||||
set_location_assignment PIN_D34 -to "ddr4_comp_dq[58]"
|
||||
set_location_assignment PIN_J32 -to "ddr4_comp_dq[59]"
|
||||
set_location_assignment PIN_C35 -to "ddr4_comp_dq[60]"
|
||||
set_location_assignment PIN_J33 -to "ddr4_comp_dq[61]"
|
||||
set_location_assignment PIN_E34 -to "ddr4_comp_dq[62]"
|
||||
set_location_assignment PIN_L32 -to "ddr4_comp_dq[63]"
|
||||
set_location_assignment PIN_C31 -to "ddr4_comp_dq[64]"
|
||||
set_location_assignment PIN_C30 -to "ddr4_comp_dq[65]"
|
||||
set_location_assignment PIN_A34 -to "ddr4_comp_dq[66]"
|
||||
set_location_assignment PIN_A30 -to "ddr4_comp_dq[67]"
|
||||
set_location_assignment PIN_D31 -to "ddr4_comp_dq[68]"
|
||||
set_location_assignment PIN_E31 -to "ddr4_comp_dq[69]"
|
||||
set_location_assignment PIN_B35 -to "ddr4_comp_dq[70]"
|
||||
set_location_assignment PIN_B30 -to "ddr4_comp_dq[71]"
|
||||
|
||||
# DDR4 DIMM CH0
|
||||
set_location_assignment PIN_B17 -to "ddr4_dimm_rzq"
|
||||
|
||||
set_location_assignment PIN_M30 -to "ddr4_dimm_event_n"
|
||||
set_location_assignment PIN_F30 -to "ddr4_dimm_save_n"
|
||||
set_location_assignment PIN_C21 -to "ddr4_dimm_alert_n"
|
||||
set_location_assignment PIN_P17 -to "ddr4_dimm_reset_n"
|
||||
set_location_assignment PIN_H18 -to "ddr4_dimm_par"
|
||||
|
||||
set_location_assignment PIN_J19 -to "ddr4_dimm_a[0]"
|
||||
set_location_assignment PIN_H19 -to "ddr4_dimm_a[1]"
|
||||
set_location_assignment PIN_L19 -to "ddr4_dimm_a[2]"
|
||||
set_location_assignment PIN_K19 -to "ddr4_dimm_a[3]"
|
||||
set_location_assignment PIN_G18 -to "ddr4_dimm_a[4]"
|
||||
set_location_assignment PIN_F18 -to "ddr4_dimm_a[5]"
|
||||
set_location_assignment PIN_G17 -to "ddr4_dimm_a[6]"
|
||||
set_location_assignment PIN_F17 -to "ddr4_dimm_a[7]"
|
||||
set_location_assignment PIN_E17 -to "ddr4_dimm_a[8]"
|
||||
set_location_assignment PIN_E16 -to "ddr4_dimm_a[9]"
|
||||
set_location_assignment PIN_D17 -to "ddr4_dimm_a[10]"
|
||||
set_location_assignment PIN_D18 -to "ddr4_dimm_a[11]"
|
||||
set_location_assignment PIN_A17 -to "ddr4_dimm_a[12]"
|
||||
set_location_assignment PIN_E19 -to "ddr4_dimm_a[13]"
|
||||
set_location_assignment PIN_F19 -to "ddr4_dimm_a[14]"
|
||||
set_location_assignment PIN_C19 -to "ddr4_dimm_a[15]"
|
||||
set_location_assignment PIN_D19 -to "ddr4_dimm_a[16]"
|
||||
set_location_assignment PIN_A20 -to "ddr4_dimm_a[17]"
|
||||
set_location_assignment PIN_A19 -to "ddr4_dimm_bg[0]"
|
||||
set_location_assignment PIN_R17 -to "ddr4_dimm_bg[1]"
|
||||
set_location_assignment PIN_N18 -to "ddr4_dimm_act_n"
|
||||
set_location_assignment PIN_M18 -to "ddr4_dimm_odt[0]"
|
||||
set_location_assignment PIN_L18 -to "ddr4_dimm_odt[1]"
|
||||
set_location_assignment PIN_K17 -to "ddr4_dimm_ck_p[0]"
|
||||
set_location_assignment PIN_J17 -to "ddr4_dimm_ck_n[0]"
|
||||
set_location_assignment PIN_D22 -to "ddr4_dimm_ck_p[1]"
|
||||
set_location_assignment PIN_E22 -to "ddr4_dimm_ck_n[1]"
|
||||
set_location_assignment PIN_P18 -to "ddr4_dimm_cs_n[0]"
|
||||
set_location_assignment PIN_J18 -to "ddr4_dimm_cs_n[1]"
|
||||
set_location_assignment PIN_E20 -to "ddr4_dimm_cs_n[2]"
|
||||
set_location_assignment PIN_F20 -to "ddr4_dimm_cs_n[3]"
|
||||
set_location_assignment PIN_G20 -to "ddr4_dimm_c2"
|
||||
set_location_assignment PIN_M17 -to "ddr4_dimm_cke[0]"
|
||||
set_location_assignment PIN_L17 -to "ddr4_dimm_cke[1]"
|
||||
set_location_assignment PIN_B20 -to "ddr4_dimm_ba[0]"
|
||||
set_location_assignment PIN_A18 -to "ddr4_dimm_ba[1]"
|
||||
|
||||
set_location_assignment PIN_L14 -to "ddr4_dimm_dqs_p[0]"
|
||||
set_location_assignment PIN_K14 -to "ddr4_dimm_dqs_n[0]"
|
||||
set_location_assignment PIN_M15 -to "ddr4_dimm_dqs_p[1]"
|
||||
set_location_assignment PIN_N15 -to "ddr4_dimm_dqs_n[1]"
|
||||
set_location_assignment PIN_L20 -to "ddr4_dimm_dqs_p[2]"
|
||||
set_location_assignment PIN_K20 -to "ddr4_dimm_dqs_n[2]"
|
||||
set_location_assignment PIN_E10 -to "ddr4_dimm_dqs_p[3]"
|
||||
set_location_assignment PIN_E11 -to "ddr4_dimm_dqs_n[3]"
|
||||
set_location_assignment PIN_A14 -to "ddr4_dimm_dqs_p[4]"
|
||||
set_location_assignment PIN_A15 -to "ddr4_dimm_dqs_n[4]"
|
||||
set_location_assignment PIN_F27 -to "ddr4_dimm_dqs_p[5]"
|
||||
set_location_assignment PIN_E27 -to "ddr4_dimm_dqs_n[5]"
|
||||
set_location_assignment PIN_D24 -to "ddr4_dimm_dqs_p[6]"
|
||||
set_location_assignment PIN_C24 -to "ddr4_dimm_dqs_n[6]"
|
||||
set_location_assignment PIN_B22 -to "ddr4_dimm_dqs_p[7]"
|
||||
set_location_assignment PIN_B21 -to "ddr4_dimm_dqs_n[7]"
|
||||
set_location_assignment PIN_B12 -to "ddr4_dimm_dqs_p[8]"
|
||||
set_location_assignment PIN_B11 -to "ddr4_dimm_dqs_n[8]"
|
||||
set_location_assignment PIN_F13 -to "ddr4_dimm_dqs_p[9]"
|
||||
set_location_assignment PIN_F14 -to "ddr4_dimm_dqs_n[9]"
|
||||
set_location_assignment PIN_J16 -to "ddr4_dimm_dqs_p[10]"
|
||||
set_location_assignment PIN_K16 -to "ddr4_dimm_dqs_n[10]"
|
||||
set_location_assignment PIN_N19 -to "ddr4_dimm_dqs_p[11]"
|
||||
set_location_assignment PIN_P19 -to "ddr4_dimm_dqs_n[11]"
|
||||
set_location_assignment PIN_C10 -to "ddr4_dimm_dqs_p[12]"
|
||||
set_location_assignment PIN_B10 -to "ddr4_dimm_dqs_n[12]"
|
||||
set_location_assignment PIN_B15 -to "ddr4_dimm_dqs_p[13]"
|
||||
set_location_assignment PIN_B16 -to "ddr4_dimm_dqs_n[13]"
|
||||
set_location_assignment PIN_J26 -to "ddr4_dimm_dqs_p[14]"
|
||||
set_location_assignment PIN_H26 -to "ddr4_dimm_dqs_n[14]"
|
||||
set_location_assignment PIN_J24 -to "ddr4_dimm_dqs_p[15]"
|
||||
set_location_assignment PIN_H24 -to "ddr4_dimm_dqs_n[15]"
|
||||
set_location_assignment PIN_G23 -to "ddr4_dimm_dqs_p[16]"
|
||||
set_location_assignment PIN_F23 -to "ddr4_dimm_dqs_n[16]"
|
||||
set_location_assignment PIN_D14 -to "ddr4_dimm_dqs_p[17]"
|
||||
set_location_assignment PIN_E14 -to "ddr4_dimm_dqs_n[17]"
|
||||
|
||||
set_location_assignment PIN_T14 -to "ddr4_dimm_dq[0]"
|
||||
set_location_assignment PIN_R14 -to "ddr4_dimm_dq[1]"
|
||||
set_location_assignment PIN_N14 -to "ddr4_dimm_dq[2]"
|
||||
set_location_assignment PIN_H14 -to "ddr4_dimm_dq[3]"
|
||||
set_location_assignment PIN_T15 -to "ddr4_dimm_dq[4]"
|
||||
set_location_assignment PIN_R15 -to "ddr4_dimm_dq[5]"
|
||||
set_location_assignment PIN_P14 -to "ddr4_dimm_dq[6]"
|
||||
set_location_assignment PIN_J14 -to "ddr4_dimm_dq[7]"
|
||||
set_location_assignment PIN_N16 -to "ddr4_dimm_dq[8]"
|
||||
set_location_assignment PIN_M16 -to "ddr4_dimm_dq[9]"
|
||||
set_location_assignment PIN_H16 -to "ddr4_dimm_dq[10]"
|
||||
set_location_assignment PIN_G16 -to "ddr4_dimm_dq[11]"
|
||||
set_location_assignment PIN_R16 -to "ddr4_dimm_dq[12]"
|
||||
set_location_assignment PIN_P16 -to "ddr4_dimm_dq[13]"
|
||||
set_location_assignment PIN_L15 -to "ddr4_dimm_dq[14]"
|
||||
set_location_assignment PIN_K15 -to "ddr4_dimm_dq[15]"
|
||||
set_location_assignment PIN_K21 -to "ddr4_dimm_dq[16]"
|
||||
set_location_assignment PIN_J22 -to "ddr4_dimm_dq[17]"
|
||||
set_location_assignment PIN_M20 -to "ddr4_dimm_dq[18]"
|
||||
set_location_assignment PIN_K22 -to "ddr4_dimm_dq[19]"
|
||||
set_location_assignment PIN_J23 -to "ddr4_dimm_dq[20]"
|
||||
set_location_assignment PIN_H23 -to "ddr4_dimm_dq[21]"
|
||||
set_location_assignment PIN_N20 -to "ddr4_dimm_dq[22]"
|
||||
set_location_assignment PIN_J21 -to "ddr4_dimm_dq[23]"
|
||||
set_location_assignment PIN_H10 -to "ddr4_dimm_dq[24]"
|
||||
set_location_assignment PIN_A10 -to "ddr4_dimm_dq[25]"
|
||||
set_location_assignment PIN_G10 -to "ddr4_dimm_dq[26]"
|
||||
set_location_assignment PIN_C11 -to "ddr4_dimm_dq[27]"
|
||||
set_location_assignment PIN_F10 -to "ddr4_dimm_dq[28]"
|
||||
set_location_assignment PIN_A9 -to "ddr4_dimm_dq[29]"
|
||||
set_location_assignment PIN_H11 -to "ddr4_dimm_dq[30]"
|
||||
set_location_assignment PIN_D11 -to "ddr4_dimm_dq[31]"
|
||||
set_location_assignment PIN_C14 -to "ddr4_dimm_dq[32]"
|
||||
set_location_assignment PIN_C16 -to "ddr4_dimm_dq[33]"
|
||||
set_location_assignment PIN_F15 -to "ddr4_dimm_dq[34]"
|
||||
set_location_assignment PIN_E15 -to "ddr4_dimm_dq[35]"
|
||||
set_location_assignment PIN_G15 -to "ddr4_dimm_dq[36]"
|
||||
set_location_assignment PIN_C15 -to "ddr4_dimm_dq[37]"
|
||||
set_location_assignment PIN_D16 -to "ddr4_dimm_dq[38]"
|
||||
set_location_assignment PIN_H15 -to "ddr4_dimm_dq[39]"
|
||||
set_location_assignment PIN_C26 -to "ddr4_dimm_dq[40]"
|
||||
set_location_assignment PIN_C25 -to "ddr4_dimm_dq[41]"
|
||||
set_location_assignment PIN_B27 -to "ddr4_dimm_dq[42]"
|
||||
set_location_assignment PIN_G26 -to "ddr4_dimm_dq[43]"
|
||||
set_location_assignment PIN_E26 -to "ddr4_dimm_dq[44]"
|
||||
set_location_assignment PIN_D26 -to "ddr4_dimm_dq[45]"
|
||||
set_location_assignment PIN_B26 -to "ddr4_dimm_dq[46]"
|
||||
set_location_assignment PIN_G27 -to "ddr4_dimm_dq[47]"
|
||||
set_location_assignment PIN_B25 -to "ddr4_dimm_dq[48]"
|
||||
set_location_assignment PIN_F24 -to "ddr4_dimm_dq[49]"
|
||||
set_location_assignment PIN_F25 -to "ddr4_dimm_dq[50]"
|
||||
set_location_assignment PIN_H25 -to "ddr4_dimm_dq[51]"
|
||||
set_location_assignment PIN_A25 -to "ddr4_dimm_dq[52]"
|
||||
set_location_assignment PIN_E24 -to "ddr4_dimm_dq[53]"
|
||||
set_location_assignment PIN_E25 -to "ddr4_dimm_dq[54]"
|
||||
set_location_assignment PIN_G25 -to "ddr4_dimm_dq[55]"
|
||||
set_location_assignment PIN_A22 -to "ddr4_dimm_dq[56]"
|
||||
set_location_assignment PIN_F22 -to "ddr4_dimm_dq[57]"
|
||||
set_location_assignment PIN_A24 -to "ddr4_dimm_dq[58]"
|
||||
set_location_assignment PIN_B23 -to "ddr4_dimm_dq[59]"
|
||||
set_location_assignment PIN_C23 -to "ddr4_dimm_dq[60]"
|
||||
set_location_assignment PIN_G22 -to "ddr4_dimm_dq[61]"
|
||||
set_location_assignment PIN_A23 -to "ddr4_dimm_dq[62]"
|
||||
set_location_assignment PIN_D23 -to "ddr4_dimm_dq[63]"
|
||||
set_location_assignment PIN_D12 -to "ddr4_dimm_dq[64]"
|
||||
set_location_assignment PIN_E12 -to "ddr4_dimm_dq[65]"
|
||||
set_location_assignment PIN_A12 -to "ddr4_dimm_dq[66]"
|
||||
set_location_assignment PIN_A13 -to "ddr4_dimm_dq[67]"
|
||||
set_location_assignment PIN_D13 -to "ddr4_dimm_dq[68]"
|
||||
set_location_assignment PIN_F12 -to "ddr4_dimm_dq[69]"
|
||||
set_location_assignment PIN_C13 -to "ddr4_dimm_dq[70]"
|
||||
set_location_assignment PIN_B13 -to "ddr4_dimm_dq[71]"
|
||||
103
fpga/mqnic/S10MX_DK/fpga_10g/fpga.sdc
Normal file
103
fpga/mqnic/S10MX_DK/fpga_10g/fpga.sdc
Normal file
@ -0,0 +1,103 @@
|
||||
# Timing constraints for the Intel Stratix 10 MX FPGA development board
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
# Clock constraints
|
||||
create_clock -period 20.000 -name {clk_sys_50m} [ get_ports {clk_sys_50m_p} ]
|
||||
create_clock -period 10.000 -name {clk_sys_100m} [ get_ports {clk_sys_100m_p} ]
|
||||
create_clock -period 10.000 -name {clk_core_bak} [ get_ports {clk_core_bak_p} ]
|
||||
create_clock -period 10.000 -name {clk_uib0} [ get_ports {clk_uib0_p} ]
|
||||
create_clock -period 10.000 -name {clk_uib1} [ get_ports {clk_uib1_p} ]
|
||||
create_clock -period 10.000 -name {clk_esram0} [ get_ports {clk_esram0_p} ]
|
||||
create_clock -period 10.000 -name {clk_esram1} [ get_ports {clk_esram1_p} ]
|
||||
create_clock -period 7.500 -name {clk_ddr4_comp} [ get_ports {clk_ddr4_comp_p} ]
|
||||
create_clock -period 7.500 -name {clk_ddr4_dimm} [ get_ports {clk_ddr4_dimm_p} ]
|
||||
|
||||
create_clock -period 10.000 -name {refclk_pcie_ep} [ get_ports {refclk_pcie_ep_p} ]
|
||||
create_clock -period 10.000 -name {refclk_pcie_ep_edge} [ get_ports {refclk_pcie_ep_edge_p} ]
|
||||
create_clock -period 10.000 -name {refclk_pcie_ep1} [ get_ports {refclk_pcie_ep1_p} ]
|
||||
create_clock -period 10.000 -name {refclk_pcie_rp} [ get_ports {refclk_pcie_rp_p} ]
|
||||
|
||||
create_clock -period 1.551 -name {refclk_qsfp0} [ get_ports {refclk_qsfp0_p} ]
|
||||
create_clock -period 1.551 -name {refclk_qsfp1} [ get_ports {refclk_qsfp1_p} ]
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_sys_50m} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_sys_100m} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_core_bak} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_uib0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_uib1} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_esram0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_esram1} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_comp} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_dimm} ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_edge} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep1} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_rp} ]
|
||||
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp1} ]
|
||||
|
||||
# JTAG constraints
|
||||
create_clock -name {altera_reserved_tck} -period 40.800 {altera_reserved_tck}
|
||||
|
||||
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
|
||||
|
||||
# IO constraints
|
||||
set_false_path -from "cpu_resetn"
|
||||
set_false_path -to "user_led[*]"
|
||||
|
||||
set_false_path -from "s10_pcie_perstn0"
|
||||
set_false_path -from "s10_pcie_perstn1"
|
||||
|
||||
|
||||
source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
|
||||
source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
|
||||
source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
|
||||
|
||||
# clocking infrastructure
|
||||
constrain_sync_reset_inst "sync_reset_100mhz_inst"
|
||||
|
||||
# PHY clocks
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
|
||||
set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
|
||||
|
||||
# PHY resets
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
|
||||
constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
|
||||
|
||||
# 10G MAC
|
||||
constrain_eth_mac_fifo_inst "core_inst|eth_mac_10g_fifo_inst"
|
||||
constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|rx_fifo|fifo_inst"
|
||||
constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|tx_fifo|fifo_inst"
|
||||
125
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
Normal file
125
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
Normal file
@ -0,0 +1,125 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_TOP = fpga
|
||||
FPGA_FAMILY = "Stratix 10 MX"
|
||||
FPGA_DEVICE = 1SM21BHU2F53E1VG
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# IP files
|
||||
IP_TCL_FILES += ip/reset_release.tcl
|
||||
IP_TCL_FILES += ip/pcie.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_pll.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
|
||||
|
||||
# QSF files
|
||||
QSF_FILES = fpga.qsf
|
||||
|
||||
# SDC files
|
||||
SDC_FILES = fpga.sdc
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/quartus_pro.mk
|
||||
|
||||
program: fpga
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
|
||||
208
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
Normal file
208
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
Normal file
@ -0,0 +1,208 @@
|
||||
# Copyright 2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# FW and board IDs
|
||||
dict set params FW_ID "32'd0"
|
||||
dict set params FW_VER "32'h00000001"
|
||||
dict set params BOARD_ID "32'h11720001"
|
||||
dict set params BOARD_VER "32'h00000001"
|
||||
dict set params FPGA_ID "32'h632ac0dd"
|
||||
|
||||
# Structural configuration
|
||||
|
||||
# counts QSFP 0 QSFP 1
|
||||
# IF PORT 0_1 0_2 0_3 0_4 1_1 1_2 1_3 1_4
|
||||
# 1 1 0 (0.0)
|
||||
# 1 2 0 (0.0) 1 (0.1)
|
||||
# 1 3 0 (0.0) 1 (0.1) 2 (0.2)
|
||||
# 1 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3)
|
||||
# 1 5 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4)
|
||||
# 1 6 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5)
|
||||
# 1 7 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6)
|
||||
# 1 8 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6) 7 (0.7)
|
||||
# 2 1 0 (0.0) 1 (1.0)
|
||||
# 2 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1)
|
||||
# 2 3 0 (0.0) 1 (0.1) 2 (0.2) 3 (1.0) 4 (1.1) 5 (1.2)
|
||||
# 2 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (1.0) 5 (1.1) 6 (1.2) 7 (1.3)
|
||||
# 3 1 0 (0.0) 1 (1.0) 2 (2.0)
|
||||
# 3 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1)
|
||||
# 4 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0)
|
||||
# 4 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1) 6 (3.0) 7 (3.1)
|
||||
# 5 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0)
|
||||
# 6 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0)
|
||||
# 7 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0)
|
||||
# 8 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0) 7 (7.0)
|
||||
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "10"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration (port)
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Timestamping configuration (port)
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_PTP_TS_FIFO_DEPTH "32"
|
||||
dict set params RX_PTP_TS_FIFO_DEPTH "32"
|
||||
|
||||
# Interface configuration (port)
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params SEG_COUNT "1"
|
||||
dict set params SEG_DATA_WIDTH "256"
|
||||
dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
|
||||
dict set params TX_SEQ_NUM_WIDTH "6"
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "0"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie pcie_s10_hip_ast_0
|
||||
set pcie_ip pcie
|
||||
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
|
||||
|
||||
puts $fp "package require qsys"
|
||||
puts $fp "load_system ip/${pcie_ip}.ip"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {4097}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {4660}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {131072}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {1}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {4466}"
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {fp pcie pf bar aperture} {
|
||||
if {$aperture > 0} {
|
||||
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
|
||||
|
||||
return
|
||||
}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
125
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
Normal file
125
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
Normal file
@ -0,0 +1,125 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_TOP = fpga
|
||||
FPGA_FAMILY = "Stratix 10 MX"
|
||||
FPGA_DEVICE = 1SM21CHU1F53E1VG
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
SYN_FILES += rtl/common/mqnic_core.v
|
||||
SYN_FILES += rtl/common/mqnic_interface.v
|
||||
SYN_FILES += rtl/common/mqnic_port.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_clock.v
|
||||
SYN_FILES += rtl/common/mqnic_ptp_perout.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += rtl/common/stats_counter.v
|
||||
SYN_FILES += rtl/common/stats_collect.v
|
||||
SYN_FILES += rtl/common/stats_pcie_if.v
|
||||
SYN_FILES += rtl/common/stats_pcie_tlp.v
|
||||
SYN_FILES += rtl/common/stats_dma_if_pcie.v
|
||||
SYN_FILES += rtl/common/stats_dma_latency.v
|
||||
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axil_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# IP files
|
||||
IP_TCL_FILES += ip/reset_release.tcl
|
||||
IP_TCL_FILES += ip/pcie.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_pll.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
|
||||
|
||||
# QSF files
|
||||
QSF_FILES = fpga.qsf
|
||||
|
||||
# SDC files
|
||||
SDC_FILES = fpga.sdc
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/quartus_pro.mk
|
||||
|
||||
program: fpga
|
||||
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
|
||||
208
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl
Normal file
208
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl
Normal file
@ -0,0 +1,208 @@
|
||||
# Copyright 2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# FW and board IDs
|
||||
dict set params FW_ID "32'd0"
|
||||
dict set params FW_VER "32'h00000001"
|
||||
dict set params BOARD_ID "32'h11720001"
|
||||
dict set params BOARD_VER "32'h00000001"
|
||||
dict set params FPGA_ID "32'h432AC0DD"
|
||||
|
||||
# Structural configuration
|
||||
|
||||
# counts QSFP 0 QSFP 1
|
||||
# IF PORT 0_1 0_2 0_3 0_4 1_1 1_2 1_3 1_4
|
||||
# 1 1 0 (0.0)
|
||||
# 1 2 0 (0.0) 1 (0.1)
|
||||
# 1 3 0 (0.0) 1 (0.1) 2 (0.2)
|
||||
# 1 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3)
|
||||
# 1 5 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4)
|
||||
# 1 6 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5)
|
||||
# 1 7 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6)
|
||||
# 1 8 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (0.4) 5 (0.5) 6 (0.6) 7 (0.7)
|
||||
# 2 1 0 (0.0) 1 (1.0)
|
||||
# 2 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1)
|
||||
# 2 3 0 (0.0) 1 (0.1) 2 (0.2) 3 (1.0) 4 (1.1) 5 (1.2)
|
||||
# 2 4 0 (0.0) 1 (0.1) 2 (0.2) 3 (0.3) 4 (1.0) 5 (1.1) 6 (1.2) 7 (1.3)
|
||||
# 3 1 0 (0.0) 1 (1.0) 2 (2.0)
|
||||
# 3 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1)
|
||||
# 4 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0)
|
||||
# 4 2 0 (0.0) 1 (0.1) 2 (1.0) 3 (1.1) 4 (2.0) 5 (2.1) 6 (3.0) 7 (3.1)
|
||||
# 5 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0)
|
||||
# 6 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0)
|
||||
# 7 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0)
|
||||
# 8 1 0 (0.0) 1 (1.0) 2 (2.0) 3 (3.0) 4 (4.0) 5 (5.0) 6 (6.0) 7 (7.0)
|
||||
|
||||
dict set params IF_COUNT "2"
|
||||
dict set params PORTS_PER_IF "1"
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_PEROUT_ENABLE "1"
|
||||
dict set params PTP_PEROUT_COUNT "1"
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
|
||||
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
|
||||
dict set params TX_QUEUE_INDEX_WIDTH "10"
|
||||
dict set params RX_QUEUE_INDEX_WIDTH "8"
|
||||
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
|
||||
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
|
||||
dict set params EVENT_QUEUE_PIPELINE "3"
|
||||
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
|
||||
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
dict set params TX_DESC_TABLE_SIZE "32"
|
||||
dict set params RX_DESC_TABLE_SIZE "32"
|
||||
|
||||
# Scheduler configuration (port)
|
||||
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
|
||||
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
|
||||
dict set params TDMA_INDEX_WIDTH "6"
|
||||
|
||||
# Timestamping configuration (port)
|
||||
dict set params PTP_TS_ENABLE "1"
|
||||
dict set params TX_PTP_TS_FIFO_DEPTH "32"
|
||||
dict set params RX_PTP_TS_FIFO_DEPTH "32"
|
||||
|
||||
# Interface configuration (port)
|
||||
dict set params TX_CHECKSUM_ENABLE "1"
|
||||
dict set params RX_RSS_ENABLE "1"
|
||||
dict set params RX_HASH_ENABLE "1"
|
||||
dict set params RX_CHECKSUM_ENABLE "1"
|
||||
dict set params TX_FIFO_DEPTH "32768"
|
||||
dict set params RX_FIFO_DEPTH "32768"
|
||||
dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ENABLE "0"
|
||||
dict set params APP_CTRL_ENABLE "1"
|
||||
dict set params APP_DMA_ENABLE "1"
|
||||
dict set params APP_AXIS_DIRECT_ENABLE "1"
|
||||
dict set params APP_AXIS_SYNC_ENABLE "1"
|
||||
dict set params APP_AXIS_IF_ENABLE "1"
|
||||
dict set params APP_STAT_ENABLE "1"
|
||||
|
||||
# DMA interface configuration
|
||||
dict set params DMA_LEN_WIDTH "16"
|
||||
dict set params DMA_TAG_WIDTH "16"
|
||||
dict set params RAM_PIPELINE "2"
|
||||
|
||||
# PCIe interface configuration
|
||||
dict set params SEG_COUNT "1"
|
||||
dict set params SEG_DATA_WIDTH "256"
|
||||
dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
|
||||
dict set params TX_SEQ_NUM_WIDTH "6"
|
||||
dict set params PCIE_TAG_COUNT "256"
|
||||
dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
|
||||
dict set params PCIE_DMA_READ_TX_LIMIT "16"
|
||||
dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
|
||||
dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
|
||||
dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
|
||||
dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_WIDTH "32"
|
||||
dict set params AXIL_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
|
||||
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
|
||||
|
||||
# Ethernet interface configuration
|
||||
dict set params AXIS_ETH_TX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
|
||||
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_PIPELINE "0"
|
||||
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
|
||||
|
||||
# Statistics counter subsystem
|
||||
dict set params STAT_ENABLE "0"
|
||||
dict set params STAT_DMA_ENABLE "1"
|
||||
dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie pcie_s10_hip_ast_0
|
||||
set pcie_ip pcie
|
||||
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
|
||||
|
||||
puts $fp "package require qsys"
|
||||
puts $fp "load_system ip/${pcie_ip}.ip"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {4097}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {4660}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {131072}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {1}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {4466}"
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {fp pcie pf bar aperture} {
|
||||
if {$aperture > 0} {
|
||||
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
|
||||
|
||||
return
|
||||
}
|
||||
puts "PF${pf} BAR${bar}: disabled"
|
||||
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
|
||||
puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
|
||||
|
||||
# Application BAR (BAR 2)
|
||||
configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
|
||||
|
||||
puts $fp "save_system"
|
||||
close $fp
|
||||
|
||||
# apply parameters to PCIe IP core
|
||||
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
|
||||
|
||||
# apply parameters to top-level
|
||||
dict for {name value} $params {
|
||||
set_parameter -name $name $value
|
||||
}
|
||||
382
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr.tcl
Normal file
382
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr.tcl
Normal file
@ -0,0 +1,382 @@
|
||||
package require -exact qsys 20.4
|
||||
|
||||
# create the system "eth_xcvr"
|
||||
proc do_create_eth_xcvr {} {
|
||||
# create the system
|
||||
create_system eth_xcvr
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GX}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.88230376152e+17}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r2}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {10312.5}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {12}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable}
|
||||
set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {}
|
||||
set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# add the exports
|
||||
set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset
|
||||
set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset
|
||||
set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset
|
||||
set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset
|
||||
set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat
|
||||
set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat
|
||||
set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat
|
||||
set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat
|
||||
set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy
|
||||
set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy
|
||||
set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0
|
||||
set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0
|
||||
set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data
|
||||
set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data
|
||||
set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref
|
||||
set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata
|
||||
set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin
|
||||
set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin
|
||||
set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout
|
||||
set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2
|
||||
set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout
|
||||
set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2
|
||||
set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data
|
||||
set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control
|
||||
set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid
|
||||
set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data
|
||||
set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data
|
||||
set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control
|
||||
set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid
|
||||
set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data
|
||||
set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="xcvr_native_s10_htile_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {eth_xcvr.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {eth_xcvr}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system eth_xcvr
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_eth_xcvr
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
141
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_pll.tcl
Normal file
141
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_pll.tcl
Normal file
@ -0,0 +1,141 @@
|
||||
package require -exact qsys 20.4
|
||||
|
||||
# create the system "eth_xcvr_pll"
|
||||
proc do_create_eth_xcvr_pll {} {
|
||||
# create the system
|
||||
create_system eth_xcvr_pll
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {disabled}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GX clock output buffer}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {5156.25}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0}
|
||||
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V}
|
||||
set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# add the exports
|
||||
set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0
|
||||
set_interface_property tx_serial_clk EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk
|
||||
set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked
|
||||
set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="xcvr_atx_pll_s10_htile_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {eth_xcvr_pll.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {eth_xcvr_pll}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system eth_xcvr_pll
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_eth_xcvr_pll
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
87
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_reset.tcl
Normal file
87
fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_reset.tcl
Normal file
@ -0,0 +1,87 @@
|
||||
package require -exact qsys 20.4
|
||||
|
||||
# create the system "eth_xcvr_reset"
|
||||
proc do_create_eth_xcvr_reset {} {
|
||||
# create the system
|
||||
create_system eth_xcvr_reset
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance xcvr_reset_control_s10_0 altera_xcvr_reset_control_s10
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {4}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {ENABLE_DIGITAL_SEQ} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {PLLS} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {REDUCED_SIM_TIME} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_ENABLE} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_MANUAL_RESET} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {RX_PER_CHANNEL} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {SYS_CLK_IN_MHZ} {100}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {TILE_TYPE} {h_tile}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_ENABLE} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_MANUAL_RESET} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PER_CHANNEL} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {TX_PLL_ENABLE} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_LOCK_HYST} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_PLL_POWERDOWN} {1000}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_ANALOGRESET} {40}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_RX_DIGITALRESET} {5000}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_ANALOGRESET} {0}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {T_TX_DIGITALRESET} {20}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {gui_pll_cal_busy} {1}
|
||||
set_instance_parameter_value xcvr_reset_control_s10_0 {gui_split_interfaces} {0}
|
||||
set_instance_property xcvr_reset_control_s10_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# add the exports
|
||||
set_interface_property clock EXPORT_OF xcvr_reset_control_s10_0.clock
|
||||
set_interface_property reset EXPORT_OF xcvr_reset_control_s10_0.reset
|
||||
set_interface_property tx_analogreset EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset
|
||||
set_interface_property tx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset
|
||||
set_interface_property tx_ready EXPORT_OF xcvr_reset_control_s10_0.tx_ready
|
||||
set_interface_property pll_locked EXPORT_OF xcvr_reset_control_s10_0.pll_locked
|
||||
set_interface_property pll_select EXPORT_OF xcvr_reset_control_s10_0.pll_select
|
||||
set_interface_property tx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.tx_cal_busy
|
||||
set_interface_property tx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_analogreset_stat
|
||||
set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.tx_digitalreset_stat
|
||||
set_interface_property pll_cal_busy EXPORT_OF xcvr_reset_control_s10_0.pll_cal_busy
|
||||
set_interface_property rx_analogreset EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset
|
||||
set_interface_property rx_digitalreset EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset
|
||||
set_interface_property rx_ready EXPORT_OF xcvr_reset_control_s10_0.rx_ready
|
||||
set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_reset_control_s10_0.rx_is_lockedtodata
|
||||
set_interface_property rx_cal_busy EXPORT_OF xcvr_reset_control_s10_0.rx_cal_busy
|
||||
set_interface_property rx_analogreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_analogreset_stat
|
||||
set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_reset_control_s10_0.rx_digitalreset_stat
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="xcvr_reset_control_s10_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {eth_xcvr_reset.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {eth_xcvr_reset}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system eth_xcvr_reset
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_eth_xcvr_reset
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
350
fpga/mqnic/S10MX_DK/fpga_10g/ip/pcie.tcl
Normal file
350
fpga/mqnic/S10MX_DK/fpga_10g/ip/pcie.tcl
Normal file
@ -0,0 +1,350 @@
|
||||
package require -exact qsys 21.3
|
||||
|
||||
# create the system "pcie"
|
||||
proc do_create_pcie {} {
|
||||
# create the system
|
||||
create_system pcie
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance pcie_s10_hip_ast_0 altera_pcie_s10_hip_ast
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {anlg_voltage} {1_1V}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {apps_type_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_clk_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_control_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_npor_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {bfm_drive_interface_pipe_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {ceb_extend_pcie_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {chosen_devkit_hwtcl} {Stratix 10 MX H-Tile Production FPGA Development Kit}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {cvp_user_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {design_environment} {NATIVE}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {device_ctrl_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {disable_256_to_512_adapter_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {eios_workaround_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_avst_reset_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_qii_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_sim_rp_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_synth_rp_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_example_design_tb_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_multi_func_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pcie_cv_fix} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pipe32_phyip_ser_driver_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_pld_warm_rst_rdy_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_rx_buffer_limit_ports_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_sriov_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {enable_test_out_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {hip_reconfig_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {hrc_rstctl_timer_g_delay_added_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {msi_info_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_avmm_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pcie_link_inspector_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_auto_lane_flip_ctrl_en_hwtcl} {enable}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_address_width_hwtcl} {24}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar0_type_hwtcl} {64-bit prefetchable memory}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_class_code_hwtcl} {131072}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_eq_eieos_cnt_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_expansion_base_address_register_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_loopback_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {32}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_device_id_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_vendor_id_hwtcl} {4097}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ep_l1_accpt_latency_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_ext_tag_supp_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_flr_cap_user_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_phy_slot_num_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_port_num_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_sel_deemphasis_hwtcl} {6dB}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_clk_config_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_scale_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_cap_slot_power_limit_value_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pcie_slot_imp_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_revision_id_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_sriov_vf_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_dev_id_hwtcl} {1313}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_subsys_vendor_id_hwtcl} {6538}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_count_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_vf_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_class_code_hwtcl} {16711680}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_expansion_base_address_register_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msi_multiple_msg_cap_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_bir_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_pba_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_pci_type0_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_revision_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_sriov_vf_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_dev_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_subsys_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_count_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf1_vf_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_class_code_hwtcl} {16711680}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_expansion_base_address_register_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msi_multiple_msg_cap_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_bir_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_pba_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_pci_type0_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_revision_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_sriov_vf_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_dev_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_subsys_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_count_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf2_vf_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_class_code_hwtcl} {16711680}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_expansion_base_address_register_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msi_multiple_msg_cap_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_bir_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_pba_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_pci_type0_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_revision_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_sup_page_size_user_hwtcl} {4KB, 8KB, 64KB, 256KB, 1MB, 4MB}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar0_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar1_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar2_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_sriov_vf_device_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_dev_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_subsys_vendor_id_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2_hwtcl} {ST table not present}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_req_cap_st_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_count_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_dev_spec_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf3_vf_tph_st_int_mode_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pll_refclk_freq_hwtcl} {100 MHz}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_hwtcl} {PIO}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {select_design_example_rtl_lang_hwtcl} {Verilog}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {select_example_design_sim_BFM_hwtcl} {Intel FPGA BFM}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {serial_sim_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {targeted_devkit_hwtcl} {NONE}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {total_pf_count_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {use_ast_parity_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {use_pll_lock_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {use_rpbfm_pro} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_ep_native_hwtcl} {Native}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_maxpayload_size_hwtcl} {1024}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msi_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msix_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msi_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_msix_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf2_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msi_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_msix_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf3_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_rp_ep_mode_hwtcl} {Native Endpoint}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {wrala_hwtcl} {Gen3x8, Interface - 256 bit, 250 MHz}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_adme_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {xcvr_reconfig_hwtcl} {0}
|
||||
set_instance_property pcie_s10_hip_ast_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# preserve ports for debug
|
||||
|
||||
# add the exports
|
||||
set_interface_property refclk EXPORT_OF pcie_s10_hip_ast_0.refclk
|
||||
set_interface_property coreclkout_hip EXPORT_OF pcie_s10_hip_ast_0.coreclkout_hip
|
||||
set_interface_property npor EXPORT_OF pcie_s10_hip_ast_0.npor
|
||||
set_interface_property hip_rst EXPORT_OF pcie_s10_hip_ast_0.hip_rst
|
||||
set_interface_property clr_st EXPORT_OF pcie_s10_hip_ast_0.clr_st
|
||||
set_interface_property ninit_done EXPORT_OF pcie_s10_hip_ast_0.ninit_done
|
||||
set_interface_property rx_st EXPORT_OF pcie_s10_hip_ast_0.rx_st
|
||||
set_interface_property tx_st EXPORT_OF pcie_s10_hip_ast_0.tx_st
|
||||
set_interface_property rx_bar EXPORT_OF pcie_s10_hip_ast_0.rx_bar
|
||||
set_interface_property tx_cred EXPORT_OF pcie_s10_hip_ast_0.tx_cred
|
||||
set_interface_property int_msi EXPORT_OF pcie_s10_hip_ast_0.int_msi
|
||||
set_interface_property hip_status EXPORT_OF pcie_s10_hip_ast_0.hip_status
|
||||
set_interface_property config_tl EXPORT_OF pcie_s10_hip_ast_0.config_tl
|
||||
set_interface_property hip_ctrl EXPORT_OF pcie_s10_hip_ast_0.hip_ctrl
|
||||
set_interface_property currentspeed EXPORT_OF pcie_s10_hip_ast_0.currentspeed
|
||||
set_interface_property hip_pipe EXPORT_OF pcie_s10_hip_ast_0.hip_pipe
|
||||
set_interface_property hip_serial EXPORT_OF pcie_s10_hip_ast_0.hip_serial
|
||||
set_interface_property power_mgnt EXPORT_OF pcie_s10_hip_ast_0.power_mgnt
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="pcie_s10_hip_ast_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {pcie.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {pcie}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system pcie
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_pcie
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
50
fpga/mqnic/S10MX_DK/fpga_10g/ip/reset_release.tcl
Normal file
50
fpga/mqnic/S10MX_DK/fpga_10g/ip/reset_release.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
package require -exact qsys 20.4
|
||||
|
||||
# create the system "reset_release"
|
||||
proc do_create_reset_release {} {
|
||||
# create the system
|
||||
create_system reset_release
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
|
||||
# add the components
|
||||
add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate
|
||||
set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface}
|
||||
set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true
|
||||
|
||||
# add wirelevel expressions
|
||||
|
||||
# add the exports
|
||||
set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done
|
||||
|
||||
# set values for exposed HDL parameters
|
||||
|
||||
# set the the module properties
|
||||
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
|
||||
<bonusData>
|
||||
<element __value="s10_user_rst_clkgate_0">
|
||||
<datum __value="_sortIndex" value="0" type="int" />
|
||||
</element>
|
||||
</bonusData>
|
||||
}
|
||||
set_module_property FILE {reset_release.ip}
|
||||
set_module_property GENERATION_ID {0x00000000}
|
||||
set_module_property NAME {reset_release}
|
||||
|
||||
# save the system
|
||||
sync_sysinfo_parameters
|
||||
save_system reset_release
|
||||
}
|
||||
|
||||
proc do_set_exported_interface_sysinfo_parameters {} {
|
||||
}
|
||||
|
||||
# create all the systems, from bottom up
|
||||
do_create_reset_release
|
||||
|
||||
# set system info parameters on exported interface, from bottom up
|
||||
do_set_exported_interface_sysinfo_parameters
|
||||
1
fpga/mqnic/S10MX_DK/fpga_10g/lib
Symbolic link
1
fpga/mqnic/S10MX_DK/fpga_10g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic/S10MX_DK/fpga_10g/rtl/common
Symbolic link
1
fpga/mqnic/S10MX_DK/fpga_10g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
282
fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
282
fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
@ -0,0 +1,282 @@
|
||||
/*
|
||||
|
||||
Copyright 2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and PHY quad wrapper
|
||||
*/
|
||||
module eth_xcvr_phy_quad_wrapper (
|
||||
input wire xcvr_ctrl_clk,
|
||||
input wire xcvr_ctrl_rst,
|
||||
input wire xcvr_ref_clk,
|
||||
output wire [3:0] xcvr_tx_serial_data,
|
||||
input wire [3:0] xcvr_rx_serial_data,
|
||||
|
||||
output wire phy_1_tx_clk,
|
||||
output wire phy_1_tx_rst,
|
||||
input wire [63:0] phy_1_xgmii_txd,
|
||||
input wire [7:0] phy_1_xgmii_txc,
|
||||
output wire phy_1_rx_clk,
|
||||
output wire phy_1_rx_rst,
|
||||
output wire [63:0] phy_1_xgmii_rxd,
|
||||
output wire [7:0] phy_1_xgmii_rxc,
|
||||
output wire phy_1_rx_block_lock,
|
||||
output wire phy_1_rx_high_ber,
|
||||
output wire phy_2_tx_clk,
|
||||
output wire phy_2_tx_rst,
|
||||
input wire [63:0] phy_2_xgmii_txd,
|
||||
input wire [7:0] phy_2_xgmii_txc,
|
||||
output wire phy_2_rx_clk,
|
||||
output wire phy_2_rx_rst,
|
||||
output wire [63:0] phy_2_xgmii_rxd,
|
||||
output wire [7:0] phy_2_xgmii_rxc,
|
||||
output wire phy_2_rx_block_lock,
|
||||
output wire phy_2_rx_high_ber,
|
||||
output wire phy_3_tx_clk,
|
||||
output wire phy_3_tx_rst,
|
||||
input wire [63:0] phy_3_xgmii_txd,
|
||||
input wire [7:0] phy_3_xgmii_txc,
|
||||
output wire phy_3_rx_clk,
|
||||
output wire phy_3_rx_rst,
|
||||
output wire [63:0] phy_3_xgmii_rxd,
|
||||
output wire [7:0] phy_3_xgmii_rxc,
|
||||
output wire phy_3_rx_block_lock,
|
||||
output wire phy_3_rx_high_ber,
|
||||
output wire phy_4_tx_clk,
|
||||
output wire phy_4_tx_rst,
|
||||
input wire [63:0] phy_4_xgmii_txd,
|
||||
input wire [7:0] phy_4_xgmii_txc,
|
||||
output wire phy_4_rx_clk,
|
||||
output wire phy_4_rx_rst,
|
||||
output wire [63:0] phy_4_xgmii_rxd,
|
||||
output wire [7:0] phy_4_xgmii_rxc,
|
||||
output wire phy_4_rx_block_lock,
|
||||
output wire phy_4_rx_high_ber
|
||||
);
|
||||
|
||||
wire xcvr_pll_locked;
|
||||
wire xcvr_pll_cal_busy;
|
||||
|
||||
wire xcvr_tx_serial_clk;
|
||||
|
||||
wire [3:0] xcvr_tx_analogreset;
|
||||
wire [3:0] xcvr_rx_analogreset;
|
||||
wire [3:0] xcvr_tx_digitalreset;
|
||||
wire [3:0] xcvr_rx_digitalreset;
|
||||
wire [3:0] xcvr_tx_analogreset_stat;
|
||||
wire [3:0] xcvr_rx_analogreset_stat;
|
||||
wire [3:0] xcvr_tx_digitalreset_stat;
|
||||
wire [3:0] xcvr_rx_digitalreset_stat;
|
||||
wire [3:0] xcvr_tx_cal_busy;
|
||||
wire [3:0] xcvr_rx_cal_busy;
|
||||
wire [3:0] xcvr_rx_is_lockedtoref;
|
||||
wire [3:0] xcvr_rx_is_lockedtodata;
|
||||
wire [3:0] xcvr_tx_ready;
|
||||
wire [3:0] xcvr_rx_ready;
|
||||
|
||||
eth_xcvr_reset eth_xcvr_reset_inst (
|
||||
.clock (xcvr_ctrl_clk),
|
||||
.reset (xcvr_ctrl_rst),
|
||||
.tx_analogreset (xcvr_tx_analogreset),
|
||||
.tx_digitalreset (xcvr_tx_digitalreset),
|
||||
.tx_ready (xcvr_tx_ready),
|
||||
.pll_locked (xcvr_pll_locked),
|
||||
.pll_select (4'd0),
|
||||
.tx_cal_busy (xcvr_tx_cal_busy),
|
||||
.tx_analogreset_stat (xcvr_tx_analogreset_stat),
|
||||
.tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
|
||||
.pll_cal_busy (xcvr_pll_cal_busy),
|
||||
.rx_analogreset (xcvr_rx_analogreset),
|
||||
.rx_digitalreset (xcvr_rx_digitalreset),
|
||||
.rx_ready (xcvr_rx_ready),
|
||||
.rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
|
||||
.rx_cal_busy (xcvr_rx_cal_busy),
|
||||
.rx_analogreset_stat (xcvr_rx_analogreset_stat),
|
||||
.rx_digitalreset_stat (xcvr_rx_digitalreset_stat)
|
||||
);
|
||||
|
||||
eth_xcvr_pll eth_xcvr_pll_inst (
|
||||
.pll_refclk0 (xcvr_ref_clk),
|
||||
.tx_serial_clk (xcvr_tx_serial_clk),
|
||||
.pll_locked (xcvr_pll_locked),
|
||||
.pll_cal_busy (xcvr_pll_cal_busy)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper eth_xcvr_phy_1 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
.xcvr_tx_analogreset(xcvr_tx_analogreset[0]),
|
||||
.xcvr_rx_analogreset(xcvr_rx_analogreset[0]),
|
||||
.xcvr_tx_digitalreset(xcvr_tx_digitalreset[0]),
|
||||
.xcvr_rx_digitalreset(xcvr_rx_digitalreset[0]),
|
||||
.xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[0]),
|
||||
.xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[0]),
|
||||
.xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[0]),
|
||||
.xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[0]),
|
||||
.xcvr_tx_cal_busy(xcvr_tx_cal_busy[0]),
|
||||
.xcvr_rx_cal_busy(xcvr_rx_cal_busy[0]),
|
||||
.xcvr_tx_serial_clk(xcvr_tx_serial_clk),
|
||||
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
|
||||
.xcvr_tx_serial_data(xcvr_tx_serial_data[0]),
|
||||
.xcvr_rx_serial_data(xcvr_rx_serial_data[0]),
|
||||
.xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[0]),
|
||||
.xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[0]),
|
||||
.xcvr_tx_ready(xcvr_tx_ready[0]),
|
||||
.xcvr_rx_ready(xcvr_rx_ready[0]),
|
||||
|
||||
.phy_tx_clk(phy_1_tx_clk),
|
||||
.phy_tx_rst(phy_1_tx_rst),
|
||||
.phy_xgmii_txd(phy_1_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_1_xgmii_txc),
|
||||
.phy_rx_clk(phy_1_rx_clk),
|
||||
.phy_rx_rst(phy_1_rx_rst),
|
||||
.phy_xgmii_rxd(phy_1_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_1_xgmii_rxc),
|
||||
.phy_rx_block_lock(phy_1_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_1_rx_high_ber)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper eth_xcvr_phy_2 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
.xcvr_tx_analogreset(xcvr_tx_analogreset[1]),
|
||||
.xcvr_rx_analogreset(xcvr_rx_analogreset[1]),
|
||||
.xcvr_tx_digitalreset(xcvr_tx_digitalreset[1]),
|
||||
.xcvr_rx_digitalreset(xcvr_rx_digitalreset[1]),
|
||||
.xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[1]),
|
||||
.xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[1]),
|
||||
.xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[1]),
|
||||
.xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[1]),
|
||||
.xcvr_tx_cal_busy(xcvr_tx_cal_busy[1]),
|
||||
.xcvr_rx_cal_busy(xcvr_rx_cal_busy[1]),
|
||||
.xcvr_tx_serial_clk(xcvr_tx_serial_clk),
|
||||
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
|
||||
.xcvr_tx_serial_data(xcvr_tx_serial_data[1]),
|
||||
.xcvr_rx_serial_data(xcvr_rx_serial_data[1]),
|
||||
.xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[1]),
|
||||
.xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[1]),
|
||||
.xcvr_tx_ready(xcvr_tx_ready[1]),
|
||||
.xcvr_rx_ready(xcvr_rx_ready[1]),
|
||||
|
||||
.phy_tx_clk(phy_2_tx_clk),
|
||||
.phy_tx_rst(phy_2_tx_rst),
|
||||
.phy_xgmii_txd(phy_2_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_2_xgmii_txc),
|
||||
.phy_rx_clk(phy_2_rx_clk),
|
||||
.phy_rx_rst(phy_2_rx_rst),
|
||||
.phy_xgmii_rxd(phy_2_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_2_xgmii_rxc),
|
||||
.phy_rx_block_lock(phy_2_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_2_rx_high_ber)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper eth_xcvr_phy_3 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
.xcvr_tx_analogreset(xcvr_tx_analogreset[2]),
|
||||
.xcvr_rx_analogreset(xcvr_rx_analogreset[2]),
|
||||
.xcvr_tx_digitalreset(xcvr_tx_digitalreset[2]),
|
||||
.xcvr_rx_digitalreset(xcvr_rx_digitalreset[2]),
|
||||
.xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[2]),
|
||||
.xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[2]),
|
||||
.xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[2]),
|
||||
.xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[2]),
|
||||
.xcvr_tx_cal_busy(xcvr_tx_cal_busy[2]),
|
||||
.xcvr_rx_cal_busy(xcvr_rx_cal_busy[2]),
|
||||
.xcvr_tx_serial_clk(xcvr_tx_serial_clk),
|
||||
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
|
||||
.xcvr_tx_serial_data(xcvr_tx_serial_data[2]),
|
||||
.xcvr_rx_serial_data(xcvr_rx_serial_data[2]),
|
||||
.xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[2]),
|
||||
.xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[2]),
|
||||
.xcvr_tx_ready(xcvr_tx_ready[2]),
|
||||
.xcvr_rx_ready(xcvr_rx_ready[2]),
|
||||
|
||||
.phy_tx_clk(phy_3_tx_clk),
|
||||
.phy_tx_rst(phy_3_tx_rst),
|
||||
.phy_xgmii_txd(phy_3_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_3_xgmii_txc),
|
||||
.phy_rx_clk(phy_3_rx_clk),
|
||||
.phy_rx_rst(phy_3_rx_rst),
|
||||
.phy_xgmii_rxd(phy_3_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_3_xgmii_rxc),
|
||||
.phy_rx_block_lock(phy_3_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_3_rx_high_ber)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper eth_xcvr_phy_4 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
.xcvr_tx_analogreset(xcvr_tx_analogreset[3]),
|
||||
.xcvr_rx_analogreset(xcvr_rx_analogreset[3]),
|
||||
.xcvr_tx_digitalreset(xcvr_tx_digitalreset[3]),
|
||||
.xcvr_rx_digitalreset(xcvr_rx_digitalreset[3]),
|
||||
.xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[3]),
|
||||
.xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[3]),
|
||||
.xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[3]),
|
||||
.xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[3]),
|
||||
.xcvr_tx_cal_busy(xcvr_tx_cal_busy[3]),
|
||||
.xcvr_rx_cal_busy(xcvr_rx_cal_busy[3]),
|
||||
.xcvr_tx_serial_clk(xcvr_tx_serial_clk),
|
||||
.xcvr_rx_cdr_refclk(xcvr_ref_clk),
|
||||
.xcvr_tx_serial_data(xcvr_tx_serial_data[3]),
|
||||
.xcvr_rx_serial_data(xcvr_rx_serial_data[3]),
|
||||
.xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[3]),
|
||||
.xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[3]),
|
||||
.xcvr_tx_ready(xcvr_tx_ready[3]),
|
||||
.xcvr_rx_ready(xcvr_rx_ready[3]),
|
||||
|
||||
.phy_tx_clk(phy_4_tx_clk),
|
||||
.phy_tx_rst(phy_4_tx_rst),
|
||||
.phy_xgmii_txd(phy_4_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_4_xgmii_txc),
|
||||
.phy_rx_clk(phy_4_rx_clk),
|
||||
.phy_rx_rst(phy_4_rx_rst),
|
||||
.phy_xgmii_rxd(phy_4_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_4_xgmii_rxc),
|
||||
.phy_rx_block_lock(phy_4_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_4_rx_high_ber)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
176
fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v
Normal file
176
fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
|
||||
Copyright 2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and PHY wrapper
|
||||
*/
|
||||
module eth_xcvr_phy_wrapper (
|
||||
input wire xcvr_ctrl_clk,
|
||||
input wire xcvr_ctrl_rst,
|
||||
|
||||
input wire xcvr_tx_analogreset,
|
||||
input wire xcvr_rx_analogreset,
|
||||
input wire xcvr_tx_digitalreset,
|
||||
input wire xcvr_rx_digitalreset,
|
||||
output wire xcvr_tx_analogreset_stat,
|
||||
output wire xcvr_rx_analogreset_stat,
|
||||
output wire xcvr_tx_digitalreset_stat,
|
||||
output wire xcvr_rx_digitalreset_stat,
|
||||
output wire xcvr_tx_cal_busy,
|
||||
output wire xcvr_rx_cal_busy,
|
||||
input wire xcvr_tx_serial_clk,
|
||||
input wire xcvr_rx_cdr_refclk,
|
||||
output wire xcvr_tx_serial_data,
|
||||
input wire xcvr_rx_serial_data,
|
||||
output wire xcvr_rx_is_lockedtoref,
|
||||
output wire xcvr_rx_is_lockedtodata,
|
||||
input wire xcvr_tx_ready,
|
||||
input wire xcvr_rx_ready,
|
||||
|
||||
output wire phy_tx_clk,
|
||||
output wire phy_tx_rst,
|
||||
input wire [63:0] phy_xgmii_txd,
|
||||
input wire [7:0] phy_xgmii_txc,
|
||||
output wire phy_rx_clk,
|
||||
output wire phy_rx_rst,
|
||||
output wire [63:0] phy_xgmii_rxd,
|
||||
output wire [7:0] phy_xgmii_rxc,
|
||||
output wire phy_rx_block_lock,
|
||||
output wire phy_rx_high_ber
|
||||
);
|
||||
|
||||
wire xcvr_tx_clk;
|
||||
wire xcvr_rx_clk;
|
||||
|
||||
assign phy_tx_clk = xcvr_tx_clk;
|
||||
assign phy_rx_clk = xcvr_rx_clk;
|
||||
|
||||
wire [1:0] xcvr_tx_hdr;
|
||||
wire [63:0] xcvr_tx_data;
|
||||
wire [1:0] xcvr_rx_hdr;
|
||||
wire [63:0] xcvr_rx_data;
|
||||
|
||||
wire [1:0] phy_tx_hdr;
|
||||
wire [63:0] phy_tx_data;
|
||||
wire [1:0] phy_rx_hdr;
|
||||
wire [63:0] phy_rx_data;
|
||||
|
||||
wire xcvr_rx_bitslip;
|
||||
|
||||
assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr};
|
||||
assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data};
|
||||
|
||||
eth_xcvr eth_xcvr_inst (
|
||||
.tx_analogreset (xcvr_tx_analogreset),
|
||||
.rx_analogreset (xcvr_rx_analogreset),
|
||||
.tx_digitalreset (xcvr_tx_digitalreset),
|
||||
.rx_digitalreset (xcvr_rx_digitalreset),
|
||||
.tx_analogreset_stat (xcvr_tx_analogreset_stat),
|
||||
.rx_analogreset_stat (xcvr_rx_analogreset_stat),
|
||||
.tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
|
||||
.rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
|
||||
.tx_cal_busy (xcvr_tx_cal_busy),
|
||||
.rx_cal_busy (xcvr_rx_cal_busy),
|
||||
.tx_serial_clk0 (xcvr_tx_serial_clk),
|
||||
.rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
|
||||
.tx_serial_data (xcvr_tx_serial_data),
|
||||
.rx_serial_data (xcvr_rx_serial_data),
|
||||
.rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
|
||||
.rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
|
||||
.tx_coreclkin (xcvr_tx_clk),
|
||||
.rx_coreclkin (xcvr_rx_clk),
|
||||
.tx_clkout (xcvr_tx_clk),
|
||||
.tx_clkout2 (),
|
||||
.rx_clkout (xcvr_rx_clk),
|
||||
.rx_clkout2 (),
|
||||
.tx_parallel_data (xcvr_tx_data),
|
||||
.tx_control (xcvr_tx_hdr),
|
||||
.tx_enh_data_valid (1'b1),
|
||||
.unused_tx_parallel_data (13'd0),
|
||||
.rx_parallel_data (xcvr_rx_data),
|
||||
.rx_control (xcvr_rx_hdr),
|
||||
.rx_enh_data_valid (),
|
||||
.unused_rx_parallel_data (),
|
||||
.rx_bitslip (xcvr_rx_bitslip)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
phy_tx_rst_reset_sync_inst (
|
||||
.clk(phy_tx_clk),
|
||||
.rst(~xcvr_tx_ready),
|
||||
.out(phy_tx_rst)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
phy_rx_rst_reset_sync_inst (
|
||||
.clk(phy_rx_clk),
|
||||
.rst(~xcvr_rx_ready),
|
||||
.out(phy_rx_rst)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.BIT_REVERSE(0),
|
||||
.BITSLIP_HIGH_CYCLES(32),
|
||||
.BITSLIP_LOW_CYCLES(32)
|
||||
)
|
||||
phy_inst (
|
||||
.tx_clk(phy_tx_clk),
|
||||
.tx_rst(phy_tx_rst),
|
||||
.rx_clk(phy_rx_clk),
|
||||
.rx_rst(phy_rx_rst),
|
||||
.xgmii_txd(phy_xgmii_txd),
|
||||
.xgmii_txc(phy_xgmii_txc),
|
||||
.xgmii_rxd(phy_xgmii_rxd),
|
||||
.xgmii_rxc(phy_xgmii_rxc),
|
||||
.serdes_tx_data(phy_tx_data),
|
||||
.serdes_tx_hdr(phy_tx_hdr),
|
||||
.serdes_rx_data(phy_rx_data),
|
||||
.serdes_rx_hdr(phy_rx_hdr),
|
||||
.serdes_rx_bitslip(xcvr_rx_bitslip),
|
||||
.rx_block_lock(phy_rx_block_lock),
|
||||
.rx_high_ber(phy_rx_high_ber)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
1099
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
Normal file
1099
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
1157
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
Normal file
1157
fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
62
fpga/mqnic/S10MX_DK/fpga_10g/rtl/sync_signal.v
Normal file
62
fpga/mqnic/S10MX_DK/fpga_10g/rtl/sync_signal.v
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
401
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
Normal file
401
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
Normal file
@ -0,0 +1,401 @@
|
||||
# Copyright 2020-2021, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_s10.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_ts_extract.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 2
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 1
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
|
||||
|
||||
# Interface configuration (port)
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 32768
|
||||
export PARAM_RX_RAM_SIZE ?= 32768
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_SEG_COUNT ?= 1
|
||||
export PARAM_SEG_DATA_WIDTH ?= 256
|
||||
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
|
||||
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 256
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= 16
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= 16
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= 3
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GSEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/mqnic.py
Symbolic link
1
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../../common/tb/mqnic.py
|
||||
681
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
Normal file
681
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
Normal file
@ -0,0 +1,681 @@
|
||||
"""
|
||||
|
||||
Copyright 2020-2021, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.eth import XgmiiSource, XgmiiSink
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = S10PcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
# pcie_link_width=8,
|
||||
# pld_clk_frequency=250e6,
|
||||
l_tile=False,
|
||||
|
||||
# signals
|
||||
# Clock and reset
|
||||
# npor=dut.npor,
|
||||
# pin_perst=dut.pin_perst,
|
||||
# ninit_done=dut.ninit_done,
|
||||
# pld_clk_inuse=dut.pld_clk_inuse,
|
||||
# pld_core_ready=dut.pld_core_ready,
|
||||
reset_status=dut.rst_250mhz,
|
||||
# clr_st=dut.clr_st,
|
||||
# refclk=dut.refclk,
|
||||
coreclkout_hip=dut.clk_250mhz,
|
||||
|
||||
# RX interface
|
||||
rx_bus=S10RxBus.from_prefix(dut, "rx_st"),
|
||||
|
||||
# TX interface
|
||||
tx_bus=S10TxBus.from_prefix(dut, "tx_st"),
|
||||
|
||||
# TX flow control
|
||||
tx_ph_cdts=dut.tx_ph_cdts,
|
||||
tx_pd_cdts=dut.tx_pd_cdts,
|
||||
tx_nph_cdts=dut.tx_nph_cdts,
|
||||
tx_npd_cdts=dut.tx_npd_cdts,
|
||||
tx_cplh_cdts=dut.tx_cplh_cdts,
|
||||
tx_cpld_cdts=dut.tx_cpld_cdts,
|
||||
tx_hdr_cdts_consumed=dut.tx_hdr_cdts_consumed,
|
||||
tx_data_cdts_consumed=dut.tx_data_cdts_consumed,
|
||||
tx_cdts_type=dut.tx_cdts_type,
|
||||
tx_cdts_data_value=dut.tx_cdts_data_value,
|
||||
|
||||
# Hard IP status
|
||||
# int_status=dut.int_status,
|
||||
# int_status_common=dut.int_status_common,
|
||||
# derr_cor_ext_rpl=dut.derr_cor_ext_rpl,
|
||||
# derr_rpl=dut.derr_rpl,
|
||||
# derr_cor_ext_rcv=dut.derr_cor_ext_rcv,
|
||||
# derr_uncor_ext_rcv=dut.derr_uncor_ext_rcv,
|
||||
# rx_par_err=dut.rx_par_err,
|
||||
# tx_par_err=dut.tx_par_err,
|
||||
# ltssmstate=dut.ltssmstate,
|
||||
# link_up=dut.link_up,
|
||||
# lane_act=dut.lane_act,
|
||||
# currentspeed=dut.currentspeed,
|
||||
|
||||
# Power management
|
||||
# pm_linkst_in_l1=dut.pm_linkst_in_l1,
|
||||
# pm_linkst_in_l0s=dut.pm_linkst_in_l0s,
|
||||
# pm_state=dut.pm_state,
|
||||
# pm_dstate=dut.pm_dstate,
|
||||
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
|
||||
# apps_ready_entr_l23=dut.apps_ready_entr_l23,
|
||||
# apps_pm_xmt_turnoff=dut.apps_pm_xmt_turnoff,
|
||||
# app_init_rst=dut.app_init_rst,
|
||||
# app_xfer_pending=dut.app_xfer_pending,
|
||||
|
||||
# Interrupt interface
|
||||
app_msi_req=dut.app_msi_req,
|
||||
app_msi_ack=dut.app_msi_ack,
|
||||
app_msi_tc=dut.app_msi_tc,
|
||||
app_msi_num=dut.app_msi_num,
|
||||
app_msi_func_num=dut.app_msi_func_num,
|
||||
# app_int_sts=dut.app_int_sts,
|
||||
|
||||
# Error interface
|
||||
# app_err_valid=dut.app_err_valid,
|
||||
# app_err_hdr=dut.app_err_hdr,
|
||||
# app_err_info=dut.app_err_info,
|
||||
# app_err_func_num=dut.app_err_func_num,
|
||||
|
||||
# Configuration output
|
||||
tl_cfg_func=dut.tl_cfg_func,
|
||||
tl_cfg_add=dut.tl_cfg_add,
|
||||
tl_cfg_ctl=dut.tl_cfg_ctl,
|
||||
|
||||
# Configuration extension bus
|
||||
# ceb_req=dut.ceb_req,
|
||||
# ceb_ack=dut.ceb_ack,
|
||||
# ceb_addr=dut.ceb_addr,
|
||||
# ceb_din=dut.ceb_din,
|
||||
# ceb_dout=dut.ceb_dout,
|
||||
# ceb_wr=dut.ceb_wr,
|
||||
# ceb_cdm_convert_data=dut.ceb_cdm_convert_data,
|
||||
# ceb_func_num=dut.ceb_func_num,
|
||||
# ceb_vf_num=dut.ceb_vf_num,
|
||||
# ceb_vf_active=dut.ceb_vf_active,
|
||||
|
||||
# Hard IP reconfiguration interface
|
||||
# hip_reconfig_clk=dut.hip_reconfig_clk,
|
||||
# hip_reconfig_address=dut.hip_reconfig_address,
|
||||
# hip_reconfig_read=dut.hip_reconfig_read,
|
||||
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
|
||||
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
|
||||
# hip_reconfig_write=dut.hip_reconfig_write,
|
||||
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
|
||||
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.driver = mqnic.Driver(self.rc)
|
||||
|
||||
self.dev.functions[0].msi_cap.msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
# Ethernet
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start())
|
||||
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
|
||||
cocotb.fork(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start())
|
||||
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start())
|
||||
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2)
|
||||
cocotb.fork(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start())
|
||||
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start())
|
||||
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3)
|
||||
cocotb.fork(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start())
|
||||
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start())
|
||||
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4)
|
||||
cocotb.fork(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start())
|
||||
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start())
|
||||
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
|
||||
cocotb.fork(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start())
|
||||
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start())
|
||||
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
|
||||
cocotb.fork(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start())
|
||||
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start())
|
||||
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
|
||||
cocotb.fork(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start())
|
||||
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
|
||||
|
||||
cocotb.fork(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start())
|
||||
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
|
||||
cocotb.fork(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
|
||||
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
|
||||
|
||||
# dut.qsfp0_i2c_scl_i.setimmediatevalue(1)
|
||||
# dut.qsfp0_i2c_sda_i.setimmediatevalue(1)
|
||||
# dut.qsfp0_intr_n.setimmediatevalue(1)
|
||||
# dut.qsfp0_mod_prsnt_n.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp0_rx_error_count_0.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_1.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_2.setimmediatevalue(0)
|
||||
# dut.qsfp0_rx_error_count_3.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp1_i2c_scl_i.setimmediatevalue(1)
|
||||
# dut.qsfp1_i2c_sda_i.setimmediatevalue(1)
|
||||
# dut.qsfp1_intr_n.setimmediatevalue(1)
|
||||
# dut.qsfp1_mod_prsnt_n.setimmediatevalue(0)
|
||||
|
||||
# dut.qsfp1_rx_error_count_0.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_1.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_2.setimmediatevalue(0)
|
||||
# dut.qsfp1_rx_error_count_3.setimmediatevalue(0)
|
||||
|
||||
# dut.qspi_dq_i.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.fork(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(1)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(1)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(1)
|
||||
|
||||
await FallingEdge(self.dut.rst_250mhz)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp0_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp0_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk_250mhz)
|
||||
|
||||
if self.loopback_enable:
|
||||
if not self.qsfp0_1_sink.empty():
|
||||
await self.qsfp0_1_source.send(await self.qsfp0_1_sink.recv())
|
||||
if not self.qsfp0_2_sink.empty():
|
||||
await self.qsfp0_2_source.send(await self.qsfp0_2_sink.recv())
|
||||
if not self.qsfp0_3_sink.empty():
|
||||
await self.qsfp0_3_source.send(await self.qsfp0_3_sink.recv())
|
||||
if not self.qsfp0_4_sink.empty():
|
||||
await self.qsfp0_4_source.send(await self.qsfp0_4_sink.recv())
|
||||
if not self.qsfp1_1_sink.empty():
|
||||
await self.qsfp1_1_source.send(await self.qsfp1_1_sink.recv())
|
||||
if not self.qsfp1_2_sink.empty():
|
||||
await self.qsfp1_2_source.send(await self.qsfp1_2_sink.recv())
|
||||
if not self.qsfp1_3_sink.empty():
|
||||
await self.qsfp1_3_source.send(await self.qsfp1_3_sink.recv())
|
||||
if not self.qsfp1_4_sink.empty():
|
||||
await self.qsfp1_4_source.send(await self.qsfp1_4_sink.recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_dev(tb.dev.functions[0].pcie_id)
|
||||
await tb.driver.interfaces[0].open()
|
||||
# await driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
await tb.rc.mem_write_dword(tb.driver.interfaces[0].ports[0].hw_addr+mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
|
||||
for k in range(tb.driver.interfaces[0].tx_queue_count):
|
||||
await tb.rc.mem_write_dword(tb.driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.rc.mem_read(tb.driver.hw_addr, 4)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.qsfp0_1_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp0_1_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
# await tb.driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# pkt = await tb.qsfp1_1_sink.recv()
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
|
||||
# await tb.qsfp1_1_source.send(pkt)
|
||||
|
||||
# pkt = await tb.driver.interfaces[1].recv()
|
||||
|
||||
# tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.qsfp0_1_sink.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.qsfp0_1_source.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
await RisingEdge(dut.clk_250mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_s10.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "event_mux.v"),
|
||||
os.path.join(rtl_dir, "common", "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber.v"),
|
||||
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_ts_extract.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = 2
|
||||
parameters['PORTS_PER_IF'] = 1
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_PEROUT_ENABLE'] = 1
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration (interface)
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration (port)
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration (port)
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Timestamping configuration (port)
|
||||
parameters['PTP_TS_ENABLE'] = 1
|
||||
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
|
||||
|
||||
# Interface configuration (port)
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 32768
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 32768
|
||||
parameters['RX_RAM_SIZE'] = 32768
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['SEG_COUNT'] = 1
|
||||
parameters['SEG_DATA_WIDTH'] = 256
|
||||
parameters['SEG_EMPTY_WIDTH'] = ((parameters['SEG_DATA_WIDTH'] // 32) - 1).bit_length()
|
||||
parameters['TX_SEQ_NUM_WIDTH'] = 6
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 256
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 16
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 16
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 3
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user