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Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster

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This commit is contained in:
Alex Forencich 2017-11-20 21:30:26 -08:00
parent de590517a9
commit 772e433ee9
11 changed files with 396 additions and 286 deletions
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112
rtl/axis_frame_length_adjust.v
View File

@ -31,8 +31,15 @@ THE SOFTWARE.
*/
module axis_frame_length_adjust #
(
parameter DATA_WIDTH = 1,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
@ -46,7 +53,9 @@ module axis_frame_length_adjust #
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/*
* AXI output
@ -56,7 +65,9 @@ module axis_frame_length_adjust #
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/*
* Status
@ -106,8 +117,9 @@ reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}};
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg [ID_WIDTH-1:0] last_word_id_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] last_word_dest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] last_word_user_reg = {USER_WIDTH{1'b0}};
reg status_valid_reg = 1'b0, status_valid_next;
reg status_frame_pad_reg = 1'b0, status_frame_pad_next;
@ -116,13 +128,15 @@ reg [15:0] status_frame_length_reg = 16'd0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg [ID_WIDTH-1:0] output_axis_tid_int;
reg [DEST_WIDTH-1:0] output_axis_tdest_int;
reg [USER_WIDTH-1:0] output_axis_tuser_int;
wire output_axis_tready_int_early;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
@ -145,16 +159,16 @@ always @* begin
short_counter_next = short_counter_reg;
long_counter_next = long_counter_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tid_int = {ID_WIDTH{1'b0}};
output_axis_tdest_int = {DEST_WIDTH{1'b0}};
output_axis_tuser_int = {USER_WIDTH{1'b0}};
input_axis_tready_next = 1'b0;
last_cycle_tuser_next = last_cycle_tuser_reg;
status_valid_next = status_valid_reg & ~status_ready;
status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg;
@ -171,6 +185,8 @@ always @* begin
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
short_counter_next = length_min;
@ -224,8 +240,7 @@ always @* begin
input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
last_cycle_tuser_next = input_axis_tuser;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
@ -268,6 +283,8 @@ always @* begin
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = input_axis_tid;
output_axis_tdest_int = input_axis_tdest;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
@ -318,8 +335,7 @@ always @* begin
input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
last_cycle_tuser_next = input_axis_tuser;
store_last_word = 1'b1;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
@ -361,7 +377,9 @@ always @* begin
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = last_word_user_reg;
if (output_axis_tready_int_reg) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
@ -386,7 +404,6 @@ always @* begin
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = last_cycle_tuser_reg;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
@ -406,6 +423,8 @@ always @* begin
output_axis_tkeep_int = last_word_keep_reg;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tlast;
output_axis_tlast_int = input_axis_tlast;
output_axis_tid_int = last_word_id_reg;
output_axis_tdest_int = last_word_dest_reg;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
@ -458,8 +477,6 @@ always @(posedge clk) begin
status_valid_reg <= status_valid_next;
end
last_cycle_tuser_reg <= last_cycle_tuser_next;
status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next;
@ -468,32 +485,41 @@ always @(posedge clk) begin
if (store_last_word) begin
last_word_data_reg <= output_axis_tdata_int;
last_word_keep_reg <= output_axis_tkeep_int;
last_word_id_reg <= output_axis_tid_int;
last_word_dest_reg <= output_axis_tdest_int;
last_word_user_reg <= output_axis_tuser_int;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg output_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] output_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] output_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] output_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
reg temp_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = KEEP_ENABLE ? output_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tid = ID_ENABLE ? output_axis_tid_reg : {ID_WIDTH{1'b0}};
assign output_axis_tdest = DEST_ENABLE ? output_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign output_axis_tuser = USER_ENABLE ? output_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
@ -506,7 +532,7 @@ always @* begin
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
@ -542,11 +568,15 @@ always @(posedge clk) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tid_reg <= output_axis_tid_int;
output_axis_tdest_reg <= output_axis_tdest_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tid_reg <= temp_axis_tid_reg;
output_axis_tdest_reg <= temp_axis_tdest_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
@ -554,6 +584,8 @@ always @(posedge clk) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tid_reg <= output_axis_tid_int;
temp_axis_tdest_reg <= output_axis_tdest_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end

71
rtl/axis_frame_length_adjust_fifo.v
View File

@ -32,6 +32,14 @@ THE SOFTWARE.
module axis_frame_length_adjust_fifo #
(
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
)
@ -43,10 +51,13 @@ module axis_frame_length_adjust_fifo #
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
input wire [ID_WIDTH-1:0] input_axis_tid,
input wire [DEST_WIDTH-1:0] input_axis_tdest,
input wire [USER_WIDTH-1:0] input_axis_tuser,
/*
* AXI output
@ -58,10 +69,13 @@ module axis_frame_length_adjust_fifo #
output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
output wire [ID_WIDTH-1:0] output_axis_tid,
output wire [DEST_WIDTH-1:0] output_axis_tdest,
output wire [USER_WIDTH-1:0] output_axis_tuser,
/*
* Configuration
@ -71,10 +85,13 @@ module axis_frame_length_adjust_fifo #
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire fifo_axis_tuser;
wire [ID_WIDTH-1:0] fifo_axis_tid;
wire [DEST_WIDTH-1:0] fifo_axis_tdest;
wire [USER_WIDTH-1:0] fifo_axis_tuser;
wire status_valid;
wire status_ready;
@ -85,24 +102,35 @@ wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(1)
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(1),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(),
.output_axis_tkeep(fifo_axis_tkeep),
.output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast),
.output_axis_tid(fifo_axis_tid),
.output_axis_tdest(fifo_axis_tdest),
.output_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
@ -118,45 +146,70 @@ axis_frame_length_adjust_inst (
axis_fifo #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(fifo_axis_tdata),
.input_axis_tkeep(fifo_axis_tkeep),
.input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast),
.input_axis_tid(fifo_axis_tid),
.input_axis_tdest(fifo_axis_tdest),
.input_axis_tuser(fifo_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser)
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16)
.DATA_WIDTH(1+1+16+16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tkeep(0),
.input_axis_tvalid(status_valid),
.input_axis_tready(status_ready),
.input_axis_tlast(0),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(0),
// AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tkeep(),
.output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser()
);
endmodule

169
rtl/axis_frame_length_adjust_fifo_64.v
View File

@ -1,169 +0,0 @@
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length adjuster with FIFO (64 bit datapath)
*/
module axis_frame_length_adjust_fifo_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire output_axis_hdr_valid,
input wire output_axis_hdr_ready,
output wire output_axis_hdr_pad,
output wire output_axis_hdr_truncate,
output wire [15:0] output_axis_hdr_length,
output wire [15:0] output_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(fifo_axis_tdata),
.output_axis_tkeep(fifo_axis_tkeep),
.output_axis_tvalid(fifo_axis_tvalid),
.output_axis_tready(fifo_axis_tready),
.output_axis_tlast(fifo_axis_tlast),
.output_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo_64 #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(fifo_axis_tdata),
.input_axis_tkeep(fifo_axis_tkeep),
.input_axis_tvalid(fifo_axis_tvalid),
.input_axis_tready(fifo_axis_tready),
.input_axis_tlast(fifo_axis_tlast),
.input_axis_tuser(fifo_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DATA_WIDTH(1+1+16+16)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.input_axis_tvalid(status_valid),
.input_axis_tready(status_ready),
.input_axis_tlast(0),
.input_axis_tuser(0),
// AXI output
.output_axis_tdata({output_axis_hdr_pad, output_axis_hdr_truncate, output_axis_hdr_length, output_axis_hdr_original_length}),
.output_axis_tvalid(output_axis_hdr_valid),
.output_axis_tready(output_axis_hdr_ready),
.output_axis_tlast(),
.output_axis_tuser()
);
endmodule

41
tb/test_axis_frame_length_adjust_64.py
View File

@ -44,7 +44,14 @@ def bench():
# Parameters
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs
clk = Signal(bool(0))
@ -52,10 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
@ -64,10 +73,12 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0))
@ -89,6 +100,8 @@ def bench():
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
@ -104,6 +117,8 @@ def bench():
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -136,6 +151,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
@ -143,6 +160,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
@ -206,7 +225,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
@ -243,8 +262,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
@ -297,10 +316,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1
test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
@ -323,7 +342,7 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)

36
tb/test_axis_frame_length_adjust_64.v
View File

@ -32,8 +32,15 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_64;
// Parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
@ -56,7 +65,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
@ -73,6 +84,8 @@ initial begin
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser,
output_axis_tready,
status_ready,
@ -85,6 +98,8 @@ initial begin
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
status_valid,
status_frame_pad,
@ -100,7 +115,14 @@ end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
@ -111,6 +133,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
@ -118,6 +142,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status
.status_valid(status_valid),

41
tb/test_axis_frame_length_adjust_8.py
View File

@ -44,7 +44,14 @@ def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
# Inputs
clk = Signal(bool(0))
@ -52,10 +59,12 @@ def bench():
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_tready = Signal(bool(0))
status_ready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
@ -64,10 +73,12 @@ def bench():
# Outputs
input_axis_tready = Signal(bool(0))
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
status_valid = Signal(bool(0))
status_frame_pad = Signal(bool(0))
status_frame_truncate = Signal(bool(0))
@ -89,6 +100,8 @@ def bench():
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
@ -104,6 +117,8 @@ def bench():
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -136,6 +151,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_tdata=output_axis_tdata,
@ -143,6 +160,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
status_valid=status_valid,
@ -206,7 +225,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame)
@ -243,8 +262,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
@ -297,10 +316,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1
test_frame1.last_cycle_user = 1
for wait in wait_normal, wait_pause_source, wait_pause_sink:
source.send(test_frame1)
@ -323,7 +342,7 @@ def bench():
assert lrx <= lmax
assert rx_frame.data[:lm] == test_frame1.data[:lm]
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
status = status_sink.recv()
assert status.data[0][0] == (lt < lmin)

36
tb/test_axis_frame_length_adjust_8.v
View File

@ -32,8 +32,15 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_8;
// Parameters
localparam DATA_WIDTH = 8;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
@ -44,7 +51,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
@ -56,7 +65,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
@ -73,6 +84,8 @@ initial begin
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser,
output_axis_tready,
status_ready,
@ -85,6 +98,8 @@ initial begin
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser,
status_valid,
status_frame_pad,
@ -100,7 +115,14 @@ end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
@ -111,6 +133,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
@ -118,6 +142,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Status
.status_valid(status_valid),

44
tb/test_axis_frame_length_adjust_fifo.py
View File

@ -46,6 +46,14 @@ def bench():
# Parameters
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 12
HEADER_FIFO_ADDR_WIDTH = 3
@ -55,9 +63,12 @@ def bench():
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
@ -71,9 +82,12 @@ def bench():
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
@ -86,9 +100,12 @@ def bench():
clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
@ -100,9 +117,12 @@ def bench():
clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -131,9 +151,12 @@ def bench():
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
@ -143,9 +166,12 @@ def bench():
output_axis_hdr_length=output_axis_hdr_length,
output_axis_hdr_original_length=output_axis_hdr_original_length,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
@ -184,7 +210,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal,:
source.send(test_frame)
@ -225,8 +251,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal,:
source.send(test_frame1)
@ -281,10 +307,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1
test_frame1.last_cycle_user = 1
for wait in wait_normal,:
source.send(test_frame1)
@ -314,7 +340,7 @@ def bench():
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()

44
tb/test_axis_frame_length_adjust_fifo.v
View File

@ -32,9 +32,17 @@ THE SOFTWARE.
module test_axis_frame_length_adjust_fifo;
// Parameters
localparam DATA_WIDTH = 8;
localparam FRAME_FIFO_ADDR_WIDTH = 12;
localparam HEADER_FIFO_ADDR_WIDTH = 3;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 12;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs
reg clk = 0;
@ -42,9 +50,12 @@ reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0;
reg [15:0] length_min = 0;
@ -53,9 +64,12 @@ reg [15:0] length_max = 0;
// Outputs
wire input_axis_tready;
wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire output_axis_hdr_valid;
wire output_axis_hdr_pad;
wire output_axis_hdr_truncate;
@ -69,8 +83,11 @@ initial begin
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
@ -85,8 +102,11 @@ initial begin
output_axis_hdr_length,
output_axis_hdr_original_length,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser
);
@ -97,6 +117,14 @@ end
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
)
@ -105,9 +133,12 @@ UUT (
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_hdr_valid(output_axis_hdr_valid),
@ -117,9 +148,12 @@ UUT (
.output_axis_hdr_length(output_axis_hdr_length),
.output_axis_hdr_original_length(output_axis_hdr_original_length),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Configuration
.length_min(length_min),

46
tb/test_axis_frame_length_adjust_fifo_64.py
View File

@ -28,15 +28,14 @@ import os
import axis_ep
module = 'axis_frame_length_adjust_fifo_64'
testbench = 'test_%s' % module
module = 'axis_frame_length_adjust_fifo'
testbench = 'test_%s_64' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_frame_length_adjust.v")
srcs.append("../rtl/axis_fifo.v")
srcs.append("../rtl/axis_fifo_64.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)
@ -47,7 +46,14 @@ def bench():
# Parameters
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)
ID_ENABLE = 1
ID_WIDTH = 8
DEST_ENABLE = 1
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 9
HEADER_FIFO_ADDR_WIDTH = 3
@ -57,10 +63,12 @@ def bench():
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
input_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
input_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
input_axis_tid = Signal(intbv(0)[ID_WIDTH:])
input_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
input_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
output_axis_hdr_ready = Signal(bool(0))
output_axis_tready = Signal(bool(0))
length_min = Signal(intbv(0)[16:])
@ -74,10 +82,12 @@ def bench():
output_axis_hdr_length = Signal(intbv(0)[16:])
output_axis_hdr_original_length = Signal(intbv(0)[16:])
output_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
output_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
output_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
output_axis_tid = Signal(intbv(0)[ID_WIDTH:])
output_axis_tdest = Signal(intbv(0)[DEST_WIDTH:])
output_axis_tuser = Signal(intbv(0)[USER_WIDTH:])
# sources and sinks
source_pause = Signal(bool(0))
@ -94,6 +104,8 @@ def bench():
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tid=input_axis_tid,
tdest=input_axis_tdest,
tuser=input_axis_tuser,
pause=source_pause,
name='source'
@ -109,6 +121,8 @@ def bench():
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tid=output_axis_tid,
tdest=output_axis_tdest,
tuser=output_axis_tuser,
pause=sink_pause,
name='sink'
@ -141,6 +155,8 @@ def bench():
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tid=input_axis_tid,
input_axis_tdest=input_axis_tdest,
input_axis_tuser=input_axis_tuser,
output_axis_hdr_valid=output_axis_hdr_valid,
@ -154,6 +170,8 @@ def bench():
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tid=output_axis_tid,
output_axis_tdest=output_axis_tdest,
output_axis_tuser=output_axis_tuser,
length_min=length_min,
@ -192,7 +210,7 @@ def bench():
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=1, dest=1)
for wait in wait_normal,:
source.send(test_frame)
@ -233,8 +251,8 @@ def bench():
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=2, dest=2)
for wait in wait_normal,:
source.send(test_frame1)
@ -289,10 +307,10 @@ def bench():
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)))
test_frame1 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=1)
test_frame2 = axis_ep.AXIStreamFrame(bytearray(range(payload_len)), id=3, dest=2)
test_frame1.user = 1
test_frame1.last_cycle_user = 1
for wait in wait_normal,:
source.send(test_frame1)
@ -322,7 +340,7 @@ def bench():
assert hdr.data[0][1] == (lt > lmax)
assert hdr.data[0][2] == lrx
assert hdr.data[0][3] == lt
assert rx_frame.user[-1]
assert rx_frame.last_cycle_user
rx_frame = sink.recv()

42
tb/test_axis_frame_length_adjust_fifo_64.v
View File

@ -27,15 +27,22 @@ THE SOFTWARE.
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust_fifo_64
* Testbench for axis_frame_length_adjust_fifo
*/
module test_axis_frame_length_adjust_fifo_64;
// Parameters
localparam DATA_WIDTH = 64;
localparam KEEP_WIDTH = (DATA_WIDTH/8);
localparam FRAME_FIFO_ADDR_WIDTH = 9;
localparam HEADER_FIFO_ADDR_WIDTH = 3;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 9;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
// Inputs
reg clk = 0;
@ -46,7 +53,9 @@ reg [DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg [ID_WIDTH-1:0] input_axis_tid = 0;
reg [DEST_WIDTH-1:0] input_axis_tdest = 0;
reg [USER_WIDTH-1:0] input_axis_tuser = 0;
reg output_axis_hdr_ready = 0;
reg output_axis_tready = 0;
reg [15:0] length_min = 0;
@ -58,7 +67,9 @@ wire [DATA_WIDTH-1:0] output_axis_tdata;
wire [KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [ID_WIDTH-1:0] output_axis_tid;
wire [DEST_WIDTH-1:0] output_axis_tdest;
wire [USER_WIDTH-1:0] output_axis_tuser;
wire output_axis_hdr_valid;
wire output_axis_hdr_pad;
wire output_axis_hdr_truncate;
@ -75,6 +86,8 @@ initial begin
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tid,
input_axis_tdest,
input_axis_tuser,
output_axis_hdr_ready,
output_axis_tready,
@ -92,6 +105,8 @@ initial begin
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tid,
output_axis_tdest,
output_axis_tuser
);
@ -100,9 +115,16 @@ initial begin
$dumpvars(0, test_axis_frame_length_adjust_fifo_64);
end
axis_frame_length_adjust_fifo_64 #(
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
)
@ -115,6 +137,8 @@ UUT (
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tid(input_axis_tid),
.input_axis_tdest(input_axis_tdest),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_hdr_valid(output_axis_hdr_valid),
@ -128,6 +152,8 @@ UUT (
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tid(output_axis_tid),
.output_axis_tdest(output_axis_tdest),
.output_axis_tuser(output_axis_tuser),
// Configuration
.length_min(length_min),