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Add missing serdes_rx_reset_req output to 10G MAC+PHY modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-02-22 17:36:01 -08:00
parent 5f15cdeb24
commit 77adf30dad
3 changed files with 6 additions and 0 deletions
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2
rtl/eth_mac_phy_10g.v
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@ -91,6 +91,7 @@ module eth_mac_phy_10g #
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* PTP
@ -151,6 +152,7 @@ eth_mac_phy_10g_rx_inst (
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.ptp_ts(rx_ptp_ts),
.rx_start_packet(rx_start_packet),
.rx_error_count(rx_error_count),

2
rtl/eth_mac_phy_10g_fifo.v
View File

@ -118,6 +118,7 @@ module eth_mac_phy_10g_fifo #
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
@ -406,6 +407,7 @@ eth_mac_phy_10g_inst (
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),

2
rtl/eth_mac_phy_10g_rx.v
View File

@ -68,6 +68,7 @@ module eth_mac_phy_10g_rx #
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* PTP
@ -132,6 +133,7 @@ eth_phy_10g_rx_if_inst (
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),