diff --git a/example/Arty/fpga/fpga.xdc b/example/Arty/fpga/fpga.xdc
index 4bf23b38a..f26c74dba 100644
--- a/example/Arty/fpga/fpga.xdc
+++ b/example/Arty/fpga/fpga.xdc
@@ -7,7 +7,6 @@ set_property CONFIG_VOLTAGE 3.3                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
-set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]
diff --git a/example/NexysVideo/fpga/fpga.xdc b/example/NexysVideo/fpga/fpga.xdc
index b83cb2194..d56cf8375 100644
--- a/example/NexysVideo/fpga/fpga.xdc
+++ b/example/NexysVideo/fpga/fpga.xdc
@@ -5,7 +5,6 @@
 set_property CFGBVS VCCO                               [current_design]
 set_property CONFIG_VOLTAGE 3.3                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
-set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]