From 786eabac4b5d56106f32d0aba97082839d21f3f5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 20 Oct 2021 02:01:33 -0700 Subject: [PATCH] Add missing wires --- rtl/eth_mac_phy_10g_fifo.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 66182d888..012eaaf53 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -201,6 +201,9 @@ end wire rx_error_bad_frame_int; wire rx_error_bad_fcs_int; +wire rx_bad_block_int; +wire rx_block_lock_int; +wire rx_high_ber_int; reg [4:0] rx_sync_reg_1 = 5'd0; reg [4:0] rx_sync_reg_2 = 5'd0;