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Update readme

This commit is contained in:
Alex Forencich 2020-08-06 23:26:20 -07:00
parent e6b35f0567
commit 788bfe1aa5

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@ -38,6 +38,7 @@ devices. Designs are included for the following FPGA boards:
* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)
* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)
* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)
For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and
PHY modules from the verilog-ethernet repository, no extra licenses are