From 788bfe1aa58f5173f01e926fe59cf25c1e8126c5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 6 Aug 2020 23:26:20 -0700 Subject: [PATCH] Update readme --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index c85cbf5bb..9ed5f8445 100644 --- a/README.md +++ b/README.md @@ -38,6 +38,7 @@ devices. Designs are included for the following FPGA boards: * Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) * Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P) * Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P) +* Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV) For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are