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fpga/mqnic/VCU118: Use QSFP Si570 for both QSFP modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-19 17:49:46 -07:00
parent 7d2f77a30b
commit 789512c6da
4 changed files with 16 additions and 86 deletions
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6
fpga/mqnic/VCU118/fpga_100g/fpga.xdc
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@ -183,8 +183,8 @@ set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHAN
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34
#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12
@ -196,7 +196,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_i
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
# 156.25 MHz MGT reference clock
create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]

45
fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
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@ -225,8 +225,8 @@ module fpga #
output wire qsfp2_tx4_n,
input wire qsfp2_rx4_p,
input wire qsfp2_rx4_n,
input wire qsfp2_mgt_refclk_0_p,
input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_0_p,
// input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_1_p,
// input wire qsfp2_mgt_refclk_1_n,
// output wire qsfp2_recclk_p,
@ -1115,41 +1115,6 @@ wire qsfp2_drp_rdy;
wire qsfp2_rx_status;
wire qsfp2_gtpowergood;
wire qsfp2_mgt_refclk_0;
wire qsfp2_mgt_refclk_0_int;
wire qsfp2_mgt_refclk_0_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst (
.I (qsfp2_mgt_refclk_0_p),
.IB (qsfp2_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp2_mgt_refclk_0),
.ODIV2 (qsfp2_mgt_refclk_0_int)
);
BUFG_GT bufg_gt_qsfp2_mgt_refclk_0_inst (
.CE (qsfp2_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp2_mgt_refclk_0_int),
.O (qsfp2_mgt_refclk_0_bufg)
);
wire qsfp2_rst;
sync_reset #(
.N(4)
)
qsfp2_sync_reset_inst (
.clk(qsfp2_mgt_refclk_0_bufg),
.rst(rst_125mhz_int),
.out(qsfp2_rst)
);
cmac_gty_wrapper #(
.DRP_CLK_FREQ_HZ(125000000),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
@ -1160,13 +1125,13 @@ cmac_gty_wrapper #(
)
qsfp2_cmac_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp2_rst),
.xcvr_ctrl_rst(qsfp1_rst),
/*
* Common
*/
.xcvr_gtpowergood_out(qsfp2_gtpowergood),
.xcvr_ref_clk(qsfp2_mgt_refclk_0),
.xcvr_gtpowergood_out(),
.xcvr_ref_clk(qsfp1_mgt_refclk_0),
/*
* DRP

6
fpga/mqnic/VCU118/fpga_25g/fpga.xdc
View File

@ -183,8 +183,8 @@ set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHAN
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34
#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12
@ -196,7 +196,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_i
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
# 156.25 MHz MGT reference clock
create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]

45
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -229,8 +229,8 @@ module fpga #
output wire qsfp2_tx4_n,
input wire qsfp2_rx4_p,
input wire qsfp2_rx4_n,
input wire qsfp2_mgt_refclk_0_p,
input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_0_p,
// input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_1_p,
// input wire qsfp2_mgt_refclk_1_n,
// output wire qsfp2_recclk_p,
@ -1211,41 +1211,6 @@ wire qsfp2_rx_status_3;
wire qsfp2_rx_block_lock_4;
wire qsfp2_rx_status_4;
wire qsfp2_gtpowergood;
wire qsfp2_mgt_refclk_0;
wire qsfp2_mgt_refclk_0_int;
wire qsfp2_mgt_refclk_0_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst (
.I (qsfp2_mgt_refclk_0_p),
.IB (qsfp2_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp2_mgt_refclk_0),
.ODIV2 (qsfp2_mgt_refclk_0_int)
);
BUFG_GT bufg_gt_qsfp2_mgt_refclk_0_inst (
.CE (qsfp2_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp2_mgt_refclk_0_int),
.O (qsfp2_mgt_refclk_0_bufg)
);
wire qsfp2_rst;
sync_reset #(
.N(4)
)
qsfp2_sync_reset_inst (
.clk(qsfp2_mgt_refclk_0_bufg),
.rst(rst_125mhz_int),
.out(qsfp2_rst)
);
eth_xcvr_phy_10g_gty_quad_wrapper #(
.PRBS31_ENABLE(1),
.TX_SERDES_PIPELINE(1),
@ -1254,13 +1219,13 @@ eth_xcvr_phy_10g_gty_quad_wrapper #(
)
qsfp2_phy_quad_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp2_rst),
.xcvr_ctrl_rst(qsfp1_rst),
/*
* Common
*/
.xcvr_gtpowergood_out(qsfp2_gtpowergood),
.xcvr_ref_clk(qsfp2_mgt_refclk_0),
.xcvr_gtpowergood_out(),
.xcvr_ref_clk(qsfp1_mgt_refclk_0),
/*
* DRP