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Minor optimization
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0c6bb169bc
commit
78d755ea9a
@ -490,6 +490,7 @@ always @* begin
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op_count_next = s_axis_write_desc_len;
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tag_next = s_axis_write_desc_tag;
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// TLP size computation
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if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin
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// packet smaller than max payload size
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if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
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@ -550,6 +551,7 @@ always @* begin
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op_table_start_tag = tag_reg;
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op_table_start_en = 1'b1;
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// TLP size computation
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if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin
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// packet smaller than max payload size
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if (((pcie_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
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@ -695,7 +697,8 @@ always @* begin
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if (!read_last_cycle_reg) begin
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read_state_next = READ_STATE_READ;
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end else if (read_cmd_valid_reg) begin
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end else begin
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// skip idle state
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read_pcie_addr_next = read_cmd_pcie_addr_reg;
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read_ram_sel_next = read_cmd_ram_sel_reg;
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@ -725,11 +728,12 @@ always @* begin
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read_ram_mask_next = read_ram_mask_0_next | read_ram_mask_1_next;
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end
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read_cmd_ready = 1'b1;
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read_state_next = READ_STATE_READ;
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end else begin
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read_state_next = READ_STATE_IDLE;
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if (read_cmd_valid_reg) begin
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read_cmd_ready = 1'b1;
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read_state_next = READ_STATE_READ;
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end else begin
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read_state_next = READ_STATE_IDLE;
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end
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end
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end else begin
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read_state_next = READ_STATE_READ;
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