mirror of
https://github.com/corundum/corundum.git
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Rename AU200 to Alveo
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
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@ -1,8 +1,8 @@
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# Corundum mqnic for Alveo U200/Alveo U250/VCU1525
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# Corundum mqnic for Alveo
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## Introduction
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This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
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This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
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* FPGA
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* AU200: xcu200-fsgd2104-2-e
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@ -10,7 +10,10 @@ This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
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* VCU1525: xcvu9p-fsgd2104-2L-e
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* MAC: Xilinx 100G CMAC
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* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
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* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* RAM
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* AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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## Quick start
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au200.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au200.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au250.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au250.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -112,7 +112,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_vcu1525.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -119,7 +119,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_vcu1525.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -1,15 +1,18 @@
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# Corundum mqnic for Alveo U200/Alveo U250/VCU1525
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# Corundum mqnic for Alveo
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## Introduction
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This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
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This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
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* FPGA
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* AU200: xcu200-fsgd2104-2-e
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* AU250: xcu250-fsgd2104-2-e
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* VCU1525: xcvu9p-fsgd2104-2L-e
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* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* RAM
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* AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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* VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM)
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## Quick start
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au200.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au200.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au250.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_au250.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_vcu1525.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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@ -7,7 +7,7 @@ FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga.v
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SYN_FILES = rtl/fpga_au200.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/debounce_switch.v
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SYN_FILES += rtl/sync_signal.v
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@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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# XDC files
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XDC_FILES = fpga.xdc
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XDC_FILES = fpga_au200.xdc
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XDC_FILES += placement_vcu1525.xdc
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XDC_FILES += cfgmclk.xdc
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XDC_FILES += boot.xdc
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