From 7914445ac05e35d85c56485759f1e2212b1b48cf Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 7 Nov 2023 22:48:37 -0800 Subject: [PATCH] Rename AU200 to Alveo Signed-off-by: Alex Forencich --- fpga/mqnic/{AU200 => Alveo}/fpga_100g/Makefile | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/README.md | 9 ++++++--- fpga/mqnic/{AU200 => Alveo}/fpga_100g/app | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/boot.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/cfgmclk.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/common/vivado.mk | 0 .../mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU200/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_100g/fpga_AU200/config.tcl | 0 .../fpga_100g/fpga_AU200_app_dma_bench/Makefile | 4 ++-- .../fpga_100g/fpga_AU200_app_dma_bench/config.tcl | 0 .../mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU250/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_100g/fpga_AU250/config.tcl | 0 .../fpga_100g/fpga_AU250_app_dma_bench/Makefile | 4 ++-- .../fpga_100g/fpga_AU250_app_dma_bench/config.tcl | 0 .../{AU200 => Alveo}/fpga_100g/fpga_VCU1525/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_100g/fpga_VCU1525/config.tcl | 0 .../fpga_100g/fpga_VCU1525_app_dma_bench/Makefile | 4 ++-- .../fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl | 0 .../fpga.xdc => Alveo/fpga_100g/fpga_au200.xdc} | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cmac_gty.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cmac_usplus.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cms.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/ddr4_0.tcl | 0 .../fpga_100g/ip/pcie4_uscale_plus_0.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/lib | 0 .../mqnic/{AU200 => Alveo}/fpga_100g/placement_au200.xdc | 0 .../mqnic/{AU200 => Alveo}/fpga_100g/placement_au250.xdc | 0 .../{AU200 => Alveo}/fpga_100g/placement_vcu1525.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/common | 0 .../{AU200 => Alveo}/fpga_100g/rtl/debounce_switch.v | 0 .../rtl/fpga.v => Alveo/fpga_100g/rtl/fpga_au200.v} | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/fpga_core.v | 0 fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/sync_signal.v | 0 .../{AU200 => Alveo}/fpga_100g/tb/fpga_core/Makefile | 0 .../{AU200 => Alveo}/fpga_100g/tb/fpga_core/mqnic.py | 0 .../fpga_100g/tb/fpga_core/test_fpga_core.py | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/Makefile | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/README.md | 9 ++++++--- fpga/mqnic/{AU200 => Alveo}/fpga_25g/app | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/boot.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/cfgmclk.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/common/vivado.mk | 0 .../fpga_25g/fpga_AU200}/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_25g/fpga_AU200/config.tcl | 0 .../fpga_25g/fpga_AU200_10g}/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/config.tcl | 0 .../fpga_25g/fpga_AU250}/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_25g/fpga_AU250/config.tcl | 0 .../fpga_25g/fpga_AU250_10g}/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/config.tcl | 0 .../{AU200 => Alveo}/fpga_25g/fpga_VCU1525/Makefile | 4 ++-- .../{AU200 => Alveo}/fpga_25g/fpga_VCU1525/config.tcl | 0 .../{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/Makefile | 4 ++-- .../fpga_25g/fpga_VCU1525_10g/config.tcl | 0 .../fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au200.xdc} | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/cms.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/ddr4_0.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/eth_xcvr_gty.tcl | 0 .../{AU200 => Alveo}/fpga_25g/ip/pcie4_uscale_plus_0.tcl | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/lib | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/placement_au200.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/placement_au250.xdc | 0 .../{AU200 => Alveo}/fpga_25g/placement_vcu1525.xdc | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/common | 0 .../{AU200 => Alveo}/fpga_25g/rtl/debounce_switch.v | 0 .../rtl/fpga.v => Alveo/fpga_25g/rtl/fpga_au200.v} | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/fpga_core.v | 0 fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/sync_signal.v | 0 .../{AU200 => Alveo}/fpga_25g/tb/fpga_core/Makefile | 0 .../{AU200 => Alveo}/fpga_25g/tb/fpga_core/mqnic.py | 0 .../fpga_25g/tb/fpga_core/test_fpga_core.py | 0 71 files changed, 36 insertions(+), 30 deletions(-) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/Makefile (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/README.md (79%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/app (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/boot.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/cfgmclk.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/common/vivado.mk (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU200/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU200/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU200_app_dma_bench/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU200_app_dma_bench/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU250/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU250/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU250_app_dma_bench/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_AU250_app_dma_bench/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_VCU1525/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_VCU1525/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl (100%) rename fpga/mqnic/{AU200/fpga_100g/fpga.xdc => Alveo/fpga_100g/fpga_au200.xdc} (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cmac_gty.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cmac_usplus.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/cms.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/ddr4_0.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/ip/pcie4_uscale_plus_0.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/lib (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/placement_au200.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/placement_au250.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/placement_vcu1525.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/common (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/debounce_switch.v (100%) rename fpga/mqnic/{AU200/fpga_100g/rtl/fpga.v => Alveo/fpga_100g/rtl/fpga_au200.v} (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/fpga_core.v (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/rtl/sync_signal.v (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/tb/fpga_core/Makefile (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/tb/fpga_core/mqnic.py (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_100g/tb/fpga_core/test_fpga_core.py (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/Makefile (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/README.md (78%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/app (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/boot.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/cfgmclk.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/common/vivado.mk (100%) rename fpga/mqnic/{AU200/fpga_25g/fpga_AU200_10g => Alveo/fpga_25g/fpga_AU200}/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_AU200/config.tcl (100%) rename fpga/mqnic/{AU200/fpga_25g/fpga_AU200 => Alveo/fpga_25g/fpga_AU200_10g}/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_AU200_10g/config.tcl (100%) rename fpga/mqnic/{AU200/fpga_25g/fpga_AU250_10g => Alveo/fpga_25g/fpga_AU250}/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_AU250/config.tcl (100%) rename fpga/mqnic/{AU200/fpga_25g/fpga_AU250 => Alveo/fpga_25g/fpga_AU250_10g}/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_AU250_10g/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_VCU1525/config.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/Makefile (99%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/fpga_VCU1525_10g/config.tcl (100%) rename fpga/mqnic/{AU200/fpga_25g/fpga.xdc => Alveo/fpga_25g/fpga_au200.xdc} (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/cms.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/ddr4_0.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/eth_xcvr_gty.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/ip/pcie4_uscale_plus_0.tcl (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/lib (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/placement_au200.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/placement_au250.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/placement_vcu1525.xdc (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/common (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/debounce_switch.v (100%) rename fpga/mqnic/{AU200/fpga_25g/rtl/fpga.v => Alveo/fpga_25g/rtl/fpga_au200.v} (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/fpga_core.v (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/rtl/sync_signal.v (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/tb/fpga_core/Makefile (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/tb/fpga_core/mqnic.py (100%) rename fpga/mqnic/{AU200 => Alveo}/fpga_25g/tb/fpga_core/test_fpga_core.py (100%) diff --git a/fpga/mqnic/AU200/fpga_100g/Makefile b/fpga/mqnic/Alveo/fpga_100g/Makefile similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/Makefile rename to fpga/mqnic/Alveo/fpga_100g/Makefile diff --git a/fpga/mqnic/AU200/fpga_100g/README.md b/fpga/mqnic/Alveo/fpga_100g/README.md similarity index 79% rename from fpga/mqnic/AU200/fpga_100g/README.md rename to fpga/mqnic/Alveo/fpga_100g/README.md index ac27f400e..72aeeb15d 100644 --- a/fpga/mqnic/AU200/fpga_100g/README.md +++ b/fpga/mqnic/Alveo/fpga_100g/README.md @@ -1,8 +1,8 @@ -# Corundum mqnic for Alveo U200/Alveo U250/VCU1525 +# Corundum mqnic for Alveo ## Introduction -This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. +This design targets multiple FPGA boards, including most of the Xilinx Alveo line. * FPGA * AU200: xcu200-fsgd2104-2-e @@ -10,7 +10,10 @@ This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. * VCU1525: xcvu9p-fsgd2104-2L-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) +* RAM + * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM) + * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM) + * VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## Quick start diff --git a/fpga/mqnic/AU200/fpga_100g/app b/fpga/mqnic/Alveo/fpga_100g/app similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/app rename to fpga/mqnic/Alveo/fpga_100g/app diff --git a/fpga/mqnic/AU200/fpga_100g/boot.xdc b/fpga/mqnic/Alveo/fpga_100g/boot.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/boot.xdc rename to fpga/mqnic/Alveo/fpga_100g/boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/cfgmclk.xdc b/fpga/mqnic/Alveo/fpga_100g/cfgmclk.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/cfgmclk.xdc rename to fpga/mqnic/Alveo/fpga_100g/cfgmclk.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/common/vivado.mk b/fpga/mqnic/Alveo/fpga_100g/common/vivado.mk similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/common/vivado.mk rename to fpga/mqnic/Alveo/fpga_100g/common/vivado.mk diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile index dd4d524fc..7cd0e5779 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU200/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU200/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU200/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile index e71b9a4e2..8b1201b45 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU200_app_dma_bench/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile index 2c62771be..d1d91143e 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU250/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU250/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU250/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile index f8e9cdc92..02329da53 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_AU250_app_dma_bench/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile index 1e2590bad..07a2fa1da 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -112,7 +112,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_VCU1525/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile rename to fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile index c99698d06..9eab57e34 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile +++ b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -119,7 +119,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl b/fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl rename to fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga.xdc b/fpga/mqnic/Alveo/fpga_100g/fpga_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/fpga.xdc rename to fpga/mqnic/Alveo/fpga_100g/fpga_au200.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/ip/cmac_gty.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/cmac_gty.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/ip/cmac_gty.tcl rename to fpga/mqnic/Alveo/fpga_100g/ip/cmac_gty.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/ip/cmac_usplus.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/ip/cmac_usplus.tcl rename to fpga/mqnic/Alveo/fpga_100g/ip/cmac_usplus.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/ip/cms.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/cms.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/ip/cms.tcl rename to fpga/mqnic/Alveo/fpga_100g/ip/cms.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/ddr4_0.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl rename to fpga/mqnic/Alveo/fpga_100g/ip/ddr4_0.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/Alveo/fpga_100g/ip/pcie4_uscale_plus_0.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/ip/pcie4_uscale_plus_0.tcl rename to fpga/mqnic/Alveo/fpga_100g/ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/lib b/fpga/mqnic/Alveo/fpga_100g/lib similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/lib rename to fpga/mqnic/Alveo/fpga_100g/lib diff --git a/fpga/mqnic/AU200/fpga_100g/placement_au200.xdc b/fpga/mqnic/Alveo/fpga_100g/placement_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/placement_au200.xdc rename to fpga/mqnic/Alveo/fpga_100g/placement_au200.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/placement_au250.xdc b/fpga/mqnic/Alveo/fpga_100g/placement_au250.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/placement_au250.xdc rename to fpga/mqnic/Alveo/fpga_100g/placement_au250.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/placement_vcu1525.xdc b/fpga/mqnic/Alveo/fpga_100g/placement_vcu1525.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/placement_vcu1525.xdc rename to fpga/mqnic/Alveo/fpga_100g/placement_vcu1525.xdc diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/common b/fpga/mqnic/Alveo/fpga_100g/rtl/common similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/rtl/common rename to fpga/mqnic/Alveo/fpga_100g/rtl/common diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/debounce_switch.v b/fpga/mqnic/Alveo/fpga_100g/rtl/debounce_switch.v similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/rtl/debounce_switch.v rename to fpga/mqnic/Alveo/fpga_100g/rtl/debounce_switch.v diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/rtl/fpga.v rename to fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v rename to fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/sync_signal.v b/fpga/mqnic/Alveo/fpga_100g/rtl/sync_signal.v similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/rtl/sync_signal.v rename to fpga/mqnic/Alveo/fpga_100g/rtl/sync_signal.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile rename to fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/Makefile diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/mqnic.py b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/mqnic.py similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/tb/fpga_core/mqnic.py rename to fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/mqnic.py diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py rename to fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.py diff --git a/fpga/mqnic/AU200/fpga_25g/Makefile b/fpga/mqnic/Alveo/fpga_25g/Makefile similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/Makefile rename to fpga/mqnic/Alveo/fpga_25g/Makefile diff --git a/fpga/mqnic/AU200/fpga_25g/README.md b/fpga/mqnic/Alveo/fpga_25g/README.md similarity index 78% rename from fpga/mqnic/AU200/fpga_25g/README.md rename to fpga/mqnic/Alveo/fpga_25g/README.md index db96227e9..025e03cf4 100644 --- a/fpga/mqnic/AU200/fpga_25g/README.md +++ b/fpga/mqnic/Alveo/fpga_25g/README.md @@ -1,15 +1,18 @@ -# Corundum mqnic for Alveo U200/Alveo U250/VCU1525 +# Corundum mqnic for Alveo ## Introduction -This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board. +This design targets multiple FPGA boards, including most of the Xilinx Alveo line. * FPGA * AU200: xcu200-fsgd2104-2-e * AU250: xcu250-fsgd2104-2-e * VCU1525: xcvu9p-fsgd2104-2L-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver -* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) +* RAM + * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM) + * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM) + * VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## Quick start diff --git a/fpga/mqnic/AU200/fpga_25g/app b/fpga/mqnic/Alveo/fpga_25g/app similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/app rename to fpga/mqnic/Alveo/fpga_25g/app diff --git a/fpga/mqnic/AU200/fpga_25g/boot.xdc b/fpga/mqnic/Alveo/fpga_25g/boot.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/boot.xdc rename to fpga/mqnic/Alveo/fpga_25g/boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/cfgmclk.xdc b/fpga/mqnic/Alveo/fpga_25g/cfgmclk.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/cfgmclk.xdc rename to fpga/mqnic/Alveo/fpga_25g/cfgmclk.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/common/vivado.mk b/fpga/mqnic/Alveo/fpga_25g/common/vivado.mk similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/common/vivado.mk rename to fpga/mqnic/Alveo/fpga_25g/common/vivado.mk diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile index 43fbeb4e2..4c102934f 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU200/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU200/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile index 43fbeb4e2..4c102934f 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU200/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au200.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU200_10g/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile index 68e4d5b0f..09da593c4 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU250/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU250/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile index 68e4d5b0f..09da593c4 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_AU250/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_au250.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_AU250_10g/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile index 4b2572738..570e09770 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_VCU1525/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile similarity index 99% rename from fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile rename to fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile index 4b2572738..570e09770 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/Makefile +++ b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile @@ -7,7 +7,7 @@ FPGA_TOP = fpga FPGA_ARCH = virtexuplus # Files for synthesis -SYN_FILES = rtl/fpga.v +SYN_FILES = rtl/fpga_au200.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v @@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v SYN_FILES += lib/pcie/rtl/pulse_merge.v # XDC files -XDC_FILES = fpga.xdc +XDC_FILES = fpga_au200.xdc XDC_FILES += placement_vcu1525.xdc XDC_FILES += cfgmclk.xdc XDC_FILES += boot.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl b/fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga_VCU1525_10g/config.tcl rename to fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga.xdc b/fpga/mqnic/Alveo/fpga_25g/fpga_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/fpga.xdc rename to fpga/mqnic/Alveo/fpga_25g/fpga_au200.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/ip/cms.tcl b/fpga/mqnic/Alveo/fpga_25g/ip/cms.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/ip/cms.tcl rename to fpga/mqnic/Alveo/fpga_25g/ip/cms.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/Alveo/fpga_25g/ip/ddr4_0.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl rename to fpga/mqnic/Alveo/fpga_25g/ip/ddr4_0.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/ip/eth_xcvr_gty.tcl rename to fpga/mqnic/Alveo/fpga_25g/ip/eth_xcvr_gty.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/Alveo/fpga_25g/ip/pcie4_uscale_plus_0.tcl similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/ip/pcie4_uscale_plus_0.tcl rename to fpga/mqnic/Alveo/fpga_25g/ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/lib b/fpga/mqnic/Alveo/fpga_25g/lib similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/lib rename to fpga/mqnic/Alveo/fpga_25g/lib diff --git a/fpga/mqnic/AU200/fpga_25g/placement_au200.xdc b/fpga/mqnic/Alveo/fpga_25g/placement_au200.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/placement_au200.xdc rename to fpga/mqnic/Alveo/fpga_25g/placement_au200.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/placement_au250.xdc b/fpga/mqnic/Alveo/fpga_25g/placement_au250.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/placement_au250.xdc rename to fpga/mqnic/Alveo/fpga_25g/placement_au250.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/placement_vcu1525.xdc b/fpga/mqnic/Alveo/fpga_25g/placement_vcu1525.xdc similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/placement_vcu1525.xdc rename to fpga/mqnic/Alveo/fpga_25g/placement_vcu1525.xdc diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/common b/fpga/mqnic/Alveo/fpga_25g/rtl/common similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/rtl/common rename to fpga/mqnic/Alveo/fpga_25g/rtl/common diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/debounce_switch.v b/fpga/mqnic/Alveo/fpga_25g/rtl/debounce_switch.v similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/rtl/debounce_switch.v rename to fpga/mqnic/Alveo/fpga_25g/rtl/debounce_switch.v diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/rtl/fpga.v rename to fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v rename to fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/Alveo/fpga_25g/rtl/sync_signal.v similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/rtl/sync_signal.v rename to fpga/mqnic/Alveo/fpga_25g/rtl/sync_signal.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile rename to fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/Makefile diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/mqnic.py similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/tb/fpga_core/mqnic.py rename to fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/mqnic.py diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py similarity index 100% rename from fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py rename to fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py