Rename AU200 to Alveo

Signed-off-by: Alex Forencich <alex@alexforencich.com>

fpga/mqnic/Alveo/fpga_100g/README.md

@@ -1,8 +1,8 @@
-# Corundum mqnic for Alveo U200/Alveo U250/VCU1525
+# Corundum mqnic for Alveo
 
 ## Introduction
 
-This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
+This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
 
 * FPGA
   * AU200: xcu200-fsgd2104-2-e
@@ -10,7 +10,10 @@ This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
   * VCU1525: xcvu9p-fsgd2104-2L-e
 * MAC: Xilinx 100G CMAC
 * PHY: 100G CAUI-4 CMAC and internal GTY transceivers
-* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+* RAM
+  * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+  * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+  * VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM)
 
 ## Quick start
 

fpga/mqnic/Alveo/fpga_100g/fpga_AU200/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au200.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_100g/fpga_AU200_app_dma_bench/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au200.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_100g/fpga_AU250/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -115,7 +115,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au250.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_100g/fpga_AU250_app_dma_bench/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -122,7 +122,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au250.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -112,7 +112,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_vcu1525.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_100g/fpga_VCU1525_app_dma_bench/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -119,7 +119,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_vcu1525.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/README.md

@@ -1,15 +1,18 @@
-# Corundum mqnic for Alveo U200/Alveo U250/VCU1525
+# Corundum mqnic for Alveo
 
 ## Introduction
 
-This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.
+This design targets multiple FPGA boards, including most of the Xilinx Alveo line.
 
 * FPGA
   * AU200: xcu200-fsgd2104-2-e
   * AU250: xcu250-fsgd2104-2-e
   * VCU1525: xcvu9p-fsgd2104-2L-e
 * PHY: 10G BASE-R PHY IP core and internal GTY transceiver
-* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+* RAM
+  * AU200: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+  * AU250: 64 GB DDR4 2400 (4x 2G x72 DIMM)
+  * VCU1525: 64 GB DDR4 2400 (4x 2G x72 DIMM)
 
 ## Quick start
 

fpga/mqnic/Alveo/fpga_25g/fpga_AU200/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au200.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/fpga_AU200_10g/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au200.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/fpga_AU250/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au250.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/fpga_AU250_10g/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -134,7 +134,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_au250.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_vcu1525.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc

fpga/mqnic/Alveo/fpga_25g/fpga_VCU1525_10g/Makefile

@@ -7,7 +7,7 @@ FPGA_TOP = fpga
 FPGA_ARCH = virtexuplus
 
 # Files for synthesis
-SYN_FILES = rtl/fpga.v
+SYN_FILES = rtl/fpga_au200.v
 SYN_FILES += rtl/fpga_core.v
 SYN_FILES += rtl/debounce_switch.v
 SYN_FILES += rtl/sync_signal.v
@@ -131,7 +131,7 @@ SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
 SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
-XDC_FILES = fpga.xdc
+XDC_FILES = fpga_au200.xdc
 XDC_FILES += placement_vcu1525.xdc
 XDC_FILES += cfgmclk.xdc
 XDC_FILES += boot.xdc