diff --git a/lib/axis/rtl/arbiter.v b/lib/axis/rtl/arbiter.v
index cfac70d1c..762907788 100644
--- a/lib/axis/rtl/arbiter.v
+++ b/lib/axis/rtl/arbiter.v
@@ -141,16 +141,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    grant_reg <= grant_next;
+    grant_valid_reg <= grant_valid_next;
+    grant_encoded_reg <= grant_encoded_next;
+    mask_reg <= mask_next;
+
     if (rst) begin
         grant_reg <= 0;
         grant_valid_reg <= 0;
         grant_encoded_reg <= 0;
         mask_reg <= 0;
-    end else begin
-        grant_reg <= grant_next;
-        grant_valid_reg <= grant_valid_next;
-        grant_encoded_reg <= grant_encoded_next;
-        mask_reg <= mask_next;
     end
 end
 
diff --git a/lib/axis/rtl/axis_adapter.v b/lib/axis/rtl/axis_adapter.v
index 51aa226ac..2cea00b74 100644
--- a/lib/axis/rtl/axis_adapter.v
+++ b/lib/axis/rtl/axis_adapter.v
@@ -484,8 +484,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -516,15 +516,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -551,6 +545,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_arb_mux.v b/lib/axis/rtl/axis_arb_mux.v
index 43a588f41..f7e39f3ba 100644
--- a/lib/axis/rtl/axis_arb_mux.v
+++ b/lib/axis/rtl/axis_arb_mux.v
@@ -118,6 +118,15 @@ wire [S_COUNT-1:0] grant;
 wire grant_valid;
 wire [CL_S_COUNT-1:0] grant_encoded;
 
+// input registers to pipeline arbitration delay
+reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata_reg = 0;
+reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep_reg = 0;
+reg [S_COUNT-1:0]            s_axis_tvalid_reg = 0;
+reg [S_COUNT-1:0]            s_axis_tlast_reg = 0;
+reg [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid_reg = 0;
+reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest_reg = 0;
+reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser_reg = 0;
+
 // internal datapath
 reg  [DATA_WIDTH-1:0] m_axis_tdata_int;
 reg  [KEEP_WIDTH-1:0] m_axis_tkeep_int;
@@ -129,17 +138,17 @@ reg  [DEST_WIDTH-1:0] m_axis_tdest_int;
 reg  [USER_WIDTH-1:0] m_axis_tuser_int;
 wire                  m_axis_tready_int_early;
 
-assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
+assign s_axis_tready = ~s_axis_tvalid_reg | ({S_COUNT{m_axis_tready_int_reg}} & grant);
 
 // mux for incoming packet
-wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
-wire [KEEP_WIDTH-1:0] current_s_tkeep  = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
-wire                  current_s_tvalid = s_axis_tvalid[grant_encoded];
+wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata_reg[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
+wire [KEEP_WIDTH-1:0] current_s_tkeep  = s_axis_tkeep_reg[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
+wire                  current_s_tvalid = s_axis_tvalid_reg[grant_encoded];
 wire                  current_s_tready = s_axis_tready[grant_encoded];
-wire                  current_s_tlast  = s_axis_tlast[grant_encoded];
-wire [S_ID_WIDTH-1:0] current_s_tid    = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
-wire [DEST_WIDTH-1:0] current_s_tdest  = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
-wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
+wire                  current_s_tlast  = s_axis_tlast_reg[grant_encoded];
+wire [S_ID_WIDTH-1:0] current_s_tid    = s_axis_tid_reg[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
+wire [DEST_WIDTH-1:0] current_s_tdest  = s_axis_tdest_reg[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
+wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser_reg[grant_encoded*USER_WIDTH +: USER_WIDTH];
 
 // arbiter instance
 arbiter #(
@@ -159,8 +168,8 @@ arb_inst (
     .grant_encoded(grant_encoded)
 );
 
-assign request = s_axis_tvalid & ~grant;
-assign acknowledge = grant & s_axis_tvalid & s_axis_tready & (LAST_ENABLE ? s_axis_tlast : {S_COUNT{1'b1}});
+assign request = (s_axis_tvalid_reg & ~grant) | (s_axis_tvalid & grant);
+assign acknowledge = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_ENABLE ? s_axis_tlast_reg : {S_COUNT{1'b1}});
 
 always @* begin
     // pass through selected packet data
@@ -176,6 +185,27 @@ always @* begin
     m_axis_tuser_int  = current_s_tuser;
 end
 
+integer i;
+
+always @(posedge clk) begin
+    // register inputs
+    for (i = 0; i < S_COUNT; i = i + 1) begin
+        if (s_axis_tready[i]) begin
+            s_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata[i*DATA_WIDTH +: DATA_WIDTH];
+            s_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep[i*KEEP_WIDTH +: KEEP_WIDTH];
+            s_axis_tvalid_reg[i] <= s_axis_tvalid[i];
+            s_axis_tlast_reg[i] <= s_axis_tlast[i];
+            s_axis_tid_reg[i*S_ID_WIDTH +: S_ID_WIDTH_INT] <= s_axis_tid[i*S_ID_WIDTH +: S_ID_WIDTH_INT];
+            s_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest[i*DEST_WIDTH +: DEST_WIDTH];
+            s_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser[i*USER_WIDTH +: USER_WIDTH];
+        end
+    end
+
+    if (rst) begin
+        s_axis_tvalid_reg <= 0;
+    end
+end
+
 // output datapath logic
 reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
 reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
@@ -206,8 +236,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {M_ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -238,15 +268,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -273,6 +297,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_broadcast.v b/lib/axis/rtl/axis_broadcast.v
index 34fafd266..b5c41a39c 100644
--- a/lib/axis/rtl/axis_broadcast.v
+++ b/lib/axis/rtl/axis_broadcast.v
@@ -121,8 +121,8 @@ assign m_axis_tid    = ID_ENABLE   ? {M_COUNT{m_axis_tid_reg}}   : {M_COUNT*ID_W
 assign m_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
+// enable ready input next cycle if output is ready or if both output registers are empty
+wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -153,15 +153,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tready_reg <= 1'b0;
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        s_axis_tready_reg <= s_axis_tready_early;
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    s_axis_tready_reg <= s_axis_tready_early;
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_input_to_output) begin
@@ -188,6 +182,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= s_axis_tdest;
         temp_m_axis_tuser_reg <= s_axis_tuser;
     end
+
+    if (rst) begin
+        s_axis_tready_reg <= 1'b0;
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_cobs_decode.v b/lib/axis/rtl/axis_cobs_decode.v
index 84f504705..50c763b22 100644
--- a/lib/axis/rtl/axis_cobs_decode.v
+++ b/lib/axis/rtl/axis_cobs_decode.v
@@ -230,20 +230,21 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    count_reg <= count_next;
+    suppress_zero_reg <= suppress_zero_next;
+
+    temp_tdata_reg <= temp_tdata_next;
+    temp_tvalid_reg <= temp_tvalid_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         temp_tvalid_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        temp_tvalid_reg <= temp_tvalid_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
-
-    temp_tdata_reg <= temp_tdata_next;
-
-    count_reg <= count_next;
-    suppress_zero_reg <= suppress_zero_next;
 end
 
 // output datapath logic
@@ -267,8 +268,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -299,15 +300,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -325,6 +320,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_cobs_encode.v b/lib/axis/rtl/axis_cobs_encode.v
index c88e95cbe..4afdbacbc 100644
--- a/lib/axis/rtl/axis_cobs_encode.v
+++ b/lib/axis/rtl/axis_cobs_encode.v
@@ -411,17 +411,17 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        input_state_reg <= INPUT_STATE_IDLE;
-        output_state_reg <= OUTPUT_STATE_IDLE;
-    end else begin
-        input_state_reg <= input_state_next;
-        output_state_reg <= output_state_next;
-    end
+    input_state_reg <= input_state_next;
+    output_state_reg <= output_state_next;
 
     input_count_reg <= input_count_next;
     output_count_reg <= output_count_next;
     fail_frame_reg <= fail_frame_next;
+
+    if (rst) begin
+        input_state_reg <= INPUT_STATE_IDLE;
+        output_state_reg <= OUTPUT_STATE_IDLE;
+    end
 end
 
 // output datapath logic
@@ -445,8 +445,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -477,15 +477,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -503,6 +497,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_crosspoint.v b/lib/axis/rtl/axis_crosspoint.v
index 7fde4ab4e..9b84caa22 100644
--- a/lib/axis/rtl/axis_crosspoint.v
+++ b/lib/axis/rtl/axis_crosspoint.v
@@ -121,33 +121,31 @@ assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {M_COUNT*USER_WIDTH{1'b0
 integer i;
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
-    end else begin
-        s_axis_tvalid_reg <= s_axis_tvalid;
-        for (i = 0; i < M_COUNT; i = i + 1) begin
-            m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
-        end
-        select_reg <= select;
-    end
-
     s_axis_tdata_reg <= s_axis_tdata;
     s_axis_tkeep_reg <= s_axis_tkeep;
+    s_axis_tvalid_reg <= s_axis_tvalid;
     s_axis_tlast_reg <= s_axis_tlast;
     s_axis_tid_reg   <= s_axis_tid;
     s_axis_tdest_reg <= s_axis_tdest;
     s_axis_tuser_reg <= s_axis_tuser;
 
+    select_reg <= select;
+
     for (i = 0; i < M_COUNT; i = i + 1) begin
         m_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DATA_WIDTH +: DATA_WIDTH];
         m_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*KEEP_WIDTH +: KEEP_WIDTH];
+        m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tlast_reg[i]                          <= s_axis_tlast_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tid_reg[i*ID_WIDTH +: ID_WIDTH]       <= s_axis_tid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*ID_WIDTH +: ID_WIDTH];
         m_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DEST_WIDTH +: DEST_WIDTH];
         m_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*USER_WIDTH +: USER_WIDTH];
     end
+
+    if (rst) begin
+        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_demux.v b/lib/axis/rtl/axis_demux.v
index 7edd757f5..89e33fe1f 100644
--- a/lib/axis/rtl/axis_demux.v
+++ b/lib/axis/rtl/axis_demux.v
@@ -184,16 +184,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    select_reg <= select_next;
+    drop_reg <= drop_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         select_reg <= 2'd0;
         drop_reg <= 1'b0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        select_reg <= select_next;
-        drop_reg <= drop_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -227,8 +227,8 @@ assign m_axis_tid    = ID_ENABLE   ? {M_COUNT{m_axis_tid_reg}}   : {M_COUNT*ID_W
 assign m_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH_INT{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -259,15 +259,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -294,6 +288,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_frame_join.v b/lib/axis/rtl/axis_frame_join.v
index d25f5c6e6..f22b5a4d4 100644
--- a/lib/axis/rtl/axis_frame_join.v
+++ b/lib/axis/rtl/axis_frame_join.v
@@ -223,6 +223,18 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    frame_ptr_reg <= frame_ptr_next;
+
+    port_sel_reg <= port_sel_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
+    output_tuser_reg <= output_tuser_next;
+
+    busy_reg <= state_next != STATE_IDLE;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
@@ -230,18 +242,6 @@ always @(posedge clk) begin
         s_axis_tready_reg <= {S_COUNT{1'b0}};
         output_tuser_reg <= 1'b0;
         busy_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-
-        frame_ptr_reg <= frame_ptr_next;
-
-        port_sel_reg <= port_sel_next;
-
-        s_axis_tready_reg <= s_axis_tready_next;
-
-        output_tuser_reg <= output_tuser_next;
-
-        busy_reg <= state_next != STATE_IDLE;
     end
 end
 
@@ -266,8 +266,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -298,15 +298,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -324,6 +318,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_frame_length_adjust.v b/lib/axis/rtl/axis_frame_length_adjust.v
index 92fb2ec11..59fb0d9e2 100644
--- a/lib/axis/rtl/axis_frame_length_adjust.v
+++ b/lib/axis/rtl/axis_frame_length_adjust.v
@@ -543,8 +543,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -575,15 +575,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -610,6 +604,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_mux.v b/lib/axis/rtl/axis_mux.v
index ab021d3ef..bde07fd7c 100644
--- a/lib/axis/rtl/axis_mux.v
+++ b/lib/axis/rtl/axis_mux.v
@@ -152,14 +152,14 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    select_reg <= select_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         select_reg <= 0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 0;
-    end else begin
-        select_reg <= select_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -193,8 +193,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -225,15 +225,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -260,6 +254,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_rate_limit.v b/lib/axis/rtl/axis_rate_limit.v
index 24ec9546a..4b1a706ec 100644
--- a/lib/axis/rtl/axis_rate_limit.v
+++ b/lib/axis/rtl/axis_rate_limit.v
@@ -145,14 +145,14 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    acc_reg <= acc_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         acc_reg <= 24'd0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        acc_reg <= acc_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -186,8 +186,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -218,15 +218,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -253,6 +247,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_register.v b/lib/axis/rtl/axis_register.v
index 7e8f10931..6b98fb90f 100644
--- a/lib/axis/rtl/axis_register.v
+++ b/lib/axis/rtl/axis_register.v
@@ -125,8 +125,8 @@ if (REG_TYPE > 1) begin
     assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
     assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
+    // enable ready input next cycle if output is ready or if both output registers are empty
+    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
     always @* begin
         // transfer sink ready state to source
@@ -157,15 +157,9 @@ if (REG_TYPE > 1) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            s_axis_tready_reg <= 1'b0;
-            m_axis_tvalid_reg <= 1'b0;
-            temp_m_axis_tvalid_reg <= 1'b0;
-        end else begin
-            s_axis_tready_reg <= s_axis_tready_early;
-            m_axis_tvalid_reg <= m_axis_tvalid_next;
-            temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-        end
+        s_axis_tready_reg <= s_axis_tready_early;
+        m_axis_tvalid_reg <= m_axis_tvalid_next;
+        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
         // datapath
         if (store_axis_input_to_output) begin
@@ -192,6 +186,12 @@ if (REG_TYPE > 1) begin
             temp_m_axis_tdest_reg <= s_axis_tdest;
             temp_m_axis_tuser_reg <= s_axis_tuser;
         end
+
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+            temp_m_axis_tvalid_reg <= 1'b0;
+        end
     end
 
 end else if (REG_TYPE == 1) begin
@@ -239,13 +239,8 @@ end else if (REG_TYPE == 1) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            s_axis_tready_reg <= 1'b0;
-            m_axis_tvalid_reg <= 1'b0;
-        end else begin
-            s_axis_tready_reg <= s_axis_tready_early;
-            m_axis_tvalid_reg <= m_axis_tvalid_next;
-        end
+        s_axis_tready_reg <= s_axis_tready_early;
+        m_axis_tvalid_reg <= m_axis_tvalid_next;
 
         // datapath
         if (store_axis_input_to_output) begin
@@ -256,6 +251,11 @@ end else if (REG_TYPE == 1) begin
             m_axis_tdest_reg <= s_axis_tdest;
             m_axis_tuser_reg <= s_axis_tuser;
         end
+
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+        end
     end
 
 end else begin
diff --git a/lib/axis/rtl/axis_srl_fifo.v b/lib/axis/rtl/axis_srl_fifo.v
index 7eabf8f45..5907dd448 100644
--- a/lib/axis/rtl/axis_srl_fifo.v
+++ b/lib/axis/rtl/axis_srl_fifo.v
@@ -169,29 +169,29 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        ptr_reg <= 0;
-        full_reg <= 1'b0;
-        empty_reg <= 1'b1;
+    if (inc) begin
+        ptr_reg <= ptr_reg + 1;
+    end else if (dec) begin
+        ptr_reg <= ptr_reg - 1;
     end else begin
-        if (inc) begin
-            ptr_reg <= ptr_reg + 1;
-        end else if (dec) begin
-            ptr_reg <= ptr_reg - 1;
-        end else begin
-            ptr_reg <= ptr_reg;
-        end
-
-        full_reg <= full_next;
-        empty_reg <= empty_next;
+        ptr_reg <= ptr_reg;
     end
 
+    full_reg <= full_next;
+    empty_reg <= empty_next;
+
     if (shift) begin
         data_reg[0] <= s_axis;
         for (i = 0; i < DEPTH-1; i = i + 1) begin
             data_reg[i+1] <= data_reg[i];
         end
     end
+
+    if (rst) begin
+        ptr_reg <= 0;
+        full_reg <= 1'b0;
+        empty_reg <= 1'b1;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_srl_register.v b/lib/axis/rtl/axis_srl_register.v
index f0e9efee2..bfe945a5c 100644
--- a/lib/axis/rtl/axis_srl_register.v
+++ b/lib/axis/rtl/axis_srl_register.v
@@ -129,27 +129,27 @@ initial begin
 end
 
 always @(posedge clk) begin
+    // transfer empty to full
+    full_reg <= !m_axis_tready && m_axis_tvalid;
+
+    // transfer in if not full
+    if (s_axis_tready) begin
+        data_reg[0] <= s_axis;
+        valid_reg[0] <= s_axis_tvalid;
+        for (i = 0; i < 1; i = i + 1) begin
+            data_reg[i+1] <= data_reg[i];
+            valid_reg[i+1] <= valid_reg[i];
+        end
+        ptr_reg <= valid_reg[0];
+    end
+
+    if (m_axis_tready) begin
+        ptr_reg <= 0;
+    end
+
     if (rst) begin
         ptr_reg <= 0;
         full_reg <= 0;
-    end else begin
-        // transfer empty to full
-        full_reg <= !m_axis_tready && m_axis_tvalid;
-
-        // transfer in if not full
-        if (s_axis_tready) begin
-            data_reg[0] <= s_axis;
-            valid_reg[0] <= s_axis_tvalid;
-            for (i = 0; i < 1; i = i + 1) begin
-                data_reg[i+1] <= data_reg[i];
-                valid_reg[i+1] <= valid_reg[i];
-            end
-            ptr_reg <= valid_reg[0];
-        end
-
-        if (m_axis_tready) begin
-            ptr_reg <= 0;
-        end
     end
 end
 
diff --git a/lib/axis/rtl/axis_stat_counter.v b/lib/axis/rtl/axis_stat_counter.v
index cc0476083..01fefe6cc 100644
--- a/lib/axis/rtl/axis_stat_counter.v
+++ b/lib/axis/rtl/axis_stat_counter.v
@@ -258,6 +258,21 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+    tick_count_reg <= tick_count_next;
+    byte_count_reg <= byte_count_next;
+    frame_count_reg <= frame_count_next;
+    frame_reg <= frame_next;
+    frame_ptr_reg <= frame_ptr_next;
+
+    busy_reg <= state_next != STATE_IDLE;
+
+    if (store_output) begin
+        tick_count_output_reg <= tick_count_reg;
+        byte_count_output_reg <= byte_count_reg;
+        frame_count_output_reg <= frame_count_reg;
+    end
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         tick_count_reg <= 0;
@@ -266,21 +281,6 @@ always @(posedge clk) begin
         frame_reg <= 1'b0;
         frame_ptr_reg <= 0;
         busy_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        tick_count_reg <= tick_count_next;
-        byte_count_reg <= byte_count_next;
-        frame_count_reg <= frame_count_next;
-        frame_reg <= frame_next;
-        frame_ptr_reg <= frame_ptr_next;
-
-        busy_reg <= state_next != STATE_IDLE;
-    end
-
-    if (store_output) begin
-        tick_count_output_reg <= tick_count_reg;
-        byte_count_output_reg <= byte_count_reg;
-        frame_count_output_reg <= frame_count_reg;
     end
 end
 
@@ -305,8 +305,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -337,15 +337,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -363,6 +357,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/lib/axis/rtl/axis_switch.v b/lib/axis/rtl/axis_switch.v
index d791294bb..fae45fb19 100644
--- a/lib/axis/rtl/axis_switch.v
+++ b/lib/axis/rtl/axis_switch.v
@@ -258,14 +258,13 @@ generate
         end
 
         always @(posedge clk) begin
-            if (rst) begin
-                select_valid_reg <= 1'b0;
-            end else begin
-                select_valid_reg <= select_valid_next;
-            end
-
             select_reg <= select_next;
             drop_reg <= drop_next;
+            select_valid_reg <= select_valid_next;
+
+            if (rst) begin
+                select_valid_reg <= 1'b0;
+            end
         end
 
         // forwarding
diff --git a/lib/axis/rtl/axis_tap.v b/lib/axis/rtl/axis_tap.v
index 13966adcb..05f4df522 100644
--- a/lib/axis/rtl/axis_tap.v
+++ b/lib/axis/rtl/axis_tap.v
@@ -213,19 +213,19 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        state_reg <= STATE_IDLE;
-        frame_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        frame_reg <= frame_next;
-    end
+    state_reg <= state_next;
+    frame_reg <= frame_next;
 
     if (store_last_word) begin
         last_word_id_reg   <= tap_axis_tid;
         last_word_dest_reg <= tap_axis_tdest;
         last_word_user_reg <= tap_axis_tuser;
     end
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        frame_reg <= 1'b0;
+    end
 end
 
 // output datapath logic
@@ -258,8 +258,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
@@ -290,15 +290,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -325,6 +319,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule