diff --git a/fpga/lib/eth/README.md b/fpga/lib/eth/README.md index 4411126af..6f589b603 100644 --- a/fpga/lib/eth/README.md +++ b/fpga/lib/eth/README.md @@ -30,6 +30,26 @@ module (ptp_clock_cdc) for transferring PTP time across clock domains, and a configurable PTP period output module for precisely generating arbitrary frequencies from PTP time. +Example designs implementing a simple UDP echo server are included for the +following boards: + +* Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P) +* Digilent Arty A7 (Xilinx Artix 7 XC7A35T) +* Digilent Atlys (Xilinx Spartan 6 XC6SLX45) +* Intel Cyclone 10 LP (Intel Cyclone 10 10CL025YU256I7G) +* Terasic DE2-115 (Intel Cyclone IV E EP4CE115F29C7) +* Terasic DE5-Net (Intel Stratix V 5SGXEA7N2F45C2) +* Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035) +* Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P) +* HiTech Global HTG-V6HXT-100GIG-565 (Xilinx Virtex 6 XC6VHX565T) +* Xilinx KC705 (Xilinx Kintex 7 XC7K325T) +* Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T) +* NetFPGA SUME (Xilinx Virtex 7 XC7V690T) +* Digilent Nexys Video (Xilinx Artix 7 XC7XC7A200T) +* Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095) +* Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P) +* Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P) + ## Documentation ### arp module diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index 0ca360ff6..114a80deb 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -54,7 +54,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES += ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..5a31d6c75 --- /dev/null +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,21 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X0Y19 X0Y18 X0Y17 X0Y16 X0Y15 X0Y14 X0Y13 X0Y12} \ + CONFIG.TX_MASTER_CHANNEL {X0Y16} \ + CONFIG.RX_MASTER_CHANNEL {X0Y16} \ + CONFIG.TX_LINE_RATE {10.3125} \ + CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {10.3125} \ + CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 X0Y15 clk0 X0Y14 clk0 X0Y13 clk0 X0Y12 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 X0Y15 clk0 X0Y14 clk0 X0Y13 clk0 X0Y12 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index ef03a5467..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1407 +0,0 @@ - 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false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexuplus - - - xcvu3p - ffvc1517 - VERILOG - - MIXED - -2 - - I - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 0ca360ff6..114a80deb 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -54,7 +54,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES += ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..ae6b316c4 --- /dev/null +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,21 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X0Y19 X0Y18 X0Y17 X0Y16 X0Y15 X0Y14 X0Y13 X0Y12} \ + CONFIG.TX_MASTER_CHANNEL {X0Y16} \ + CONFIG.RX_MASTER_CHANNEL {X0Y16} \ + CONFIG.TX_LINE_RATE {25.78125} \ + CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {25.78125} \ + CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 X0Y15 clk0 X0Y14 clk0 X0Y13 clk0 X0Y12 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X0Y19 clk0 X0Y18 clk0 X0Y17 clk0 X0Y16 clk0 X0Y15 clk0 X0Y14 clk0 X0Y13 clk0 X0Y12 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index 9862aadf8..000000000 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1411 +0,0 @@ - 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false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexuplus - - - xcvu3p - ffvc1517 - VERILOG - - MIXED - -2 - - I - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 5ed2b44f7..5f48f4c71 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -102,9 +102,9 @@ wire clk_125mhz_mmcm_out; wire clk_125mhz_int; wire rst_125mhz_int; -// Internal 156.25 MHz clock -wire clk_156mhz_int; -wire rst_156mhz_int; +// Internal 390.625 MHz clock +wire clk_390mhz_int; +wire rst_390mhz_int; wire mmcm_rst = 1'b0; wire mmcm_locked; @@ -341,7 +341,7 @@ BUFG_GT bufg_gt_tx_usrclk_inst ( .O (gt_txusrclk) ); -assign clk_156mhz_int = gt_txusrclk; +assign clk_390mhz_int = gt_txusrclk; always @(posedge gt_txusrclk, posedge gt_tx_reset) begin if (gt_tx_reset) begin @@ -382,10 +382,10 @@ endgenerate sync_reset #( .N(4) ) -sync_reset_156mhz_inst ( - .clk(clk_156mhz_int), +sync_reset_390mhz_inst ( + .clk(clk_390mhz_int), .rst(~gt_reset_tx_done), - .out(rst_156mhz_int) + .out(rst_390mhz_int) ); wire [5:0] qsfp_0_gt_txheader_0; @@ -509,8 +509,8 @@ qsfp_gty_inst ( .txprgdivresetdone_out(gt_txprgdivresetdone) ); -assign qsfp_0_tx_clk_0_int = clk_156mhz_int; -assign qsfp_0_tx_rst_0_int = rst_156mhz_int; +assign qsfp_0_tx_clk_0_int = clk_390mhz_int; +assign qsfp_0_tx_rst_0_int = rst_390mhz_int; assign qsfp_0_rx_clk_0_int = gt_rxusrclk[4]; @@ -547,8 +547,8 @@ qsfp_0_phy_0_inst ( .rx_high_ber() ); -assign qsfp_0_tx_clk_1_int = clk_156mhz_int; -assign qsfp_0_tx_rst_1_int = rst_156mhz_int; +assign qsfp_0_tx_clk_1_int = clk_390mhz_int; +assign qsfp_0_tx_rst_1_int = rst_390mhz_int; assign qsfp_0_rx_clk_1_int = gt_rxusrclk[5]; @@ -585,8 +585,8 @@ qsfp_0_phy_1_inst ( .rx_high_ber() ); -assign qsfp_0_tx_clk_2_int = clk_156mhz_int; -assign qsfp_0_tx_rst_2_int = rst_156mhz_int; +assign qsfp_0_tx_clk_2_int = clk_390mhz_int; +assign qsfp_0_tx_rst_2_int = rst_390mhz_int; assign qsfp_0_rx_clk_2_int = gt_rxusrclk[6]; @@ -623,8 +623,8 @@ qsfp_0_phy_2_inst ( .rx_high_ber() ); -assign qsfp_0_tx_clk_3_int = clk_156mhz_int; -assign qsfp_0_tx_rst_3_int = rst_156mhz_int; +assign qsfp_0_tx_clk_3_int = clk_390mhz_int; +assign qsfp_0_tx_rst_3_int = rst_390mhz_int; assign qsfp_0_rx_clk_3_int = gt_rxusrclk[7]; @@ -661,8 +661,8 @@ qsfp_0_phy_3_inst ( .rx_high_ber() ); -assign qsfp_1_tx_clk_0_int = clk_156mhz_int; -assign qsfp_1_tx_rst_0_int = rst_156mhz_int; +assign qsfp_1_tx_clk_0_int = clk_390mhz_int; +assign qsfp_1_tx_rst_0_int = rst_390mhz_int; assign qsfp_1_rx_clk_0_int = gt_rxusrclk[0]; @@ -699,8 +699,8 @@ qsfp_1_phy_0_inst ( .rx_high_ber() ); -assign qsfp_1_tx_clk_1_int = clk_156mhz_int; -assign qsfp_1_tx_rst_1_int = rst_156mhz_int; +assign qsfp_1_tx_clk_1_int = clk_390mhz_int; +assign qsfp_1_tx_rst_1_int = rst_390mhz_int; assign qsfp_1_rx_clk_1_int = gt_rxusrclk[1]; @@ -737,8 +737,8 @@ qsfp_1_phy_1_inst ( .rx_high_ber() ); -assign qsfp_1_tx_clk_2_int = clk_156mhz_int; -assign qsfp_1_tx_rst_2_int = rst_156mhz_int; +assign qsfp_1_tx_clk_2_int = clk_390mhz_int; +assign qsfp_1_tx_rst_2_int = rst_390mhz_int; assign qsfp_1_rx_clk_2_int = gt_rxusrclk[2]; @@ -775,8 +775,8 @@ qsfp_1_phy_2_inst ( .rx_high_ber() ); -assign qsfp_1_tx_clk_3_int = clk_156mhz_int; -assign qsfp_1_tx_rst_3_int = rst_156mhz_int; +assign qsfp_1_tx_clk_3_int = clk_390mhz_int; +assign qsfp_1_tx_rst_3_int = rst_390mhz_int; assign qsfp_1_rx_clk_3_int = gt_rxusrclk[3]; @@ -819,11 +819,11 @@ assign front_led = {1'b0, qsfp_0_rx_block_lock_0}; fpga_core core_inst ( /* - * Clock: 156.25 MHz + * Clock: 390.625 MHz * Synchronous reset */ - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), + .clk(clk_390mhz_int), + .rst(rst_390mhz_int), /* * GPIO */ diff --git a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index afda622b0..e4aa46b22 100644 --- a/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/lib/eth/example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -35,7 +35,7 @@ module fpga_core # ) ( /* - * Clock: 156.25MHz + * Clock: 390.625 MHz * Synchronous reset */ input wire clk, diff --git a/fpga/lib/eth/example/Arty/fpga/common/vivado.mk b/fpga/lib/eth/example/Arty/fpga/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/Arty/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/Arty/fpga/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/C10LP/fpga/Makefile b/fpga/lib/eth/example/C10LP/fpga/Makefile new file mode 100644 index 000000000..8d766f026 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/Makefile @@ -0,0 +1,25 @@ +# Targets +TARGETS:= + +# Subdirectories +SUBDIRS = fpga +SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) + +# Rules +.PHONY: all +all: $(SUBDIRS) $(TARGETS) + +.PHONY: $(SUBDIRS) +$(SUBDIRS): + cd $@ && $(MAKE) + +.PHONY: $(SUBDIRS_CLEAN) +$(SUBDIRS_CLEAN): + cd $(@:.clean=) && $(MAKE) clean + +.PHONY: clean +clean: $(SUBDIRS_CLEAN) + -rm -rf $(TARGETS) + +program: + #program commands diff --git a/fpga/lib/eth/example/C10LP/fpga/README.md b/fpga/lib/eth/example/C10LP/fpga/README.md new file mode 100644 index 000000000..70110cf3d --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/README.md @@ -0,0 +1,25 @@ +# Verilog Ethernet Cyclone 10 LP Example Design + +## Introduction + +This example design targets the Intel Cyclone 10 LP FPGA development board. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and +will echo back any packets received. The design will also respond correctly +to ARP requests. + +FPGA: 5SGXEA7N2F45C2 +PHY: Intel XWAY PHY11G PEF7071 + +## How to build + +Run make to build. Ensure that the Altera Quartus toolchain components are +in PATH. + +## How to test + +Run make program to program the board with the Altera software. Then run +netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any +text entered into netcat will be echoed back after pressing enter. + + diff --git a/fpga/lib/eth/example/C10LP/fpga/common/quartus.mk b/fpga/lib/eth/example/C10LP/fpga/common/quartus.mk new file mode 100644 index 000000000..e06d66313 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/common/quartus.mk @@ -0,0 +1,141 @@ +################################################################### +# +# Altera FPGA Makefile +# +# Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. Stratix V) +# FPGA_DEVICE - FPGA device (e.g. 5SGXEA7N2F45C2) +# SYN_FILES - space-separated list of source files +# QSF_FILES - space-separated list of settings files +# SDC_FILES - space-separated list of timing constraint files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = "Stratix V" +# FPGA_DEVICE = 5SGXEA7N2F45C2 +# SYN_FILES = rtl/fpga.v rtl/clocks.v +# QSF_FILES = fpga.qsf +# SDC_FILES = fpga.sdc +# include ../common/altera.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# output files to hang on to +.PRECIOUS: %.sof %.map.rpt %.fit.rpt %.asm.rpt %.sta.rpt + +# any project specific settings +-include ../config.mk + +SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) + +ifdef QSF_FILES + QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) +else + QSF_FILES_REL = ../$(FPGA_TOP).qsf +endif + +SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) + +ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and database +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).sof + +clean: + rm -rf *.rpt *.summary *.smsg *.chg smart.log *.htm *.eqn *.pin *.sof *.pof *.qsf *.qpf *.jdi *.sld *.txt db incremental_db reconfig_mif + +map: smart.log $(PROJECT).map.rpt +fit: smart.log $(PROJECT).fit.rpt +asm: smart.log $(PROJECT).asm.rpt +sta: smart.log $(PROJECT).sta.rpt +smart: smart.log + +################################################################### +# Executable Configuration +################################################################### + +MAP_ARGS = --family=$(FPGA_FAMILY) +FIT_ARGS = --part=$(FPGA_DEVICE) +ASM_ARGS = +STA_ARGS = + +################################################################### +# Target implementations +################################################################### + +STAMP = echo done > + +%.map.rpt: map.chg $(SYN_FILES_REL) + quartus_map $(MAP_ARGS) $(FPGA_TOP) + +%.fit.rpt: fit.chg %.map.rpt + quartus_fit $(FIT_ARGS) $(FPGA_TOP) + +%.sta.rpt: sta.chg %.fit.rpt + quartus_sta $(STA_ARGS) $(FPGA_TOP) + +%.asm.rpt: asm.chg %.sta.rpt + quartus_asm $(ASM_ARGS) $(FPGA_TOP) + mkdir -p rev + EXT=sof; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do let COUNT=COUNT+1; done; \ + cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; + +%.sof: smart.log %.asm.rpt + + +smart.log: $(ASSIGNMENT_FILES) + quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log + +################################################################### +# Project initialization +################################################################### + +$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(SYN_FILES_REL) + rm -f $(FPGA_TOP).qsf + quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) + echo >> $(FPGA_TOP).qsf + echo >> $(FPGA_TOP).qsf + echo "# Source files" >> $(FPGA_TOP).qsf + for x in $(SYN_FILES_REL); do \ + case $${x##*.} in \ + v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ + *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + esac; \ + done + echo >> $(FPGA_TOP).qsf + echo "# SDC files" >> $(FPGA_TOP).qsf + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done + for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + +map.chg: + $(STAMP) map.chg +fit.chg: + $(STAMP) fit.chg +sta.chg: + $(STAMP) sta.chg +asm.chg: + $(STAMP) asm.chg + + diff --git a/fpga/lib/eth/example/C10LP/fpga/fpga.qsf b/fpga/lib/eth/example/C10LP/fpga/fpga.qsf new file mode 100644 index 000000000..869f8bfbd --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/fpga.qsf @@ -0,0 +1,228 @@ +# I/O constraints for the Intel Cyclone 10 LP FPGA development board +# part: 10CL025YU256I7G + +set_global_assignment -name FAMILY "Cyclone 10 LP" +set_global_assignment -name DEVICE 10CL025YU256I7G +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Clock and reset +set_location_assignment PIN_J15 -to c10_resetn +set_location_assignment PIN_E1 -to c10_clk50m +set_location_assignment PIN_E16 -to c10_clk_adj +set_location_assignment PIN_B9 -to c10_usb_clk +set_location_assignment PIN_T8 -to enet_clk_125m +set_location_assignment PIN_M15 -to hbus_clk_50m + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to c10_resetn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to c10_clk50m +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to c10_clk_adj +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to c10_usb_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_clk_125m +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hbus_clk_50m + +# Switches, buttons, LEDs +set_location_assignment PIN_M16 -to user_dip[0] +set_location_assignment PIN_A8 -to user_dip[1] +set_location_assignment PIN_A9 -to user_dip[2] +set_location_assignment PIN_E15 -to user_pb[0] +set_location_assignment PIN_F14 -to user_pb[1] +set_location_assignment PIN_C11 -to user_pb[2] +set_location_assignment PIN_D9 -to user_pb[3] +set_location_assignment PIN_L14 -to user_led[0] +set_location_assignment PIN_K15 -to user_led[1] +set_location_assignment PIN_J14 -to user_led[2] +set_location_assignment PIN_J13 -to user_led[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_dip +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_led +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to user_pb + +# Arduino interface +set_location_assignment PIN_B1 -to arduino_io[0] +set_location_assignment PIN_C2 -to arduino_io[1] +set_location_assignment PIN_F3 -to arduino_io[2] +set_location_assignment PIN_D1 -to arduino_io[3] +set_location_assignment PIN_G2 -to arduino_io[4] +set_location_assignment PIN_G1 -to arduino_io[5] +set_location_assignment PIN_J2 -to arduino_io[6] +set_location_assignment PIN_J1 -to arduino_io[7] +set_location_assignment PIN_K2 -to arduino_io[8] +set_location_assignment PIN_K5 -to arduino_io[9] +set_location_assignment PIN_L4 -to arduino_io[10] +set_location_assignment PIN_K1 -to arduino_io[11] +set_location_assignment PIN_L2 -to arduino_io[12] +set_location_assignment PIN_L1 -to arduino_io[13] +set_location_assignment PIN_L3 -to arduino_rstn +set_location_assignment PIN_C8 -to arduino_adc_sda +set_location_assignment PIN_D8 -to arduino_adc_scl +set_location_assignment PIN_N1 -to arduino_scl +set_location_assignment PIN_N2 -to arduino_sda + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_io +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_rstn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_adc_sda +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_adc_scl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_scl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_sda + +# PMOD +set_location_assignment PIN_D16 -to pmod_d[0] +set_location_assignment PIN_F13 -to pmod_d[1] +set_location_assignment PIN_D15 -to pmod_d[2] +set_location_assignment PIN_F16 -to pmod_d[3] +set_location_assignment PIN_C16 -to pmod_d[4] +set_location_assignment PIN_F15 -to pmod_d[5] +set_location_assignment PIN_C15 -to pmod_d[6] +set_location_assignment PIN_B16 -to pmod_d[7] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pmod_d + +# GPIO +set_location_assignment PIN_L13 -to gpio[0] +set_location_assignment PIN_L16 -to gpio[1] +set_location_assignment PIN_L15 -to gpio[2] +set_location_assignment PIN_K16 -to gpio[3] +set_location_assignment PIN_P16 -to gpio[4] +set_location_assignment PIN_R16 -to gpio[5] +set_location_assignment PIN_N16 -to gpio[6] +set_location_assignment PIN_N15 -to gpio[7] +set_location_assignment PIN_N14 -to gpio[8] +set_location_assignment PIN_P15 -to gpio[9] +set_location_assignment PIN_N8 -to gpio[10] +set_location_assignment PIN_P8 -to gpio[11] +set_location_assignment PIN_M8 -to gpio[12] +set_location_assignment PIN_L8 -to gpio[13] +set_location_assignment PIN_R7 -to gpio[14] +set_location_assignment PIN_T7 -to gpio[15] +set_location_assignment PIN_L7 -to gpio[16] +set_location_assignment PIN_M7 -to gpio[17] +set_location_assignment PIN_R6 -to gpio[18] +set_location_assignment PIN_T6 -to gpio[19] +set_location_assignment PIN_T2 -to gpio[20] +set_location_assignment PIN_M6 -to gpio[21] +set_location_assignment PIN_R5 -to gpio[22] +set_location_assignment PIN_T5 -to gpio[23] +set_location_assignment PIN_N5 -to gpio[24] +set_location_assignment PIN_N6 -to gpio[25] +set_location_assignment PIN_R4 -to gpio[26] +set_location_assignment PIN_T4 -to gpio[27] +set_location_assignment PIN_N3 -to gpio[28] +set_location_assignment PIN_P3 -to gpio[29] +set_location_assignment PIN_R3 -to gpio[30] +set_location_assignment PIN_T3 -to gpio[31] +set_location_assignment PIN_P6 -to gpio[32] +set_location_assignment PIN_P2 -to gpio[33] +set_location_assignment PIN_P1 -to gpio[34] +set_location_assignment PIN_R1 -to gpio[35] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio + +# Ethernet +set_location_assignment PIN_B8 -to enet_rx_clk +set_location_assignment PIN_A5 -to enet_rx_dv +set_location_assignment PIN_A7 -to enet_rx_d[0] +set_location_assignment PIN_B7 -to enet_rx_d[1] +set_location_assignment PIN_A6 -to enet_rx_d[2] +set_location_assignment PIN_B6 -to enet_rx_d[3] +set_location_assignment PIN_D3 -to enet_tx_clk +set_location_assignment PIN_D6 -to enet_tx_en +set_location_assignment PIN_E6 -to enet_tx_d[0] +set_location_assignment PIN_A3 -to enet_tx_d[1] +set_location_assignment PIN_B3 -to enet_tx_d[2] +set_location_assignment PIN_A2 -to enet_tx_d[3] +set_location_assignment PIN_C6 -to enet_resetn +set_location_assignment PIN_B4 -to enet_mdc +set_location_assignment PIN_A4 -to enet_mdio +set_location_assignment PIN_B5 -to enet_int + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_rx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_rx_dv +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_rx_d +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_tx_clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_tx_en +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_tx_d +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_resetn +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_mdc +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_mdio +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to enet_int + +# HyperBUS (HyperRAM) +set_location_assignment PIN_P11 -to hbus_intn +set_location_assignment PIN_T15 -to hbus_rston +set_location_assignment PIN_T12 -to hbus_dq[0] +set_location_assignment PIN_T13 -to hbus_dq[1] +set_location_assignment PIN_T11 -to hbus_dq[2] +set_location_assignment PIN_R10 -to hbus_dq[3] +set_location_assignment PIN_T10 -to hbus_dq[4] +set_location_assignment PIN_R11 -to hbus_dq[5] +set_location_assignment PIN_R12 -to hbus_dq[6] +set_location_assignment PIN_R13 -to hbus_dq[7] +set_location_assignment PIN_P9 -to hbus_cs2n +set_location_assignment PIN_N12 -to hbus_cs1n +set_location_assignment PIN_N9 -to hbus_rstn +set_location_assignment PIN_T14 -to hbus_rwds +set_location_assignment PIN_P14 -to hbus_clk0p +set_location_assignment PIN_R14 -to hbus_clk0n + +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_intn +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_rston +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_dq +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_cs2n +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_cs1n +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_rstn +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_rwds +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_clk0p +set_instance_assignment -name IO_STANDARD "1.8 V" -to hbus_clk0n + +# QSPI +set_location_assignment PIN_C1 -to qspi_sdo +set_location_assignment PIN_D2 -to qspi_sce +set_location_assignment PIN_H1 -to qspi_dclk +set_location_assignment PIN_H2 -to qspi_data0 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_sdo +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_sce +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_dclk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_data0 + +# MAX10 +set_location_assignment PIN_E8 -to c10_m10_io[0] +set_location_assignment PIN_E7 -to c10_m10_io[1] +set_location_assignment PIN_F8 -to c10_m10_io[2] +set_location_assignment PIN_C3 -to c10_m10_io[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to c10_m10_io + +# MAX10 USB +set_location_assignment PIN_A15 -to usb_data[0] +set_location_assignment PIN_B14 -to usb_data[1] +set_location_assignment PIN_A14 -to usb_data[2] +set_location_assignment PIN_B13 -to usb_data[3] +set_location_assignment PIN_A13 -to usb_data[4] +set_location_assignment PIN_B12 -to usb_data[5] +set_location_assignment PIN_A12 -to usb_data[6] +set_location_assignment PIN_B10 -to usb_data[7] +set_location_assignment PIN_A10 -to usb_addr[0] +set_location_assignment PIN_A11 -to usb_addr[1] +set_location_assignment PIN_D12 -to usb_full +set_location_assignment PIN_D14 -to usb_empty +set_location_assignment PIN_C14 -to usb_scl +set_location_assignment PIN_E9 -to usb_sda +set_location_assignment PIN_F9 -to usb_oe_n +set_location_assignment PIN_D11 -to usb_rd_n +set_location_assignment PIN_B11 -to usb_wr_n +set_location_assignment PIN_C9 -to usb_reset_n + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_data +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_addr +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_full +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_empty +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_scl +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_sda +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_oe_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_rd_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_wr_n +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb_reset_n diff --git a/fpga/lib/eth/example/C10LP/fpga/fpga.sdc b/fpga/lib/eth/example/C10LP/fpga/fpga.sdc new file mode 100644 index 000000000..c920e83e7 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/fpga.sdc @@ -0,0 +1,61 @@ + +create_clock -period 20.00 -name {c10_clk50m} [get_ports {c10_clk50m}] +create_clock -period 10.00 -name {c10_clk_adj} [get_ports {c10_clk_adj}] +create_clock -period 8.000 -name {c10_usb_clk} [get_ports {c10_usb_clk}] +create_clock -period 8.000 -name {enet_clk_125m} [get_ports {enet_clk_125m}] +create_clock -period 20.000 -name {hbus_clk_50m} [get_ports {hbus_clk_50m}] + +set_clock_groups -asynchronous -group [get_clocks {c10_clk50m}] +set_clock_groups -asynchronous -group [get_clocks {c10_clk_adj}] +set_clock_groups -asynchronous -group [get_clocks {c10_usb_clk}] +set_clock_groups -asynchronous -group [get_clocks {enet_clk_125m}] +set_clock_groups -asynchronous -group [get_clocks {hbus_clk_50m}] + +create_clock -period "40.000 ns" -name {altera_reserved_tck} {altera_reserved_tck} +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] + +#JTAG Signal Constraints +#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook) +set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi] +set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms] +set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo] + +# c10_resetn +set_input_delay -clock [get_clocks c10_clk50m] 10 [get_ports {c10_resetn}] + +# Ethernet MDIO interface +set_output_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdc}] +set_input_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdio}] +set_output_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdio}] + +set_false_path -from [get_ports c10_resetn] -to * +set_false_path -from [get_ports {user_pb[*]}] -to * +set_false_path -from [get_ports {user_dip[*]}] -to * +set_false_path -from * -to [get_ports {user_led[*]}] + +set_false_path -from [get_ports enet_intn] -to * +set_false_path -from * -to [get_ports enet_resetn] + + +derive_pll_clocks +derive_clock_uncertainty + + +source ../lib/eth/syn/eth_mac_1g_rgmii.sdc +source ../lib/eth/syn/rgmii_phy_if.sdc +source ../lib/eth/syn/rgmii_io.sdc +source ../lib/eth/lib/axis/syn/sync_reset.sdc +source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc + +# clocking infrastructure +constrain_sync_reset_inst "sync_reset_inst" + +# RGMII MAC +constrain_eth_mac_1g_rgmii_inst "core_inst|eth_mac_inst|eth_mac_1g_rgmii_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|rx_fifo|fifo_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|tx_fifo|fifo_inst" + +# RGMII interface +constrain_rgmii_input_pins "enet" "enet_rx_clk" "enet_rx_dv enet_rx_d*" +constrain_rgmii_output_pins "enet" "altpll_component|auto_generated|pll1|clk[0]" "enet_tx_clk" "enet_tx_en enet_tx_d*" + diff --git a/fpga/lib/eth/example/C10LP/fpga/fpga/Makefile b/fpga/lib/eth/example/C10LP/fpga/fpga/Makefile new file mode 100644 index 000000000..abfc85b9c --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/fpga/Makefile @@ -0,0 +1,58 @@ + +# FPGA settings +FPGA_TOP = fpga +FPGA_FAMILY = "Cyclone 10 LP" +FPGA_DEVICE = 10CL025YU256I7G + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += lib/eth/rtl/iddr.v +SYN_FILES += lib/eth/rtl/oddr.v +SYN_FILES += lib/eth/rtl/ssio_ddr_in.v +SYN_FILES += lib/eth/rtl/ssio_ddr_out.v +SYN_FILES += lib/eth/rtl/rgmii_phy_if.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v +SYN_FILES += lib/eth/rtl/eth_mac_1g.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen.v +SYN_FILES += lib/eth/rtl/udp.v +SYN_FILES += lib/eth/rtl/udp_ip_rx.v +SYN_FILES += lib/eth/rtl/udp_ip_tx.v +SYN_FILES += lib/eth/rtl/ip_complete.v +SYN_FILES += lib/eth/rtl/ip.v +SYN_FILES += lib/eth/rtl/ip_eth_rx.v +SYN_FILES += lib/eth/rtl/ip_eth_tx.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/ip_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/rtl/eth_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# QSF files +QSF_FILES = fpga.qsf + +# SDC files +SDC_FILES = fpga.sdc + +include ../common/quartus.mk + +program: fpga + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof" diff --git a/fpga/lib/eth/example/C10LP/fpga/lib/eth b/fpga/lib/eth/example/C10LP/fpga/lib/eth new file mode 120000 index 000000000..11a54ed36 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/lib/eth @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/rtl/debounce_switch.v b/fpga/lib/eth/example/C10LP/fpga/rtl/debounce_switch.v new file mode 100644 index 000000000..bb631cc35 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/rtl/debounce_switch.v @@ -0,0 +1,89 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes switch and button inputs with a slow sampled shift register + */ +module debounce_switch #( + parameter WIDTH=1, // width of the input and output signals + parameter N=3, // length of shift register + parameter RATE=125000 // clock division factor +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [23:0] cnt_reg = 24'd0; + +reg [N-1:0] debounce_reg[WIDTH-1:0]; + +reg [WIDTH-1:0] state; + +/* + * The synchronized output is the state register + */ +assign out = state; + +integer k; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cnt_reg <= 0; + state <= 0; + + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= 0; + end + end else begin + if (cnt_reg < RATE) begin + cnt_reg <= cnt_reg + 24'd1; + end else begin + cnt_reg <= 24'd0; + end + + if (cnt_reg == 24'd0) begin + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; + end + end + + for (k = 0; k < WIDTH; k = k + 1) begin + if (|debounce_reg[k] == 0) begin + state[k] <= 0; + end else if (&debounce_reg[k] == 1) begin + state[k] <= 1; + end else begin + state[k] <= state[k]; + end + end + end +end + +endmodule diff --git a/fpga/lib/eth/example/C10LP/fpga/rtl/fpga.v b/fpga/lib/eth/example/C10LP/fpga/rtl/fpga.v new file mode 100644 index 000000000..bc1d33760 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/rtl/fpga.v @@ -0,0 +1,230 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 125MHz + * Reset: Push button, active low + */ + input wire enet_clk_125m, + input wire c10_resetn, + + /* + * GPIO + */ + input wire [3:0] user_pb, + input wire [2:0] user_dip, + output wire [3:0] user_led, + + /* + * Ethernet: 1000BASE-T RGMII + */ + input wire enet_rx_clk, + input wire [3:0] enet_rx_d, + input wire enet_rx_dv, + output wire enet_tx_clk, + output wire [3:0] enet_tx_d, + output wire enet_tx_en, + output wire enet_resetn, + input wire enet_int +); + +// Clock and reset + +// Internal 125 MHz clock +wire clk_int; +wire rst_int; + +wire pll_rst = ~c10_resetn; +wire pll_locked; + +wire clk90_int; + +altpll #( + .bandwidth_type("AUTO"), + .clk0_divide_by(1), + .clk0_duty_cycle(50), + .clk0_multiply_by(1), + .clk0_phase_shift("0"), + .clk1_divide_by(1), + .clk1_duty_cycle(50), + .clk1_multiply_by(1), + .clk1_phase_shift("2000"), + .compensate_clock("CLK0"), + .inclk0_input_frequency(8000), + .intended_device_family("Cyclone 10 LP"), + .operation_mode("NORMAL"), + .pll_type("AUTO"), + .port_activeclock("PORT_UNUSED"), + .port_areset("PORT_USED"), + .port_clkbad0("PORT_UNUSED"), + .port_clkbad1("PORT_UNUSED"), + .port_clkloss("PORT_UNUSED"), + .port_clkswitch("PORT_UNUSED"), + .port_configupdate("PORT_UNUSED"), + .port_fbin("PORT_UNUSED"), + .port_inclk0("PORT_USED"), + .port_inclk1("PORT_UNUSED"), + .port_locked("PORT_USED"), + .port_pfdena("PORT_UNUSED"), + .port_phasecounterselect("PORT_UNUSED"), + .port_phasedone("PORT_UNUSED"), + .port_phasestep("PORT_UNUSED"), + .port_phaseupdown("PORT_UNUSED"), + .port_pllena("PORT_UNUSED"), + .port_scanaclr("PORT_UNUSED"), + .port_scanclk("PORT_UNUSED"), + .port_scanclkena("PORT_UNUSED"), + .port_scandata("PORT_UNUSED"), + .port_scandataout("PORT_UNUSED"), + .port_scandone("PORT_UNUSED"), + .port_scanread("PORT_UNUSED"), + .port_scanwrite("PORT_UNUSED"), + .port_clk0("PORT_USED"), + .port_clk1("PORT_USED"), + .port_clk2("PORT_UNUSED"), + .port_clk3("PORT_UNUSED"), + .port_clk4("PORT_UNUSED"), + .port_clk5("PORT_UNUSED"), + .port_clkena0("PORT_UNUSED"), + .port_clkena1("PORT_UNUSED"), + .port_clkena2("PORT_UNUSED"), + .port_clkena3("PORT_UNUSED"), + .port_clkena4("PORT_UNUSED"), + .port_clkena5("PORT_UNUSED"), + .port_extclk0("PORT_UNUSED"), + .port_extclk1("PORT_UNUSED"), + .port_extclk2("PORT_UNUSED"), + .port_extclk3("PORT_UNUSED"), + .self_reset_on_loss_lock("ON"), + .width_clock(5) +) +altpll_component ( + .areset(pll_rst), + .inclk({1'b0, enet_clk_125m}), + .clk({clk90_int, clk_int}), + .locked(pll_locked), + .activeclock(), + .clkbad(), + .clkena({6{1'b1}}), + .clkloss(), + .clkswitch(1'b0), + .configupdate(1'b0), + .enable0(), + .enable1(), + .extclk(), + .extclkena({4{1'b1}}), + .fbin(1'b1), + .fbmimicbidir(), + .fbout(), + .fref(), + .icdrclk(), + .pfdena(1'b1), + .phasecounterselect({4{1'b1}}), + .phasedone(), + .phasestep(1'b1), + .phaseupdown(1'b1), + .pllena(1'b1), + .scanaclr(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0), + .scandataout(), + .scandone(), + .scanread(1'b0), + .scanwrite(1'b0), + .sclkout0(), + .sclkout1(), + .vcooverrange(), + .vcounderrange() +); + +sync_reset #( + .N(4) +) +sync_reset_inst ( + .clk(clk_int), + .rst(~pll_locked), + .out(rst_int) +); + +// GPIO +wire [3:0] btn_int; +wire [2:0] sw_int; +wire [3:0] led_int; + +debounce_switch #( + .WIDTH(7), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_int), + .rst(rst_int), + .in({user_pb, + user_dip}), + .out({btn_int, + sw_int}) +); + +assign user_led = ~led_int; + +fpga_core +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk(clk_int), + .clk90(clk90_int), + .rst(rst_int), + + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led(led_int), + + /* + * Ethernet: 1000BASE-T RGMII + */ + .phy_rx_clk(enet_rx_clk), + .phy_rxd(enet_rx_d), + .phy_rx_ctl(enet_rx_dv), + .phy_tx_clk(enet_tx_clk), + .phy_txd(enet_tx_d), + .phy_tx_ctl(enet_tx_en), + .phy_reset_n(enet_resetn), + .phy_int_n(enet_int) +); + +endmodule diff --git a/fpga/lib/eth/example/C10LP/fpga/rtl/fpga_core.v b/fpga/lib/eth/example/C10LP/fpga/rtl/fpga_core.v new file mode 100644 index 000000000..b37fc3599 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/rtl/fpga_core.v @@ -0,0 +1,567 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter TARGET = "ALTERA" +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire clk, + input wire clk90, + input wire rst, + + /* + * GPIO + */ + input wire [3:0] btn, + input wire [2:0] sw, + output wire [3:0] led, + + /* + * Ethernet: 1000BASE-T RGMII + */ + input wire phy_rx_clk, + input wire [3:0] phy_rxd, + input wire phy_rx_ctl, + output wire phy_tx_clk, + output wire [3:0] phy_txd, + output wire phy_tx_ctl, + output wire phy_reset_n, + input wire phy_int_n +); + +// AXI between MAC and Ethernet modules +wire [7:0] rx_axis_tdata; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [7:0] tx_axis_tdata; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [7:0] rx_eth_payload_axis_tdata; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [7:0] tx_eth_payload_axis_tdata; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [7:0] rx_ip_payload_axis_tdata; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [7:0] tx_ip_payload_axis_tdata; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [7:0] rx_udp_payload_axis_tdata; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [7:0] tx_udp_payload_axis_tdata; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [7:0] rx_fifo_udp_payload_axis_tdata; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [7:0] tx_fifo_udp_payload_axis_tdata; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (tx_udp_payload_axis_tvalid) begin + if (!valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + valid_last <= 1'b1; + end + if (tx_udp_payload_axis_tlast) begin + valid_last <= 1'b0; + end + end + + if (rst) begin + led_reg <= 0; + end +end + +//assign led = sw; +assign led = led_reg; +assign phy_reset_n = ~rst; + +eth_mac_1g_rgmii_fifo #( + .TARGET(TARGET), + .USE_CLK90("TRUE"), + .ENABLE_PADDING(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_inst ( + .gtx_clk(clk), + .gtx_clk90(clk90), + .gtx_rst(rst), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .rgmii_rx_clk(phy_rx_clk), + .rgmii_rxd(phy_rxd), + .rgmii_rx_ctl(phy_rx_ctl), + .rgmii_tx_clk(phy_tx_clk), + .rgmii_txd(phy_txd), + .rgmii_tx_ctl(phy_tx_ctl), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + .speed(), + + .ifg_delay(12) +); + +eth_axis_rx +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(8), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(0), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule diff --git a/fpga/lib/eth/example/C10LP/fpga/rtl/sync_signal.v b/fpga/lib/eth/example/C10LP/fpga/rtl/sync_signal.v new file mode 100644 index 000000000..b2a8ce3de --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/rtl/sync_signal.v @@ -0,0 +1,58 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/arp_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/arp_ep.py new file mode 120000 index 000000000..7b3d3ed97 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/arp_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/arp_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/axis_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/axis_ep.py new file mode 120000 index 000000000..385bb0300 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/axis_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/axis_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/eth_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/eth_ep.py new file mode 120000 index 000000000..bac19feea --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/eth_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/eth_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/gmii_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/gmii_ep.py new file mode 120000 index 000000000..754166f2f --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/gmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/gmii_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/ip_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/ip_ep.py new file mode 120000 index 000000000..6dfa928a7 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/ip_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/ip_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/rgmii_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/rgmii_ep.py new file mode 120000 index 000000000..986c56280 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/rgmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/rgmii_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.py b/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.py new file mode 100755 index 000000000..b937f5392 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.py @@ -0,0 +1,302 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2015-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +from myhdl import * +import os + +import eth_ep +import arp_ep +import udp_ep +import rgmii_ep + +module = 'fpga_core' +testbench = 'test_%s' % module + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("../lib/eth/rtl/iddr.v") +srcs.append("../lib/eth/rtl/oddr.v") +srcs.append("../lib/eth/rtl/ssio_ddr_in.v") +srcs.append("../lib/eth/rtl/ssio_ddr_out.v") +srcs.append("../lib/eth/rtl/rgmii_phy_if.v") +srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v") +srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii.v") +srcs.append("../lib/eth/rtl/eth_mac_1g.v") +srcs.append("../lib/eth/rtl/axis_gmii_rx.v") +srcs.append("../lib/eth/rtl/axis_gmii_tx.v") +srcs.append("../lib/eth/rtl/lfsr.v") +srcs.append("../lib/eth/rtl/eth_axis_rx.v") +srcs.append("../lib/eth/rtl/eth_axis_tx.v") +srcs.append("../lib/eth/rtl/udp_complete.v") +srcs.append("../lib/eth/rtl/udp_checksum_gen.v") +srcs.append("../lib/eth/rtl/udp.v") +srcs.append("../lib/eth/rtl/udp_ip_rx.v") +srcs.append("../lib/eth/rtl/udp_ip_tx.v") +srcs.append("../lib/eth/rtl/ip_complete.v") +srcs.append("../lib/eth/rtl/ip.v") +srcs.append("../lib/eth/rtl/ip_eth_rx.v") +srcs.append("../lib/eth/rtl/ip_eth_tx.v") +srcs.append("../lib/eth/rtl/ip_arb_mux.v") +srcs.append("../lib/eth/rtl/ip_mux.v") +srcs.append("../lib/eth/rtl/arp.v") +srcs.append("../lib/eth/rtl/arp_cache.v") +srcs.append("../lib/eth/rtl/arp_eth_rx.v") +srcs.append("../lib/eth/rtl/arp_eth_tx.v") +srcs.append("../lib/eth/rtl/eth_arb_mux.v") +srcs.append("../lib/eth/rtl/eth_mux.v") +srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") +srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") +srcs.append("%s.v" % testbench) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) + +def bench(): + + # Parameters + TARGET = "SIM" + + # Inputs + clk = Signal(bool(0)) + clk90 = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + btn = Signal(intbv(0)[4:]) + sw = Signal(intbv(0)[3:]) + phy_rx_clk = Signal(bool(0)) + phy_rxd = Signal(intbv(0)[4:]) + phy_rx_ctl = Signal(bool(0)) + phy_int_n = Signal(bool(1)) + + # Outputs + led = Signal(intbv(0)[4:]) + phy_tx_clk = Signal(bool(0)) + phy_txd = Signal(intbv(0)[4:]) + phy_tx_ctl = Signal(bool(0)) + phy_reset_n = Signal(bool(0)) + + # sources and sinks + mii_select = Signal(bool(0)) + + rgmii_source = rgmii_ep.RGMIISource() + + rgmii_source_logic = rgmii_source.create_logic( + phy_rx_clk, + rst, + txd=phy_rxd, + tx_ctl=phy_rx_ctl, + mii_select=mii_select, + name='rgmii_source' + ) + + rgmii_sink = rgmii_ep.RGMIISink() + + rgmii_sink_logic = rgmii_sink.create_logic( + phy_tx_clk, + rst, + rxd=phy_txd, + rx_ctl=phy_tx_ctl, + mii_select=mii_select, + name='rgmii_sink' + ) + + # DUT + if os.system(build_cmd): + raise Exception("Error running build command") + + dut = Cosimulation( + "vvp -m myhdl %s.vvp -lxt2" % testbench, + clk=clk, + clk90=clk90, + rst=rst, + current_test=current_test, + + btn=btn, + sw=sw, + led=led, + + phy_rx_clk=phy_rx_clk, + phy_rxd=phy_rxd, + phy_rx_ctl=phy_rx_ctl, + phy_tx_clk=phy_tx_clk, + phy_txd=phy_txd, + phy_tx_ctl=phy_tx_ctl, + phy_reset_n=phy_reset_n, + phy_int_n=phy_int_n + ) + + @always(delay(4)) + def clkgen(): + clk.next = not clk + + @instance + def clkgen2(): + yield delay(4+2) + while True: + clk90.next = not clk90 + yield delay(4) + + rx_clk_hp = Signal(int(4)) + + @instance + def rx_clk_gen(): + while True: + yield delay(int(rx_clk_hp)) + phy_rx_clk.next = not phy_rx_clk + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + yield clk.posedge + rst.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + # testbench stimulus + + yield clk.posedge + print("test 1: test UDP RX packet") + current_test.next = 1 + + test_frame = udp_ep.UDPFrame() + test_frame.eth_dest_mac = 0x020000000000 + test_frame.eth_src_mac = 0xDAD1D2D3D4D5 + test_frame.eth_type = 0x0800 + test_frame.ip_version = 4 + test_frame.ip_ihl = 5 + test_frame.ip_dscp = 0 + test_frame.ip_ecn = 0 + test_frame.ip_length = None + test_frame.ip_identification = 0 + test_frame.ip_flags = 2 + test_frame.ip_fragment_offset = 0 + test_frame.ip_ttl = 64 + test_frame.ip_protocol = 0x11 + test_frame.ip_header_checksum = None + test_frame.ip_source_ip = 0xc0a80181 + test_frame.ip_dest_ip = 0xc0a80180 + test_frame.udp_source_port = 5678 + test_frame.udp_dest_port = 1234 + test_frame.payload = bytearray(range(32)) + test_frame.build() + + rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data) + + # wait for ARP request packet + while rgmii_sink.empty(): + yield clk.posedge + + rx_frame = rgmii_sink.recv() + check_eth_frame = eth_ep.EthFrame() + check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) + check_frame = arp_ep.ARPFrame() + check_frame.parse_eth(check_eth_frame) + + print(check_frame) + + assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF + assert check_frame.eth_src_mac == 0x020000000000 + assert check_frame.eth_type == 0x0806 + assert check_frame.arp_htype == 0x0001 + assert check_frame.arp_ptype == 0x0800 + assert check_frame.arp_hlen == 6 + assert check_frame.arp_plen == 4 + assert check_frame.arp_oper == 1 + assert check_frame.arp_sha == 0x020000000000 + assert check_frame.arp_spa == 0xc0a80180 + assert check_frame.arp_tha == 0x000000000000 + assert check_frame.arp_tpa == 0xc0a80181 + + # generate response + arp_frame = arp_ep.ARPFrame() + arp_frame.eth_dest_mac = 0x020000000000 + arp_frame.eth_src_mac = 0xDAD1D2D3D4D5 + arp_frame.eth_type = 0x0806 + arp_frame.arp_htype = 0x0001 + arp_frame.arp_ptype = 0x0800 + arp_frame.arp_hlen = 6 + arp_frame.arp_plen = 4 + arp_frame.arp_oper = 2 + arp_frame.arp_sha = 0xDAD1D2D3D4D5 + arp_frame.arp_spa = 0xc0a80181 + arp_frame.arp_tha = 0x020000000000 + arp_frame.arp_tpa = 0xc0a80180 + + rgmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data) + + while rgmii_sink.empty(): + yield clk.posedge + + rx_frame = rgmii_sink.recv() + check_eth_frame = eth_ep.EthFrame() + check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) + check_frame = udp_ep.UDPFrame() + check_frame.parse_eth(check_eth_frame) + + print(check_frame) + + assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 + assert check_frame.eth_src_mac == 0x020000000000 + assert check_frame.eth_type == 0x0800 + assert check_frame.ip_version == 4 + assert check_frame.ip_ihl == 5 + assert check_frame.ip_dscp == 0 + assert check_frame.ip_ecn == 0 + assert check_frame.ip_identification == 0 + assert check_frame.ip_flags == 2 + assert check_frame.ip_fragment_offset == 0 + assert check_frame.ip_ttl == 64 + assert check_frame.ip_protocol == 0x11 + assert check_frame.ip_source_ip == 0xc0a80180 + assert check_frame.ip_dest_ip == 0xc0a80181 + assert check_frame.udp_source_port == 1234 + assert check_frame.udp_dest_port == 5678 + assert check_frame.payload.data == bytearray(range(32)) + + assert rgmii_source.empty() + assert rgmii_sink.empty() + + yield delay(100) + + raise StopSimulation + + return instances() + +def test_bench(): + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.v b/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.v new file mode 100644 index 000000000..bd4238578 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/test_fpga_core.v @@ -0,0 +1,104 @@ +/* + +Copyright (c) 2015-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Testbench for fpga_core + */ +module test_fpga_core; + +// Parameters +parameter TARGET = "SIM"; + +// Inputs +reg clk = 0; +reg clk90 = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg [3:0] btn = 0; +reg [2:0] sw = 0; +reg phy_rx_clk = 0; +reg [3:0] phy_rxd = 0; +reg phy_rx_ctl = 0; +reg phy_int_n = 1; + +// Outputs +wire [3:0] led; +wire phy_tx_clk; +wire [3:0] phy_txd; +wire phy_tx_ctl; +wire phy_reset_n; + +initial begin + // myhdl integration + $from_myhdl( + clk, + clk90, + rst, + current_test, + btn, + sw, + phy_rx_clk, + phy_rxd, + phy_rx_ctl, + phy_int_n + ); + $to_myhdl( + led, + phy_tx_clk, + phy_txd, + phy_tx_ctl, + phy_reset_n + ); + + // dump file + $dumpfile("test_fpga_core.lxt"); + $dumpvars(0, test_fpga_core); +end + +fpga_core #( + .TARGET(TARGET) +) +UUT ( + .clk(clk), + .clk90(clk90), + .rst(rst), + .btn(btn), + .sw(sw), + .led(led), + .phy_rx_clk(phy_rx_clk), + .phy_rxd(phy_rxd), + .phy_rx_ctl(phy_rx_ctl), + .phy_tx_clk(phy_tx_clk), + .phy_txd(phy_txd), + .phy_tx_ctl(phy_tx_ctl), + .phy_reset_n(phy_reset_n), + .phy_int_n(phy_int_n) +); + +endmodule diff --git a/fpga/lib/eth/example/C10LP/fpga/tb/udp_ep.py b/fpga/lib/eth/example/C10LP/fpga/tb/udp_ep.py new file mode 120000 index 000000000..073c5d3c6 --- /dev/null +++ b/fpga/lib/eth/example/C10LP/fpga/tb/udp_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/udp_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/Makefile b/fpga/lib/eth/example/DE2-115/fpga/Makefile new file mode 100644 index 000000000..8d766f026 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/Makefile @@ -0,0 +1,25 @@ +# Targets +TARGETS:= + +# Subdirectories +SUBDIRS = fpga +SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) + +# Rules +.PHONY: all +all: $(SUBDIRS) $(TARGETS) + +.PHONY: $(SUBDIRS) +$(SUBDIRS): + cd $@ && $(MAKE) + +.PHONY: $(SUBDIRS_CLEAN) +$(SUBDIRS_CLEAN): + cd $(@:.clean=) && $(MAKE) clean + +.PHONY: clean +clean: $(SUBDIRS_CLEAN) + -rm -rf $(TARGETS) + +program: + #program commands diff --git a/fpga/lib/eth/example/DE2-115/fpga/README.md b/fpga/lib/eth/example/DE2-115/fpga/README.md new file mode 100644 index 000000000..bdca5c69f --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/README.md @@ -0,0 +1,25 @@ +# Verilog Ethernet DE2-115 Example Design + +## Introduction + +This example design targets the Terasic DE2-115 FPGA board. + +The design by default listens to UDP port 1234 at IP address 192.168.1.128 and +will echo back any packets received. The design will also respond correctly +to ARP requests. + +FPGA: EP4CE115F29C7 +PHY: Marvell Alaska 88E1111 + +## How to build + +Run make to build. Ensure that the Altera Quartus toolchain components are +in PATH. + +## How to test + +Run make program to program the board with the Altera software. Then run +netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any +text entered into netcat will be echoed back after pressing enter. + + diff --git a/fpga/lib/eth/example/DE2-115/fpga/common/quartus.mk b/fpga/lib/eth/example/DE2-115/fpga/common/quartus.mk new file mode 100644 index 000000000..e06d66313 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/common/quartus.mk @@ -0,0 +1,141 @@ +################################################################### +# +# Altera FPGA Makefile +# +# Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. Stratix V) +# FPGA_DEVICE - FPGA device (e.g. 5SGXEA7N2F45C2) +# SYN_FILES - space-separated list of source files +# QSF_FILES - space-separated list of settings files +# SDC_FILES - space-separated list of timing constraint files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = "Stratix V" +# FPGA_DEVICE = 5SGXEA7N2F45C2 +# SYN_FILES = rtl/fpga.v rtl/clocks.v +# QSF_FILES = fpga.qsf +# SDC_FILES = fpga.sdc +# include ../common/altera.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# output files to hang on to +.PRECIOUS: %.sof %.map.rpt %.fit.rpt %.asm.rpt %.sta.rpt + +# any project specific settings +-include ../config.mk + +SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) + +ifdef QSF_FILES + QSF_FILES_REL = $(patsubst %, ../%, $(QSF_FILES)) +else + QSF_FILES_REL = ../$(FPGA_TOP).qsf +endif + +SDC_FILES_REL = $(patsubst %, ../%, $(SDC_FILES)) + +ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and database +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).sof + +clean: + rm -rf *.rpt *.summary *.smsg *.chg smart.log *.htm *.eqn *.pin *.sof *.pof *.qsf *.qpf *.jdi *.sld *.txt db incremental_db reconfig_mif + +map: smart.log $(PROJECT).map.rpt +fit: smart.log $(PROJECT).fit.rpt +asm: smart.log $(PROJECT).asm.rpt +sta: smart.log $(PROJECT).sta.rpt +smart: smart.log + +################################################################### +# Executable Configuration +################################################################### + +MAP_ARGS = --family=$(FPGA_FAMILY) +FIT_ARGS = --part=$(FPGA_DEVICE) +ASM_ARGS = +STA_ARGS = + +################################################################### +# Target implementations +################################################################### + +STAMP = echo done > + +%.map.rpt: map.chg $(SYN_FILES_REL) + quartus_map $(MAP_ARGS) $(FPGA_TOP) + +%.fit.rpt: fit.chg %.map.rpt + quartus_fit $(FIT_ARGS) $(FPGA_TOP) + +%.sta.rpt: sta.chg %.fit.rpt + quartus_sta $(STA_ARGS) $(FPGA_TOP) + +%.asm.rpt: asm.chg %.sta.rpt + quartus_asm $(ASM_ARGS) $(FPGA_TOP) + mkdir -p rev + EXT=sof; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do let COUNT=COUNT+1; done; \ + cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; + +%.sof: smart.log %.asm.rpt + + +smart.log: $(ASSIGNMENT_FILES) + quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log + +################################################################### +# Project initialization +################################################################### + +$(ASSIGNMENT_FILES): $(QSF_FILES_REL) $(SYN_FILES_REL) + rm -f $(FPGA_TOP).qsf + quartus_sh --prepare -f $(FPGA_FAMILY) -d $(FPGA_DEVICE) -t $(FPGA_TOP) $(FPGA_TOP) + echo >> $(FPGA_TOP).qsf + echo >> $(FPGA_TOP).qsf + echo "# Source files" >> $(FPGA_TOP).qsf + for x in $(SYN_FILES_REL); do \ + case $${x##*.} in \ + v|V) echo set_global_assignment -name VERILOG_FILE $$x >> $(FPGA_TOP).qsf ;;\ + vhd|VHD) echo set_global_assignment -name VHDL_FILE $$x >> $(FPGA_TOP).qsf ;;\ + qip|QIP) echo set_global_assignment -name QIP_FILE $$x >> $(FPGA_TOP).qsf ;;\ + *) echo set_global_assignment -name SOURCE_FILE $$x >> $(FPGA_TOP).qsf ;;\ + esac; \ + done + echo >> $(FPGA_TOP).qsf + echo "# SDC files" >> $(FPGA_TOP).qsf + for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE $$x >> $(FPGA_TOP).qsf; done + for x in $(QSF_FILES_REL); do printf "\n#\n# Included QSF file $$x\n#\n" >> $(FPGA_TOP).qsf; cat $$x >> $(FPGA_TOP).qsf; done + +map.chg: + $(STAMP) map.chg +fit.chg: + $(STAMP) fit.chg +sta.chg: + $(STAMP) sta.chg +asm.chg: + $(STAMP) asm.chg + + diff --git a/fpga/lib/eth/example/DE2-115/fpga/fpga.qsf b/fpga/lib/eth/example/DE2-115/fpga/fpga.qsf new file mode 100644 index 000000000..1a57254ed --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/fpga.qsf @@ -0,0 +1,1201 @@ +# I/O constraints for the Terasic DE2-115 FPGA board +# part: EP4CE115F29C7 + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_AUTO_COMPUTE_TJ ON +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 + +#============================================================ +# Sma +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT + +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] + +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] + +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] + +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] + +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] + +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] + +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW + +#============================================================ +# SEG7 +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] + +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] + +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] + +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] + +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] + +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] + +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] + +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] + +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] + +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] + +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX4 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX5 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX6 +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX7 + +#============================================================ +# LCD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON + +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON + +#============================================================ +# RS232 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS + +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_J13 -to UART_CTS +set_location_assignment PIN_G14 -to UART_RTS + +#============================================================ +# PS2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_G5 -to PS2_CLK2 + +#============================================================ +# SDCARD +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] + +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] + +#============================================================ +# VGA +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] + +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] + +#============================================================ +# Audio +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK + +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK + +#============================================================ +# I2C for EEPROM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT + +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT + +#============================================================ +# I2C for Audioand Tv-Decode 1 and 2 +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT + +#============================================================ +# Ethernet +#============================================================ +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 + +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 + +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_C14 -to ENET0_LINK100 + +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D13 -to ENET1_LINK100 + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_location_assignment PIN_A14 -to ENETCLK_25 + +#============================================================ +# TV Decoder +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] + +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] + +#============================================================ +# USB +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N + +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N + +#============================================================ +# IR Receiver +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD + +set_location_assignment PIN_Y15 -to IRDA_RXD + +#============================================================ +# SDRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] + +#============================================================ +# SRAM +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N + +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N + +#============================================================ +# Flash +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N + +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] + +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 + +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 + +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] + +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 + +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 + +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] + +#============================================================ +# HSMC, HSMC connect to HSMC Default +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] + +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] diff --git a/fpga/lib/eth/example/DE2-115/fpga/fpga.sdc b/fpga/lib/eth/example/DE2-115/fpga/fpga.sdc new file mode 100644 index 000000000..68cddb967 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/fpga.sdc @@ -0,0 +1,75 @@ + +create_clock -period 20.00 -name {CLOCK_50} [get_ports {CLOCK_50}] +create_clock -period 20.00 -name {CLOCK2_50} [get_ports {CLOCK2_50}] +create_clock -period 20.00 -name {CLOCK3_50} [get_ports {CLOCK3_50}] +create_clock -period 40.00 -name {ENETCLK_25} [get_ports {ENETCLK_25}] + +set_clock_groups -asynchronous -group [get_clocks {CLOCK_50}] +set_clock_groups -asynchronous -group [get_clocks {CLOCK2_50}] +set_clock_groups -asynchronous -group [get_clocks {CLOCK3_50}] +set_clock_groups -asynchronous -group [get_clocks {ENETCLK_25}] + +create_clock -period "40.000 ns" -name {altera_reserved_tck} {altera_reserved_tck} +set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] + +#JTAG Signal Constraints +#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook) +set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi] +set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms] +set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo] + +# Ethernet MDIO interface +set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdc}] +set_input_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdio}] +set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdio}] + +set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdc}] +set_input_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdio}] +set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdio}] + +set_false_path -from [get_ports {KEY[*]}] -to * +set_false_path -from [get_ports {SW[*]}] -to * +set_false_path -from * -to [get_ports {LEDG[*]}] +set_false_path -from * -to [get_ports {LEDR[*]}] +set_false_path -from * -to [get_ports {HEX0[*]}] +set_false_path -from * -to [get_ports {HEX1[*]}] +set_false_path -from * -to [get_ports {HEX2[*]}] +set_false_path -from * -to [get_ports {HEX3[*]}] +set_false_path -from * -to [get_ports {HEX4[*]}] +set_false_path -from * -to [get_ports {HEX5[*]}] +set_false_path -from * -to [get_ports {HEX6[*]}] +set_false_path -from * -to [get_ports {HEX7[*]}] + +set_false_path -from [get_ports ENET0_INT_N] -to * +set_false_path -from * -to [get_ports ENET0_RST_N] + +set_false_path -from [get_ports ENET1_INT_N] -to * +set_false_path -from * -to [get_ports ENET1_RST_N] + + +derive_pll_clocks +derive_clock_uncertainty + + +source ../lib/eth/syn/eth_mac_1g_rgmii.sdc +source ../lib/eth/syn/rgmii_phy_if.sdc +source ../lib/eth/syn/rgmii_io.sdc +source ../lib/eth/lib/axis/syn/sync_reset.sdc +source ../lib/eth/lib/axis/syn/axis_async_fifo.sdc + +# clocking infrastructure +constrain_sync_reset_inst "sync_reset_inst" + +# ENET0 RGMII MAC +constrain_eth_mac_1g_rgmii_inst "core_inst|eth_mac_inst|eth_mac_1g_rgmii_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|rx_fifo|fifo_inst" +constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|tx_fifo|fifo_inst" + +# ENET0 RGMII interface +constrain_rgmii_input_pins "enet0" "ENET0_RX_CLK" "ENET0_RX_DV ENET0_RX_D*" +constrain_rgmii_output_pins "enet0" "altpll_component|auto_generated|pll1|clk[0]" "ENET0_GTX_CLK" "ENET0_TX_EN ENET0_TX_D*" + +# ENET1 RGMII interface +constrain_rgmii_input_pins "enet1" "ENET1_RX_CLK" "ENET1_RX_DV ENET1_RX_D*" +constrain_rgmii_output_pins "enet1" "altpll_component|auto_generated|pll1|clk[0]" "ENET1_GTX_CLK" "ENET1_TX_EN ENET1_TX_D*" + diff --git a/fpga/lib/eth/example/DE2-115/fpga/fpga/Makefile b/fpga/lib/eth/example/DE2-115/fpga/fpga/Makefile new file mode 100644 index 000000000..d1c4c97cc --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/fpga/Makefile @@ -0,0 +1,59 @@ + +# FPGA settings +FPGA_TOP = fpga +FPGA_FAMILY = "Cyclone IV E" +FPGA_DEVICE = EP4CE115F29C7 + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/hex_display.v +SYN_FILES += lib/eth/rtl/iddr.v +SYN_FILES += lib/eth/rtl/oddr.v +SYN_FILES += lib/eth/rtl/ssio_ddr_in.v +SYN_FILES += lib/eth/rtl/ssio_ddr_out.v +SYN_FILES += lib/eth/rtl/rgmii_phy_if.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v +SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v +SYN_FILES += lib/eth/rtl/eth_mac_1g.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/eth_axis_rx.v +SYN_FILES += lib/eth/rtl/eth_axis_tx.v +SYN_FILES += lib/eth/rtl/udp_complete.v +SYN_FILES += lib/eth/rtl/udp_checksum_gen.v +SYN_FILES += lib/eth/rtl/udp.v +SYN_FILES += lib/eth/rtl/udp_ip_rx.v +SYN_FILES += lib/eth/rtl/udp_ip_tx.v +SYN_FILES += lib/eth/rtl/ip_complete.v +SYN_FILES += lib/eth/rtl/ip.v +SYN_FILES += lib/eth/rtl/ip_eth_rx.v +SYN_FILES += lib/eth/rtl/ip_eth_tx.v +SYN_FILES += lib/eth/rtl/ip_arb_mux.v +SYN_FILES += lib/eth/rtl/ip_mux.v +SYN_FILES += lib/eth/rtl/arp.v +SYN_FILES += lib/eth/rtl/arp_cache.v +SYN_FILES += lib/eth/rtl/arp_eth_rx.v +SYN_FILES += lib/eth/rtl/arp_eth_tx.v +SYN_FILES += lib/eth/rtl/eth_arb_mux.v +SYN_FILES += lib/eth/rtl/eth_mux.v +SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v +SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v + +# QSF files +QSF_FILES = fpga.qsf + +# SDC files +SDC_FILES = fpga.sdc + +include ../common/quartus.mk + +program: fpga + quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof" diff --git a/fpga/lib/eth/example/DE2-115/fpga/lib/eth b/fpga/lib/eth/example/DE2-115/fpga/lib/eth new file mode 120000 index 000000000..11a54ed36 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/lib/eth @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/rtl/debounce_switch.v b/fpga/lib/eth/example/DE2-115/fpga/rtl/debounce_switch.v new file mode 100644 index 000000000..bb631cc35 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/rtl/debounce_switch.v @@ -0,0 +1,89 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes switch and button inputs with a slow sampled shift register + */ +module debounce_switch #( + parameter WIDTH=1, // width of the input and output signals + parameter N=3, // length of shift register + parameter RATE=125000 // clock division factor +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [23:0] cnt_reg = 24'd0; + +reg [N-1:0] debounce_reg[WIDTH-1:0]; + +reg [WIDTH-1:0] state; + +/* + * The synchronized output is the state register + */ +assign out = state; + +integer k; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cnt_reg <= 0; + state <= 0; + + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= 0; + end + end else begin + if (cnt_reg < RATE) begin + cnt_reg <= cnt_reg + 24'd1; + end else begin + cnt_reg <= 24'd0; + end + + if (cnt_reg == 24'd0) begin + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; + end + end + + for (k = 0; k < WIDTH; k = k + 1) begin + if (|debounce_reg[k] == 0) begin + state[k] <= 0; + end else if (&debounce_reg[k] == 1) begin + state[k] <= 1; + end else begin + state[k] <= state[k]; + end + end + end +end + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga.v b/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga.v new file mode 100644 index 000000000..ae51d7df2 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga.v @@ -0,0 +1,263 @@ +/* + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 125MHz + */ + input wire CLOCK_50, + + /* + * GPIO + */ + input wire [3:0] KEY, + input wire [17:0] SW, + output wire [8:0] LEDG, + output wire [17:0] LEDR, + output wire [6:0] HEX0, + output wire [6:0] HEX1, + output wire [6:0] HEX2, + output wire [6:0] HEX3, + output wire [6:0] HEX4, + output wire [6:0] HEX5, + output wire [6:0] HEX6, + output wire [6:0] HEX7, + output wire [35:0] GPIO, + + /* + * Ethernet: 1000BASE-T RGMII + */ + output wire ENET0_GTX_CLK, + output wire [3:0] ENET0_TX_DATA, + output wire ENET0_TX_EN, + input wire ENET0_RX_CLK, + input wire [3:0] ENET0_RX_DATA, + input wire ENET0_RX_DV, + output wire ENET0_RST_N, + input wire ENET0_INT_N, + + output wire ENET1_GTX_CLK, + output wire [3:0] ENET1_TX_DATA, + output wire ENET1_TX_EN, + input wire ENET1_RX_CLK, + input wire [3:0] ENET1_RX_DATA, + input wire ENET1_RX_DV, + output wire ENET1_RST_N, + input wire ENET1_INT_N +); + +// Clock and reset + +// Internal 125 MHz clock +wire clk_int; +wire rst_int; + +wire pll_rst = ~KEY[3]; +wire pll_locked; + +wire clk90_int; + +altpll #( + .bandwidth_type("AUTO"), + .clk0_divide_by(2), + .clk0_duty_cycle(50), + .clk0_multiply_by(5), + .clk0_phase_shift("0"), + .clk1_divide_by(2), + .clk1_duty_cycle(50), + .clk1_multiply_by(5), + .clk1_phase_shift("2000"), + .compensate_clock("CLK0"), + .inclk0_input_frequency(20000), + .intended_device_family("Cyclone IV E"), + .operation_mode("NORMAL"), + .pll_type("AUTO"), + .port_activeclock("PORT_UNUSED"), + .port_areset("PORT_USED"), + .port_clkbad0("PORT_UNUSED"), + .port_clkbad1("PORT_UNUSED"), + .port_clkloss("PORT_UNUSED"), + .port_clkswitch("PORT_UNUSED"), + .port_configupdate("PORT_UNUSED"), + .port_fbin("PORT_UNUSED"), + .port_inclk0("PORT_USED"), + .port_inclk1("PORT_UNUSED"), + .port_locked("PORT_USED"), + .port_pfdena("PORT_UNUSED"), + .port_phasecounterselect("PORT_UNUSED"), + .port_phasedone("PORT_UNUSED"), + .port_phasestep("PORT_UNUSED"), + .port_phaseupdown("PORT_UNUSED"), + .port_pllena("PORT_UNUSED"), + .port_scanaclr("PORT_UNUSED"), + .port_scanclk("PORT_UNUSED"), + .port_scanclkena("PORT_UNUSED"), + .port_scandata("PORT_UNUSED"), + .port_scandataout("PORT_UNUSED"), + .port_scandone("PORT_UNUSED"), + .port_scanread("PORT_UNUSED"), + .port_scanwrite("PORT_UNUSED"), + .port_clk0("PORT_USED"), + .port_clk1("PORT_USED"), + .port_clk2("PORT_UNUSED"), + .port_clk3("PORT_UNUSED"), + .port_clk4("PORT_UNUSED"), + .port_clk5("PORT_UNUSED"), + .port_clkena0("PORT_UNUSED"), + .port_clkena1("PORT_UNUSED"), + .port_clkena2("PORT_UNUSED"), + .port_clkena3("PORT_UNUSED"), + .port_clkena4("PORT_UNUSED"), + .port_clkena5("PORT_UNUSED"), + .port_extclk0("PORT_UNUSED"), + .port_extclk1("PORT_UNUSED"), + .port_extclk2("PORT_UNUSED"), + .port_extclk3("PORT_UNUSED"), + .self_reset_on_loss_lock("ON"), + .width_clock(5) +) +altpll_component ( + .areset(pll_rst), + .inclk({1'b0, CLOCK_50}), + .clk({clk90_int, clk_int}), + .locked(pll_locked), + .activeclock(), + .clkbad(), + .clkena({6{1'b1}}), + .clkloss(), + .clkswitch(1'b0), + .configupdate(1'b0), + .enable0(), + .enable1(), + .extclk(), + .extclkena({4{1'b1}}), + .fbin(1'b1), + .fbmimicbidir(), + .fbout(), + .fref(), + .icdrclk(), + .pfdena(1'b1), + .phasecounterselect({4{1'b1}}), + .phasedone(), + .phasestep(1'b1), + .phaseupdown(1'b1), + .pllena(1'b1), + .scanaclr(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0), + .scandataout(), + .scandone(), + .scanread(1'b0), + .scanwrite(1'b0), + .sclkout0(), + .sclkout1(), + .vcooverrange(), + .vcounderrange() +); + +sync_reset #( + .N(4) +) +sync_reset_inst ( + .clk(clk_int), + .rst(~pll_locked), + .out(rst_int) +); + +// GPIO +wire [3:0] btn_int; +wire [17:0] sw_int; + +debounce_switch #( + .WIDTH(4+18), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_int), + .rst(rst_int), + .in({~KEY, + SW}), + .out({btn_int, + sw_int}) +); + +fpga_core +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk(clk_int), + .clk90(clk90_int), + .rst(rst_int), + + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .ledg(LEDG), + .ledr(LEDR), + .hex0(HEX0), + .hex1(HEX1), + .hex2(HEX2), + .hex3(HEX3), + .hex4(HEX4), + .hex5(HEX5), + .hex6(HEX6), + .hex7(HEX7), + .gpio(GPIO), + + /* + * Ethernet: 1000BASE-T RGMII + */ + .phy0_rx_clk(ENET0_RX_CLK), + .phy0_rxd(ENET0_RX_DATA), + .phy0_rx_ctl(ENET0_RX_DV), + .phy0_tx_clk(ENET0_GTX_CLK), + .phy0_txd(ENET0_TX_DATA), + .phy0_tx_ctl(ENET0_TX_EN), + .phy0_reset_n(ENET0_RST_N), + .phy0_int_n(ENET0_INT_N), + + .phy1_rx_clk(ENET1_RX_CLK), + .phy1_rxd(ENET1_RX_DATA), + .phy1_rx_ctl(ENET1_RX_DV), + .phy1_tx_clk(ENET1_GTX_CLK), + .phy1_txd(ENET1_TX_DATA), + .phy1_tx_ctl(ENET1_TX_EN), + .phy1_reset_n(ENET1_RST_N), + .phy1_int_n(ENET1_INT_N) +); + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga_core.v b/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga_core.v new file mode 100644 index 000000000..6e50e6b94 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/rtl/fpga_core.v @@ -0,0 +1,675 @@ +/* + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter TARGET = "ALTERA" +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire clk, + input wire clk90, + input wire rst, + + /* + * GPIO + */ + input wire [3:0] btn, + input wire [17:0] sw, + output wire [8:0] ledg, + output wire [17:0] ledr, + output wire [6:0] hex0, + output wire [6:0] hex1, + output wire [6:0] hex2, + output wire [6:0] hex3, + output wire [6:0] hex4, + output wire [6:0] hex5, + output wire [6:0] hex6, + output wire [6:0] hex7, + output wire [35:0] gpio, + + /* + * Ethernet: 1000BASE-T RGMII + */ + input wire phy0_rx_clk, + input wire [3:0] phy0_rxd, + input wire phy0_rx_ctl, + output wire phy0_tx_clk, + output wire [3:0] phy0_txd, + output wire phy0_tx_ctl, + output wire phy0_reset_n, + input wire phy0_int_n, + + input wire phy1_rx_clk, + input wire [3:0] phy1_rxd, + input wire phy1_rx_ctl, + output wire phy1_tx_clk, + output wire [3:0] phy1_txd, + output wire phy1_tx_ctl, + output wire phy1_reset_n, + input wire phy1_int_n +); + +// AXI between MAC and Ethernet modules +wire [7:0] rx_axis_tdata; +wire rx_axis_tvalid; +wire rx_axis_tready; +wire rx_axis_tlast; +wire rx_axis_tuser; + +wire [7:0] tx_axis_tdata; +wire tx_axis_tvalid; +wire tx_axis_tready; +wire tx_axis_tlast; +wire tx_axis_tuser; + +// Ethernet frame between Ethernet modules and UDP stack +wire rx_eth_hdr_ready; +wire rx_eth_hdr_valid; +wire [47:0] rx_eth_dest_mac; +wire [47:0] rx_eth_src_mac; +wire [15:0] rx_eth_type; +wire [7:0] rx_eth_payload_axis_tdata; +wire rx_eth_payload_axis_tvalid; +wire rx_eth_payload_axis_tready; +wire rx_eth_payload_axis_tlast; +wire rx_eth_payload_axis_tuser; + +wire tx_eth_hdr_ready; +wire tx_eth_hdr_valid; +wire [47:0] tx_eth_dest_mac; +wire [47:0] tx_eth_src_mac; +wire [15:0] tx_eth_type; +wire [7:0] tx_eth_payload_axis_tdata; +wire tx_eth_payload_axis_tvalid; +wire tx_eth_payload_axis_tready; +wire tx_eth_payload_axis_tlast; +wire tx_eth_payload_axis_tuser; + +// IP frame connections +wire rx_ip_hdr_valid; +wire rx_ip_hdr_ready; +wire [47:0] rx_ip_eth_dest_mac; +wire [47:0] rx_ip_eth_src_mac; +wire [15:0] rx_ip_eth_type; +wire [3:0] rx_ip_version; +wire [3:0] rx_ip_ihl; +wire [5:0] rx_ip_dscp; +wire [1:0] rx_ip_ecn; +wire [15:0] rx_ip_length; +wire [15:0] rx_ip_identification; +wire [2:0] rx_ip_flags; +wire [12:0] rx_ip_fragment_offset; +wire [7:0] rx_ip_ttl; +wire [7:0] rx_ip_protocol; +wire [15:0] rx_ip_header_checksum; +wire [31:0] rx_ip_source_ip; +wire [31:0] rx_ip_dest_ip; +wire [7:0] rx_ip_payload_axis_tdata; +wire rx_ip_payload_axis_tvalid; +wire rx_ip_payload_axis_tready; +wire rx_ip_payload_axis_tlast; +wire rx_ip_payload_axis_tuser; + +wire tx_ip_hdr_valid; +wire tx_ip_hdr_ready; +wire [5:0] tx_ip_dscp; +wire [1:0] tx_ip_ecn; +wire [15:0] tx_ip_length; +wire [7:0] tx_ip_ttl; +wire [7:0] tx_ip_protocol; +wire [31:0] tx_ip_source_ip; +wire [31:0] tx_ip_dest_ip; +wire [7:0] tx_ip_payload_axis_tdata; +wire tx_ip_payload_axis_tvalid; +wire tx_ip_payload_axis_tready; +wire tx_ip_payload_axis_tlast; +wire tx_ip_payload_axis_tuser; + +// UDP frame connections +wire rx_udp_hdr_valid; +wire rx_udp_hdr_ready; +wire [47:0] rx_udp_eth_dest_mac; +wire [47:0] rx_udp_eth_src_mac; +wire [15:0] rx_udp_eth_type; +wire [3:0] rx_udp_ip_version; +wire [3:0] rx_udp_ip_ihl; +wire [5:0] rx_udp_ip_dscp; +wire [1:0] rx_udp_ip_ecn; +wire [15:0] rx_udp_ip_length; +wire [15:0] rx_udp_ip_identification; +wire [2:0] rx_udp_ip_flags; +wire [12:0] rx_udp_ip_fragment_offset; +wire [7:0] rx_udp_ip_ttl; +wire [7:0] rx_udp_ip_protocol; +wire [15:0] rx_udp_ip_header_checksum; +wire [31:0] rx_udp_ip_source_ip; +wire [31:0] rx_udp_ip_dest_ip; +wire [15:0] rx_udp_source_port; +wire [15:0] rx_udp_dest_port; +wire [15:0] rx_udp_length; +wire [15:0] rx_udp_checksum; +wire [7:0] rx_udp_payload_axis_tdata; +wire rx_udp_payload_axis_tvalid; +wire rx_udp_payload_axis_tready; +wire rx_udp_payload_axis_tlast; +wire rx_udp_payload_axis_tuser; + +wire tx_udp_hdr_valid; +wire tx_udp_hdr_ready; +wire [5:0] tx_udp_ip_dscp; +wire [1:0] tx_udp_ip_ecn; +wire [7:0] tx_udp_ip_ttl; +wire [31:0] tx_udp_ip_source_ip; +wire [31:0] tx_udp_ip_dest_ip; +wire [15:0] tx_udp_source_port; +wire [15:0] tx_udp_dest_port; +wire [15:0] tx_udp_length; +wire [15:0] tx_udp_checksum; +wire [7:0] tx_udp_payload_axis_tdata; +wire tx_udp_payload_axis_tvalid; +wire tx_udp_payload_axis_tready; +wire tx_udp_payload_axis_tlast; +wire tx_udp_payload_axis_tuser; + +wire [7:0] rx_fifo_udp_payload_axis_tdata; +wire rx_fifo_udp_payload_axis_tvalid; +wire rx_fifo_udp_payload_axis_tready; +wire rx_fifo_udp_payload_axis_tlast; +wire rx_fifo_udp_payload_axis_tuser; + +wire [7:0] tx_fifo_udp_payload_axis_tdata; +wire tx_fifo_udp_payload_axis_tvalid; +wire tx_fifo_udp_payload_axis_tready; +wire tx_fifo_udp_payload_axis_tlast; +wire tx_fifo_udp_payload_axis_tuser; + +// Configuration +wire [47:0] local_mac = 48'h02_00_00_00_00_00; +wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; +wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; +wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; + +// IP ports not used +assign rx_ip_hdr_ready = 1; +assign rx_ip_payload_axis_tready = 1; + +assign tx_ip_hdr_valid = 0; +assign tx_ip_dscp = 0; +assign tx_ip_ecn = 0; +assign tx_ip_length = 0; +assign tx_ip_ttl = 0; +assign tx_ip_protocol = 0; +assign tx_ip_source_ip = 0; +assign tx_ip_dest_ip = 0; +assign tx_ip_payload_axis_tdata = 0; +assign tx_ip_payload_axis_tvalid = 0; +assign tx_ip_payload_axis_tlast = 0; +assign tx_ip_payload_axis_tuser = 0; + +// Loop back UDP +wire match_cond = rx_udp_dest_port == 1234; +wire no_match = !match_cond; + +reg match_cond_reg = 0; +reg no_match_reg = 0; + +always @(posedge clk) begin + if (rst) begin + match_cond_reg <= 0; + no_match_reg <= 0; + end else begin + if (rx_udp_payload_axis_tvalid) begin + if ((!match_cond_reg && !no_match_reg) || + (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin + match_cond_reg <= match_cond; + no_match_reg <= no_match; + end + end else begin + match_cond_reg <= 0; + no_match_reg <= 0; + end + end +end + +assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; +assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; +assign tx_udp_ip_dscp = 0; +assign tx_udp_ip_ecn = 0; +assign tx_udp_ip_ttl = 64; +assign tx_udp_ip_source_ip = local_ip; +assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; +assign tx_udp_source_port = rx_udp_dest_port; +assign tx_udp_dest_port = rx_udp_source_port; +assign tx_udp_length = rx_udp_length; +assign tx_udp_checksum = 0; + +assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; +assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; +assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; +assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; +assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; + +assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; +assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; +assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; +assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; +assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; + +// Place first payload byte onto LEDs +reg valid_last = 0; +reg [7:0] led_reg = 0; + +always @(posedge clk) begin + if (tx_udp_payload_axis_tvalid) begin + if (!valid_last) begin + led_reg <= tx_udp_payload_axis_tdata; + valid_last <= 1'b1; + end + if (tx_udp_payload_axis_tlast) begin + valid_last <= 1'b0; + end + end + + if (rst) begin + led_reg <= 0; + end +end + +// place dest IP onto 7 segment displays +reg [31:0] dest_ip_reg = 0; + +always @(posedge clk) begin + if (tx_udp_hdr_valid) begin + dest_ip_reg <= tx_udp_ip_dest_ip; + end + + if (rst) begin + dest_ip_reg <= 0; + end +end + +hex_display #( + .INVERT(1) +) +hex_display_0 ( + .in(dest_ip_reg[3:0]), + .enable(1), + .out(hex0) +); + +hex_display #( + .INVERT(1) +) +hex_display_1 ( + .in(dest_ip_reg[7:4]), + .enable(1), + .out(hex1) +); + +hex_display #( + .INVERT(1) +) +hex_display_2 ( + .in(dest_ip_reg[11:8]), + .enable(1), + .out(hex2) +); + +hex_display #( + .INVERT(1) +) +hex_display_3 ( + .in(dest_ip_reg[15:12]), + .enable(1), + .out(hex3) +); + +hex_display #( + .INVERT(1) +) +hex_display_4 ( + .in(dest_ip_reg[19:16]), + .enable(1), + .out(hex4) +); + +hex_display #( + .INVERT(1) +) +hex_display_5 ( + .in(dest_ip_reg[23:20]), + .enable(1), + .out(hex5) +); + +hex_display #( + .INVERT(1) +) +hex_display_6 ( + .in(dest_ip_reg[27:24]), + .enable(1), + .out(hex6) +); + +hex_display #( + .INVERT(1) +) +hex_display_7 ( + .in(dest_ip_reg[31:28]), + .enable(1), + .out(hex7) +); + +//assign led = sw; +assign ledg = led_reg; +assign ledr = sw; +assign phy0_reset_n = ~rst; +assign phy1_reset_n = ~rst; + +assign gpio = 0; + +eth_mac_1g_rgmii_fifo #( + .TARGET(TARGET), + .USE_CLK90("TRUE"), + .ENABLE_PADDING(1), + .MIN_FRAME_LENGTH(64), + .TX_FIFO_DEPTH(4096), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(4096), + .RX_FRAME_FIFO(1) +) +eth_mac_inst ( + .gtx_clk(clk), + .gtx_clk90(clk90), + .gtx_rst(rst), + .logic_clk(clk), + .logic_rst(rst), + + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + .rgmii_rx_clk(phy0_rx_clk), + .rgmii_rxd(phy0_rxd), + .rgmii_rx_ctl(phy0_rx_ctl), + .rgmii_tx_clk(phy0_tx_clk), + .rgmii_txd(phy0_txd), + .rgmii_tx_ctl(phy0_tx_ctl), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + .speed(), + + .ifg_delay(12) +); + +eth_axis_rx +eth_axis_rx_inst ( + .clk(clk), + .rst(rst), + // AXI input + .s_axis_tdata(rx_axis_tdata), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tuser(rx_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(rx_eth_hdr_valid), + .m_eth_hdr_ready(rx_eth_hdr_ready), + .m_eth_dest_mac(rx_eth_dest_mac), + .m_eth_src_mac(rx_eth_src_mac), + .m_eth_type(rx_eth_type), + .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Status signals + .busy(), + .error_header_early_termination() +); + +eth_axis_tx +eth_axis_tx_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(tx_eth_hdr_valid), + .s_eth_hdr_ready(tx_eth_hdr_ready), + .s_eth_dest_mac(tx_eth_dest_mac), + .s_eth_src_mac(tx_eth_src_mac), + .s_eth_type(tx_eth_type), + .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // AXI output + .m_axis_tdata(tx_axis_tdata), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tuser(tx_axis_tuser), + // Status signals + .busy() +); + +udp_complete +udp_complete_inst ( + .clk(clk), + .rst(rst), + // Ethernet frame input + .s_eth_hdr_valid(rx_eth_hdr_valid), + .s_eth_hdr_ready(rx_eth_hdr_ready), + .s_eth_dest_mac(rx_eth_dest_mac), + .s_eth_src_mac(rx_eth_src_mac), + .s_eth_type(rx_eth_type), + .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), + .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), + .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), + .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), + .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), + // Ethernet frame output + .m_eth_hdr_valid(tx_eth_hdr_valid), + .m_eth_hdr_ready(tx_eth_hdr_ready), + .m_eth_dest_mac(tx_eth_dest_mac), + .m_eth_src_mac(tx_eth_src_mac), + .m_eth_type(tx_eth_type), + .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), + .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), + .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), + .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), + .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), + // IP frame input + .s_ip_hdr_valid(tx_ip_hdr_valid), + .s_ip_hdr_ready(tx_ip_hdr_ready), + .s_ip_dscp(tx_ip_dscp), + .s_ip_ecn(tx_ip_ecn), + .s_ip_length(tx_ip_length), + .s_ip_ttl(tx_ip_ttl), + .s_ip_protocol(tx_ip_protocol), + .s_ip_source_ip(tx_ip_source_ip), + .s_ip_dest_ip(tx_ip_dest_ip), + .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), + .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), + .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), + .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), + .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), + // IP frame output + .m_ip_hdr_valid(rx_ip_hdr_valid), + .m_ip_hdr_ready(rx_ip_hdr_ready), + .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), + .m_ip_eth_src_mac(rx_ip_eth_src_mac), + .m_ip_eth_type(rx_ip_eth_type), + .m_ip_version(rx_ip_version), + .m_ip_ihl(rx_ip_ihl), + .m_ip_dscp(rx_ip_dscp), + .m_ip_ecn(rx_ip_ecn), + .m_ip_length(rx_ip_length), + .m_ip_identification(rx_ip_identification), + .m_ip_flags(rx_ip_flags), + .m_ip_fragment_offset(rx_ip_fragment_offset), + .m_ip_ttl(rx_ip_ttl), + .m_ip_protocol(rx_ip_protocol), + .m_ip_header_checksum(rx_ip_header_checksum), + .m_ip_source_ip(rx_ip_source_ip), + .m_ip_dest_ip(rx_ip_dest_ip), + .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), + .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), + .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), + .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), + .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), + // UDP frame input + .s_udp_hdr_valid(tx_udp_hdr_valid), + .s_udp_hdr_ready(tx_udp_hdr_ready), + .s_udp_ip_dscp(tx_udp_ip_dscp), + .s_udp_ip_ecn(tx_udp_ip_ecn), + .s_udp_ip_ttl(tx_udp_ip_ttl), + .s_udp_ip_source_ip(tx_udp_ip_source_ip), + .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), + .s_udp_source_port(tx_udp_source_port), + .s_udp_dest_port(tx_udp_dest_port), + .s_udp_length(tx_udp_length), + .s_udp_checksum(tx_udp_checksum), + .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), + .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), + .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), + .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), + .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), + // UDP frame output + .m_udp_hdr_valid(rx_udp_hdr_valid), + .m_udp_hdr_ready(rx_udp_hdr_ready), + .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), + .m_udp_eth_src_mac(rx_udp_eth_src_mac), + .m_udp_eth_type(rx_udp_eth_type), + .m_udp_ip_version(rx_udp_ip_version), + .m_udp_ip_ihl(rx_udp_ip_ihl), + .m_udp_ip_dscp(rx_udp_ip_dscp), + .m_udp_ip_ecn(rx_udp_ip_ecn), + .m_udp_ip_length(rx_udp_ip_length), + .m_udp_ip_identification(rx_udp_ip_identification), + .m_udp_ip_flags(rx_udp_ip_flags), + .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), + .m_udp_ip_ttl(rx_udp_ip_ttl), + .m_udp_ip_protocol(rx_udp_ip_protocol), + .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), + .m_udp_ip_source_ip(rx_udp_ip_source_ip), + .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), + .m_udp_source_port(rx_udp_source_port), + .m_udp_dest_port(rx_udp_dest_port), + .m_udp_length(rx_udp_length), + .m_udp_checksum(rx_udp_checksum), + .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), + .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), + .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), + .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), + .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), + // Status signals + .ip_rx_busy(), + .ip_tx_busy(), + .udp_rx_busy(), + .udp_tx_busy(), + .ip_rx_error_header_early_termination(), + .ip_rx_error_payload_early_termination(), + .ip_rx_error_invalid_header(), + .ip_rx_error_invalid_checksum(), + .ip_tx_error_payload_early_termination(), + .ip_tx_error_arp_failed(), + .udp_rx_error_header_early_termination(), + .udp_rx_error_payload_early_termination(), + .udp_tx_error_payload_early_termination(), + // Configuration + .local_mac(local_mac), + .local_ip(local_ip), + .gateway_ip(gateway_ip), + .subnet_mask(subnet_mask), + .clear_arp_cache(0) +); + +axis_fifo #( + .DEPTH(8192), + .DATA_WIDTH(8), + .KEEP_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(1), + .FRAME_FIFO(0) +) +udp_payload_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), + .s_axis_tkeep(0), + .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), + .s_axis_tready(rx_fifo_udp_payload_axis_tready), + .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), + .m_axis_tkeep(), + .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), + .m_axis_tready(tx_fifo_udp_payload_axis_tready), + .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/rtl/hex_display.v b/fpga/lib/eth/example/DE2-115/fpga/rtl/hex_display.v new file mode 100644 index 000000000..dddf57de7 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/rtl/hex_display.v @@ -0,0 +1,70 @@ +/* + +Copyright (c) 2020 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * 7 segment display hexadecimal encoding + */ +module hex_display #( + parameter INVERT = 0 +) +( + input wire [3:0] in, + input wire enable, + + output wire [6:0] out +); + +reg [6:0] enc; + +always @* begin + enc <= 7'b0000000; + if (enable) begin + case (in) + 4'h0: enc <= 7'b0111111; + 4'h1: enc <= 7'b0000110; + 4'h2: enc <= 7'b1011011; + 4'h3: enc <= 7'b1001111; + 4'h4: enc <= 7'b1100110; + 4'h5: enc <= 7'b1101101; + 4'h6: enc <= 7'b1111101; + 4'h7: enc <= 7'b0000111; + 4'h8: enc <= 7'b1111111; + 4'h9: enc <= 7'b1101111; + 4'ha: enc <= 7'b1110111; + 4'hb: enc <= 7'b1111100; + 4'hc: enc <= 7'b0111001; + 4'hd: enc <= 7'b1011110; + 4'he: enc <= 7'b1111001; + 4'hf: enc <= 7'b1110001; + endcase + end +end + +assign out = INVERT ? ~enc : enc; + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/rtl/sync_signal.v b/fpga/lib/eth/example/DE2-115/fpga/rtl/sync_signal.v new file mode 100644 index 000000000..b2a8ce3de --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/rtl/sync_signal.v @@ -0,0 +1,58 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/arp_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/arp_ep.py new file mode 120000 index 000000000..7b3d3ed97 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/arp_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/arp_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/axis_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/axis_ep.py new file mode 120000 index 000000000..385bb0300 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/axis_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/axis_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/eth_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/eth_ep.py new file mode 120000 index 000000000..bac19feea --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/eth_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/eth_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/gmii_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/gmii_ep.py new file mode 120000 index 000000000..754166f2f --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/gmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/gmii_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/ip_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/ip_ep.py new file mode 120000 index 000000000..6dfa928a7 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/ip_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/ip_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/rgmii_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/rgmii_ep.py new file mode 120000 index 000000000..986c56280 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/rgmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/rgmii_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.py b/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.py new file mode 100755 index 000000000..af67005d8 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.py @@ -0,0 +1,364 @@ +#!/usr/bin/env python +""" + +Copyright (c) 2015-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +""" + +from myhdl import * +import os + +import eth_ep +import arp_ep +import udp_ep +import rgmii_ep + +module = 'fpga_core' +testbench = 'test_%s' % module + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("../rtl/hex_display.v") +srcs.append("../lib/eth/rtl/iddr.v") +srcs.append("../lib/eth/rtl/oddr.v") +srcs.append("../lib/eth/rtl/ssio_ddr_in.v") +srcs.append("../lib/eth/rtl/ssio_ddr_out.v") +srcs.append("../lib/eth/rtl/rgmii_phy_if.v") +srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v") +srcs.append("../lib/eth/rtl/eth_mac_1g_rgmii.v") +srcs.append("../lib/eth/rtl/eth_mac_1g.v") +srcs.append("../lib/eth/rtl/axis_gmii_rx.v") +srcs.append("../lib/eth/rtl/axis_gmii_tx.v") +srcs.append("../lib/eth/rtl/lfsr.v") +srcs.append("../lib/eth/rtl/eth_axis_rx.v") +srcs.append("../lib/eth/rtl/eth_axis_tx.v") +srcs.append("../lib/eth/rtl/udp_complete.v") +srcs.append("../lib/eth/rtl/udp_checksum_gen.v") +srcs.append("../lib/eth/rtl/udp.v") +srcs.append("../lib/eth/rtl/udp_ip_rx.v") +srcs.append("../lib/eth/rtl/udp_ip_tx.v") +srcs.append("../lib/eth/rtl/ip_complete.v") +srcs.append("../lib/eth/rtl/ip.v") +srcs.append("../lib/eth/rtl/ip_eth_rx.v") +srcs.append("../lib/eth/rtl/ip_eth_tx.v") +srcs.append("../lib/eth/rtl/ip_arb_mux.v") +srcs.append("../lib/eth/rtl/ip_mux.v") +srcs.append("../lib/eth/rtl/arp.v") +srcs.append("../lib/eth/rtl/arp_cache.v") +srcs.append("../lib/eth/rtl/arp_eth_rx.v") +srcs.append("../lib/eth/rtl/arp_eth_tx.v") +srcs.append("../lib/eth/rtl/eth_arb_mux.v") +srcs.append("../lib/eth/rtl/eth_mux.v") +srcs.append("../lib/eth/lib/axis/rtl/arbiter.v") +srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v") +srcs.append("%s.v" % testbench) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) + +def bench(): + + # Parameters + TARGET = "SIM" + + # Inputs + clk = Signal(bool(0)) + clk90 = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + btn = Signal(intbv(0)[4:]) + sw = Signal(intbv(0)[17:]) + phy0_rx_clk = Signal(bool(0)) + phy0_rxd = Signal(intbv(0)[4:]) + phy0_rx_ctl = Signal(bool(0)) + phy0_int_n = Signal(bool(1)) + phy1_rx_clk = Signal(bool(0)) + phy1_rxd = Signal(intbv(0)[4:]) + phy1_rx_ctl = Signal(bool(0)) + phy1_int_n = Signal(bool(1)) + + # Outputs + ledg = Signal(intbv(0)[8:]) + ledr = Signal(intbv(0)[18:]) + hex0 = Signal(intbv(0)[7:]) + hex1 = Signal(intbv(0)[7:]) + hex2 = Signal(intbv(0)[7:]) + hex3 = Signal(intbv(0)[7:]) + hex4 = Signal(intbv(0)[7:]) + hex5 = Signal(intbv(0)[7:]) + hex6 = Signal(intbv(0)[7:]) + hex7 = Signal(intbv(0)[7:]) + gpio = Signal(intbv(0)[36:]) + phy0_tx_clk = Signal(bool(0)) + phy0_txd = Signal(intbv(0)[4:]) + phy0_tx_ctl = Signal(bool(0)) + phy0_reset_n = Signal(bool(0)) + phy1_tx_clk = Signal(bool(0)) + phy1_txd = Signal(intbv(0)[4:]) + phy1_tx_ctl = Signal(bool(0)) + phy1_reset_n = Signal(bool(0)) + + # sources and sinks + mii_select_0 = Signal(bool(0)) + + rgmii_source_0 = rgmii_ep.RGMIISource() + + rgmii_source_0_logic = rgmii_source_0.create_logic( + phy0_rx_clk, + rst, + txd=phy0_rxd, + tx_ctl=phy0_rx_ctl, + mii_select=mii_select_0, + name='rgmii_source_0' + ) + + rgmii_sink_0 = rgmii_ep.RGMIISink() + + rgmii_sink_0_logic = rgmii_sink_0.create_logic( + phy0_tx_clk, + rst, + rxd=phy0_txd, + rx_ctl=phy0_tx_ctl, + mii_select=mii_select_0, + name='rgmii_sink_0' + ) + + mii_select_1 = Signal(bool(0)) + + rgmii_source_1 = rgmii_ep.RGMIISource() + + rgmii_source_1_logic = rgmii_source_1.create_logic( + phy1_rx_clk, + rst, + txd=phy1_rxd, + tx_ctl=phy1_rx_ctl, + mii_select=mii_select_1, + name='rgmii_source_1' + ) + + rgmii_sink_1 = rgmii_ep.RGMIISink() + + rgmii_sink_1_logic = rgmii_sink_1.create_logic( + phy1_tx_clk, + rst, + rxd=phy1_txd, + rx_ctl=phy1_tx_ctl, + mii_select=mii_select_1, + name='rgmii_sink_1' + ) + + # DUT + if os.system(build_cmd): + raise Exception("Error running build command") + + dut = Cosimulation( + "vvp -m myhdl %s.vvp -lxt2" % testbench, + clk=clk, + clk90=clk90, + rst=rst, + current_test=current_test, + + btn=btn, + sw=sw, + ledg=ledg, + ledr=ledr, + hex0=hex0, + hex1=hex1, + hex2=hex2, + hex3=hex3, + hex4=hex4, + hex5=hex5, + hex6=hex6, + hex7=hex7, + gpio=gpio, + + phy0_rx_clk=phy0_rx_clk, + phy0_rxd=phy0_rxd, + phy0_rx_ctl=phy0_rx_ctl, + phy0_tx_clk=phy0_tx_clk, + phy0_txd=phy0_txd, + phy0_tx_ctl=phy0_tx_ctl, + phy0_reset_n=phy0_reset_n, + phy0_int_n=phy0_int_n, + + phy1_rx_clk=phy1_rx_clk, + phy1_rxd=phy1_rxd, + phy1_rx_ctl=phy1_rx_ctl, + phy1_tx_clk=phy1_tx_clk, + phy1_txd=phy1_txd, + phy1_tx_ctl=phy1_tx_ctl, + phy1_reset_n=phy1_reset_n, + phy1_int_n=phy1_int_n + ) + + @always(delay(4)) + def clkgen(): + clk.next = not clk + + @instance + def clkgen2(): + yield delay(4+2) + while True: + clk90.next = not clk90 + yield delay(4) + + rx_clk_hp = Signal(int(4)) + + @instance + def rx_clk_gen(): + while True: + yield delay(int(rx_clk_hp)) + phy0_rx_clk.next = not phy0_rx_clk + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + yield clk.posedge + rst.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + # testbench stimulus + + yield clk.posedge + print("test 1: test UDP RX packet") + current_test.next = 1 + + test_frame = udp_ep.UDPFrame() + test_frame.eth_dest_mac = 0x020000000000 + test_frame.eth_src_mac = 0xDAD1D2D3D4D5 + test_frame.eth_type = 0x0800 + test_frame.ip_version = 4 + test_frame.ip_ihl = 5 + test_frame.ip_dscp = 0 + test_frame.ip_ecn = 0 + test_frame.ip_length = None + test_frame.ip_identification = 0 + test_frame.ip_flags = 2 + test_frame.ip_fragment_offset = 0 + test_frame.ip_ttl = 64 + test_frame.ip_protocol = 0x11 + test_frame.ip_header_checksum = None + test_frame.ip_source_ip = 0xc0a80181 + test_frame.ip_dest_ip = 0xc0a80180 + test_frame.udp_source_port = 5678 + test_frame.udp_dest_port = 1234 + test_frame.payload = bytearray(range(32)) + test_frame.build() + + rgmii_source_0.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data) + + # wait for ARP request packet + while rgmii_sink_0.empty(): + yield clk.posedge + + rx_frame = rgmii_sink_0.recv() + check_eth_frame = eth_ep.EthFrame() + check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) + check_frame = arp_ep.ARPFrame() + check_frame.parse_eth(check_eth_frame) + + print(check_frame) + + assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF + assert check_frame.eth_src_mac == 0x020000000000 + assert check_frame.eth_type == 0x0806 + assert check_frame.arp_htype == 0x0001 + assert check_frame.arp_ptype == 0x0800 + assert check_frame.arp_hlen == 6 + assert check_frame.arp_plen == 4 + assert check_frame.arp_oper == 1 + assert check_frame.arp_sha == 0x020000000000 + assert check_frame.arp_spa == 0xc0a80180 + assert check_frame.arp_tha == 0x000000000000 + assert check_frame.arp_tpa == 0xc0a80181 + + # generate response + arp_frame = arp_ep.ARPFrame() + arp_frame.eth_dest_mac = 0x020000000000 + arp_frame.eth_src_mac = 0xDAD1D2D3D4D5 + arp_frame.eth_type = 0x0806 + arp_frame.arp_htype = 0x0001 + arp_frame.arp_ptype = 0x0800 + arp_frame.arp_hlen = 6 + arp_frame.arp_plen = 4 + arp_frame.arp_oper = 2 + arp_frame.arp_sha = 0xDAD1D2D3D4D5 + arp_frame.arp_spa = 0xc0a80181 + arp_frame.arp_tha = 0x020000000000 + arp_frame.arp_tpa = 0xc0a80180 + + rgmii_source_0.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data) + + while rgmii_sink_0.empty(): + yield clk.posedge + + rx_frame = rgmii_sink_0.recv() + check_eth_frame = eth_ep.EthFrame() + check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) + check_frame = udp_ep.UDPFrame() + check_frame.parse_eth(check_eth_frame) + + print(check_frame) + + assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 + assert check_frame.eth_src_mac == 0x020000000000 + assert check_frame.eth_type == 0x0800 + assert check_frame.ip_version == 4 + assert check_frame.ip_ihl == 5 + assert check_frame.ip_dscp == 0 + assert check_frame.ip_ecn == 0 + assert check_frame.ip_identification == 0 + assert check_frame.ip_flags == 2 + assert check_frame.ip_fragment_offset == 0 + assert check_frame.ip_ttl == 64 + assert check_frame.ip_protocol == 0x11 + assert check_frame.ip_source_ip == 0xc0a80180 + assert check_frame.ip_dest_ip == 0xc0a80181 + assert check_frame.udp_source_port == 1234 + assert check_frame.udp_dest_port == 5678 + assert check_frame.payload.data == bytearray(range(32)) + + assert rgmii_source_0.empty() + assert rgmii_sink_0.empty() + + yield delay(100) + + raise StopSimulation + + return instances() + +def test_bench(): + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.v b/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.v new file mode 100644 index 000000000..6010ac583 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/test_fpga_core.v @@ -0,0 +1,158 @@ +/* + +Copyright (c) 2015-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Testbench for fpga_core + */ +module test_fpga_core; + +// Parameters +parameter TARGET = "SIM"; + +// Inputs +reg clk = 0; +reg clk90 = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg [3:0] btn = 0; +reg [17:0] sw = 0; +reg phy0_rx_clk = 0; +reg [3:0] phy0_rxd = 0; +reg phy0_rx_ctl = 0; +reg phy0_int_n = 1; +reg phy1_rx_clk = 0; +reg [3:0] phy1_rxd = 0; +reg phy1_rx_ctl = 0; +reg phy1_int_n = 1; + +// Outputs +wire [17:0] ledr; +wire [8:0] ledg; +wire [6:0] hex0; +wire [6:0] hex1; +wire [6:0] hex2; +wire [6:0] hex3; +wire [6:0] hex4; +wire [6:0] hex5; +wire [6:0] hex6; +wire [6:0] hex7; +wire [35:0] gpio; +wire phy0_tx_clk; +wire [3:0] phy0_txd; +wire phy0_tx_ctl; +wire phy0_reset_n; +wire phy1_tx_clk; +wire [3:0] phy1_txd; +wire phy1_tx_ctl; +wire phy1_reset_n; + +initial begin + // myhdl integration + $from_myhdl( + clk, + clk90, + rst, + current_test, + btn, + sw, + phy0_rx_clk, + phy0_rxd, + phy0_rx_ctl, + phy0_int_n, + phy1_rx_clk, + phy1_rxd, + phy1_rx_ctl, + phy1_int_n + ); + $to_myhdl( + ledr, + ledg, + hex0, + hex1, + hex2, + hex3, + hex4, + hex5, + hex6, + hex7, + gpio, + phy0_tx_clk, + phy0_txd, + phy0_tx_ctl, + phy0_reset_n, + phy1_tx_clk, + phy1_txd, + phy1_tx_ctl, + phy1_reset_n + ); + + // dump file + $dumpfile("test_fpga_core.lxt"); + $dumpvars(0, test_fpga_core); +end + +fpga_core #( + .TARGET(TARGET) +) +UUT ( + .clk(clk), + .clk90(clk90), + .rst(rst), + .btn(btn), + .sw(sw), + .ledr(ledr), + .ledg(ledg), + .hex0(hex0), + .hex1(hex1), + .hex2(hex2), + .hex3(hex3), + .hex4(hex4), + .hex5(hex5), + .hex6(hex6), + .hex7(hex7), + .gpio(gpio), + .phy0_rx_clk(phy0_rx_clk), + .phy0_rxd(phy0_rxd), + .phy0_rx_ctl(phy0_rx_ctl), + .phy0_tx_clk(phy0_tx_clk), + .phy0_txd(phy0_txd), + .phy0_tx_ctl(phy0_tx_ctl), + .phy0_reset_n(phy0_reset_n), + .phy0_int_n(phy0_int_n), + .phy1_rx_clk(phy1_rx_clk), + .phy1_rxd(phy1_rxd), + .phy1_rx_ctl(phy1_rx_ctl), + .phy1_tx_clk(phy1_tx_clk), + .phy1_txd(phy1_txd), + .phy1_tx_ctl(phy1_tx_ctl), + .phy1_reset_n(phy1_reset_n), + .phy1_int_n(phy1_int_n) +); + +endmodule diff --git a/fpga/lib/eth/example/DE2-115/fpga/tb/udp_ep.py b/fpga/lib/eth/example/DE2-115/fpga/tb/udp_ep.py new file mode 120000 index 000000000..073c5d3c6 --- /dev/null +++ b/fpga/lib/eth/example/DE2-115/fpga/tb/udp_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/udp_ep.py \ No newline at end of file diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk b/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile index 6901574db..30c895374 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile @@ -53,7 +53,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..1273d0be2 --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,22 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTH-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X0Y13 X0Y12} \ + CONFIG.TX_MASTER_CHANNEL {X0Y12} \ + CONFIG.RX_MASTER_CHANNEL {X0Y12} \ + CONFIG.TX_LINE_RATE {10.3125} \ + CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {32} \ + CONFIG.RX_LINE_RATE {10.3125} \ + CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {32} \ + CONFIG.RX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ + CONFIG.ENABLE_OPTIONAL_PORTS {rxpolarity_in txpolarity_in} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index 3380b154b..000000000 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1406 +0,0 @@ - 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false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - kintexu - - - xcku035 - fbva676 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v b/fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v index 275228386..132a54bcd 100644 --- a/fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v +++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/rtl/fpga.v @@ -308,19 +308,19 @@ sync_reset_156mhz_inst ( ); wire [5:0] sfp_1_gt_txheader; -wire [127:0] sfp_1_gt_txdata; +wire [63:0] sfp_1_gt_txdata; wire sfp_1_gt_rxgearboxslip; wire [5:0] sfp_1_gt_rxheader; wire [1:0] sfp_1_gt_rxheadervalid; -wire [127:0] sfp_1_gt_rxdata; +wire [63:0] sfp_1_gt_rxdata; wire [1:0] sfp_1_gt_rxdatavalid; wire [5:0] sfp_2_gt_txheader; -wire [127:0] sfp_2_gt_txdata; +wire [63:0] sfp_2_gt_txdata; wire sfp_2_gt_rxgearboxslip; wire [5:0] sfp_2_gt_rxheader; wire [1:0] sfp_2_gt_rxheadervalid; -wire [127:0] sfp_2_gt_rxdata; +wire [63:0] sfp_2_gt_rxdata; wire [1:0] sfp_2_gt_rxdatavalid; gtwizard_ultrascale_0 @@ -353,7 +353,7 @@ sfp_gth_inst ( .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk2), - .txdata_in({sfp_2_gt_txdata, sfp_1_gt_txdata}), + .gtwiz_userdata_tx_in({sfp_2_gt_txdata, sfp_1_gt_txdata}), .txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}), .txsequence_in({2{7'b0}}), @@ -369,7 +369,7 @@ sfp_gth_inst ( .rxpolarity_in(2'b00), .rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}), - .rxdata_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}), + .gtwiz_userdata_rx_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}), .rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}), .rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}), .rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}), diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc index d21d927e0..cd3965aee 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga.xdc @@ -59,9 +59,9 @@ set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_l set_property -dict {LOC Y17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los] set_property -dict {LOC G14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs] set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs] -set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl] -set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda] -set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda] +#set_property -dict {LOC A10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl] +#set_property -dict {LOC C11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda] +#set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda] # 161.1328125 MHz MGT reference clock create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p] diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile index 1da0103ca..3facc2b92 100644 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/fpga/Makefile @@ -53,7 +53,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..5ba5fdb3b --- /dev/null +++ b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,22 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X0Y13 X0Y12} \ + CONFIG.TX_MASTER_CHANNEL {X0Y12} \ + CONFIG.RX_MASTER_CHANNEL {X0Y12} \ + CONFIG.TX_LINE_RATE {10.3125} \ + CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {10.3125} \ + CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X0Y13 clk0 X0Y12 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ + CONFIG.ENABLE_OPTIONAL_PORTS {rxpolarity_in txpolarity_in} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index cf560103c..000000000 --- a/fpga/lib/eth/example/ExaNIC_X25/fpga_10g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1406 +0,0 @@ - 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false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - kintexuplus - - - xcku3p - ffvb676 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk b/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk +++ b/fpga/lib/eth/example/KC705/fpga_gmii/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk b/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga/Makefile index cf05d17e4..6f8ad6cb9 100644 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/fpga/Makefile @@ -55,9 +55,8 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -#XCI_FILES = ip/gtwizard_0.xci -XCI_FILES = ip/ten_gig_eth_pcs_pma_0.xci -XCI_FILES += ip/ten_gig_eth_pcs_pma_1.xci +IP_TCL_FILES = ip/ten_gig_eth_pcs_pma_0.tcl +IP_TCL_FILES += ip/ten_gig_eth_pcs_pma_1.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl new file mode 100644 index 000000000..d8359592e --- /dev/null +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl @@ -0,0 +1,9 @@ + +create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_0 + +set_property -dict [list \ + CONFIG.MDIO_Management {false} \ + CONFIG.base_kr {BASE-R} \ + CONFIG.SupportLevel {1} \ + CONFIG.DClkRate {125} \ +] [get_ips ten_gig_eth_pcs_pma_0] diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.xci b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.xci deleted file mode 100644 index 70fb9fa95..000000000 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.xci +++ /dev/null @@ -1,202 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ten_gig_eth_pcs_pma_0 - - - 0 - 0 - 0 - 0 - 0 - - - 0 - 0.000 - - - - 0 - 0.000 - - - 100000000 - 0 - 0.000 - 0 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - 0 - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - false - 0 - 0 - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - - 0 - 0.000 - - - - 0 - 0.000 - 0 - ten_gig_eth_pcs_pma_0 - 125 - virtex7 - X0Y0 - 32 - 1 - false - false - false - false - false - false - clk0 - 156 - 10 - ten_gig_eth_pcs_pma_0_gt - ten_gig_eth_pcs_pma_0 - 125 - None - X0Y0 - false - clk0 - 156.25 - 1 - Time_of_day - false - false - false - BASE-R - 64bit - false - false - 10Gig - GTH - virtex7 - - - xc7vx690t - ffg1761 - VERILOG - - MIXED - -3 - - - TRUE - TRUE - IP_Flow - 15 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl new file mode 100644 index 000000000..448e42ac4 --- /dev/null +++ b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl @@ -0,0 +1,9 @@ + +create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_1 + +set_property -dict [list \ + CONFIG.MDIO_Management {false} \ + CONFIG.base_kr {BASE-R} \ + CONFIG.SupportLevel {0} \ + CONFIG.DClkRate {125} \ +] [get_ips ten_gig_eth_pcs_pma_1] diff --git a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.xci b/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.xci deleted file mode 100644 index 1d8e0e1dc..000000000 --- a/fpga/lib/eth/example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.xci +++ /dev/null @@ -1,202 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - ten_gig_eth_pcs_pma_1 - - - 0 - 0 - 0 - 0 - 0 - - - 0 - 0.000 - - - - 0 - 0.000 - - - 100000000 - 0 - 0.000 - 0 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - 0 - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 0 - 0.000 - false - 0 - 0 - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - 0 - - - - 0 - 0.000 - - - - 0 - 0.000 - - 0 - 0.000 - - - - 0 - 0.000 - 0 - ten_gig_eth_pcs_pma_1 - 125 - virtex7 - X0Y0 - 32 - 1 - false - false - false - false - false - false - clk0 - 156 - 10 - ten_gig_eth_pcs_pma_1_gt - ten_gig_eth_pcs_pma_1 - 125 - None - X0Y0 - false - clk0 - 156.25 - 0 - Time_of_day - false - false - false - BASE-R - 64bit - false - false - 10Gig - GTH - virtex7 - - - xc7vx690t - ffg1761 - VERILOG - - MIXED - -3 - - - TRUE - TRUE - IP_Flow - 15 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk b/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk +++ b/fpga/lib/eth/example/NexysVideo/fpga/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU108/fpga_10g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/VCU108/fpga_10g/fpga/Makefile index eb81c8b36..d400e5181 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU108/fpga_10g/fpga/Makefile @@ -62,8 +62,8 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci -XCI_FILES += ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl +IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl new file mode 100644 index 000000000..fa23582a1 --- /dev/null +++ b/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl @@ -0,0 +1,10 @@ + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ +] [get_ips gig_ethernet_pcs_pma_0] diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci b/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci deleted file mode 100644 index 91b324db6..000000000 --- a/fpga/lib/eth/example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci +++ /dev/null @@ -1,360 +0,0 @@ - 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false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexu - - - xcvu095 - ffva2104 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga.v index 5fe635def..654c39b6b 100644 --- a/fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga.v +++ b/fpga/lib/eth/example/VCU108/fpga_10g/rtl/fpga.v @@ -395,35 +395,35 @@ sync_reset_156mhz_inst ( ); wire [5:0] qsfp_gt_txheader_1; -wire [127:0] qsfp_gt_txdata_1; +wire [63:0] qsfp_gt_txdata_1; wire qsfp_gt_rxgearboxslip_1; wire [5:0] qsfp_gt_rxheader_1; wire [1:0] qsfp_gt_rxheadervalid_1; -wire [127:0] qsfp_gt_rxdata_1; +wire [63:0] qsfp_gt_rxdata_1; wire [1:0] qsfp_gt_rxdatavalid_1; wire [5:0] qsfp_gt_txheader_2; -wire [127:0] qsfp_gt_txdata_2; +wire [63:0] qsfp_gt_txdata_2; wire qsfp_gt_rxgearboxslip_2; wire [5:0] qsfp_gt_rxheader_2; wire [1:0] qsfp_gt_rxheadervalid_2; -wire [127:0] qsfp_gt_rxdata_2; +wire [63:0] qsfp_gt_rxdata_2; wire [1:0] qsfp_gt_rxdatavalid_2; wire [5:0] qsfp_gt_txheader_3; -wire [127:0] qsfp_gt_txdata_3; +wire [63:0] qsfp_gt_txdata_3; wire qsfp_gt_rxgearboxslip_3; wire [5:0] qsfp_gt_rxheader_3; wire [1:0] qsfp_gt_rxheadervalid_3; -wire [127:0] qsfp_gt_rxdata_3; +wire [63:0] qsfp_gt_rxdata_3; wire [1:0] qsfp_gt_rxdatavalid_3; wire [5:0] qsfp_gt_txheader_4; -wire [127:0] qsfp_gt_txdata_4; +wire [63:0] qsfp_gt_txdata_4; wire qsfp_gt_rxgearboxslip_4; wire [5:0] qsfp_gt_rxheader_4; wire [1:0] qsfp_gt_rxheadervalid_4; -wire [127:0] qsfp_gt_rxdata_4; +wire [63:0] qsfp_gt_rxdata_4; wire [1:0] qsfp_gt_rxdatavalid_4; gtwizard_ultrascale_0 @@ -456,7 +456,7 @@ qsfp_gty_inst ( .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk), - .txdata_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}), + .gtwiz_userdata_tx_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}), .txheader_in({qsfp_gt_txheader_4, qsfp_gt_txheader_3, qsfp_gt_txheader_2, qsfp_gt_txheader_1}), .txsequence_in({4{1'b0}}), @@ -469,7 +469,7 @@ qsfp_gty_inst ( .gtytxp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}), .rxgearboxslip_in({qsfp_gt_rxgearboxslip_4, qsfp_gt_rxgearboxslip_3, qsfp_gt_rxgearboxslip_2, qsfp_gt_rxgearboxslip_1}), - .rxdata_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}), + .gtwiz_userdata_rx_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}), .rxdatavalid_out({qsfp_gt_rxdatavalid_4, qsfp_gt_rxdatavalid_3, qsfp_gt_rxdatavalid_2, qsfp_gt_rxdatavalid_1}), .rxheader_out({qsfp_gt_rxheader_4, qsfp_gt_rxheader_3, qsfp_gt_rxheader_2, qsfp_gt_rxheader_1}), .rxheadervalid_out({qsfp_gt_rxheadervalid_4, qsfp_gt_rxheadervalid_3, qsfp_gt_rxheadervalid_2, qsfp_gt_rxheadervalid_1}), @@ -623,139 +623,6 @@ qsfp_phy_4_inst ( .rx_high_ber() ); -// // XGMII 10G PHY -// assign qsfp_modsell = 1'b0; -// assign qsfp_resetl = 1'b1; -// assign qsfp_lpmode = 1'b0; - -// wire [63:0] qsfp_txd_1_int; -// wire [7:0] qsfp_txc_1_int; -// wire [63:0] qsfp_rxd_1_int; -// wire [7:0] qsfp_rxc_1_int; -// wire [63:0] qsfp_txd_2_int; -// wire [7:0] qsfp_txc_2_int; -// wire [63:0] qsfp_rxd_2_int = 64'h0707070707070707; -// wire [7:0] qsfp_rxc_2_int = 8'hff; -// wire [63:0] qsfp_txd_3_int; -// wire [7:0] qsfp_txc_3_int; -// wire [63:0] qsfp_rxd_3_int = 64'h0707070707070707; -// wire [7:0] qsfp_rxc_3_int = 8'hff; -// wire [63:0] qsfp_txd_4_int; -// wire [7:0] qsfp_txc_4_int; -// wire [63:0] qsfp_rxd_4_int = 64'h0707070707070707; -// wire [7:0] qsfp_rxc_4_int = 8'hff; - -// wire [535:0] configuration_vector; -// wire [447:0] status_vector; -// wire [7:0] core_status; - -// assign configuration_vector[0] = 1'b0; // PMA Loopback Enable -// assign configuration_vector[14:1] = 0; -// assign configuration_vector[15] = 1'b0; // PMA Reset -// assign configuration_vector[16] = 1'b0; // Global PMD TX Disable -// assign configuration_vector[109:17] = 0; -// assign configuration_vector[110] = 1'b0; // PCS Loopback Enable -// assign configuration_vector[111] = 1'b0; // PCS Reset -// assign configuration_vector[169:112] = 58'd0; // 10GBASE-R Test Pattern Seed A0-3 -// assign configuration_vector[175:170] = 0; -// assign configuration_vector[233:176] = 58'd0; // 10GBASE-R Test Pattern Seed B0-3 -// assign configuration_vector[239:234] = 0; -// assign configuration_vector[240] = 1'b0; // Data Pattern Select -// assign configuration_vector[241] = 1'b0; // Test Pattern Select -// assign configuration_vector[242] = 1'b0; // RX Test Pattern Checking Enable -// assign configuration_vector[243] = 1'b0; // TX Test Pattern Enable -// assign configuration_vector[244] = 1'b0; // PRBS31 TX Test Pattern Enable -// assign configuration_vector[245] = 1'b0; // PRBS31 RX Test Pattern Checking Enable -// assign configuration_vector[383:246] = 0; -// assign configuration_vector[399:384] = 16'h4C4B; // 125 us timer control -// assign configuration_vector[511:400] = 0; -// assign configuration_vector[512] = 1'b0; // Set PMA Link Status -// assign configuration_vector[513] = 1'b0; // Clear PMA/PMD Link Faults -// assign configuration_vector[515:514] = 0; -// assign configuration_vector[516] = 1'b0; // Set PCS Link Status -// assign configuration_vector[517] = 1'b0; // Clear PCS Link Faults -// assign configuration_vector[518] = 1'b0; // Clear 10GBASE-R Status 2 -// assign configuration_vector[519] = 1'b0; // Clear 10GBASE-R Test Pattern Error Counter -// assign configuration_vector[535:520] = 0; - -// wire drp_gnt; -// wire gt_drprdy; -// wire [15:0] gt_drpdo; -// wire gt_drpen; -// wire gt_drpwe; -// wire [15:0] gt_drpaddr; -// wire [15:0] gt_drpdi; - -// ten_gig_eth_pcs_pma_0 -// ten_gig_eth_pcs_pma_inst ( -// .refclk_p(qsfp_mgt_refclk_0_p), -// .refclk_n(qsfp_mgt_refclk_0_n), - -// .dclk(clk_125mhz_int), - -// .coreclk_out(), - -// //.reset(rst_125mhz_int | si570_i2c_init_busy), -// .reset(rst_125mhz_int), - -// .sim_speedup_control(1'b0), - -// .qpll0outclk_out(), -// .qpll0outrefclk_out(), -// .qpll0lock_out(), - -// .rxrecclk_out(), - -// .txusrclk_out(), -// .txusrclk2_out(clk_156mhz_int), - -// .gttxreset_out(), -// .gtrxreset_out(), - -// .txuserrdy_out(), - -// .areset_datapathclk_out(rst_156mhz_int), -// .areset_coreclk_out(), -// .reset_counter_done_out(), - -// .xgmii_txd(qsfp_txd_1_int), -// .xgmii_txc(qsfp_txc_1_int), -// .xgmii_rxd(qsfp_rxd_1_int), -// .xgmii_rxc(qsfp_rxc_1_int), - -// .txp(qsfp_tx1_p), -// .txn(qsfp_tx1_n), -// .rxp(qsfp_rx1_p), -// .rxn(qsfp_rx1_n), - -// .resetdone_out(), -// .signal_detect(1'b1), -// .tx_fault(1'b0), - -// .drp_req(drp_gnt), -// .drp_gnt(drp_gnt), - -// .core_to_gt_drprdy(gt_drprdy), -// .core_to_gt_drpdo(gt_drpdo), -// .core_to_gt_drpen(gt_drpen), -// .core_to_gt_drpwe(gt_drpwe), -// .core_to_gt_drpaddr(gt_drpaddr), -// .core_to_gt_drpdi(gt_drpdi), - -// .gt_drprdy(gt_drprdy), -// .gt_drpdo(gt_drpdo), -// .gt_drpen(gt_drpen), -// .gt_drpwe(gt_drpwe), -// .gt_drpaddr(gt_drpaddr), -// .gt_drpdi(gt_drpdi), - -// .tx_disable(), -// .configuration_vector(configuration_vector), -// .status_vector(status_vector), -// .pma_pmd_type(3'b101), -// .core_status(core_status) -// ); - // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk b/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU108/fpga_1g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/fpga/Makefile b/fpga/lib/eth/example/VCU108/fpga_1g/fpga/Makefile index 4ad9298c2..b0da2b547 100644 --- a/fpga/lib/eth/example/VCU108/fpga_1g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU108/fpga_1g/fpga/Makefile @@ -46,7 +46,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl new file mode 100644 index 000000000..fa23582a1 --- /dev/null +++ b/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl @@ -0,0 +1,10 @@ + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ +] [get_ips gig_ethernet_pcs_pma_0] diff --git a/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci b/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci deleted file mode 100644 index 91b324db6..000000000 --- a/fpga/lib/eth/example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci +++ /dev/null @@ -1,360 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gig_ethernet_pcs_pma_0 - - - 1 - 1 - 1 - 1 - - - - 0 - - - - 0 - - - 0 - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - - - - 0 - - - - 0 - false - 100000000 - - - - 0 - - - - 0 - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - false - false - false - - - - 100000000 - 0 - 0.000 - 0 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - - 100000000 - 0 - 0.000 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - true - 0 - 0 - true - false - DIFF_PAIR_0 - DIFF_PAIR_1 - false - DIFF_PAIR_0 - DIFF_PAIR_1 - virtexu - 0 - gig_ethernet_pcs_pma_0 - 50.0 - false - . - false - false - false - false - virtexu - 17 - 9 - X0Y0 - 7 - 4 - GTH - false - true - false - false - false - false - true - 1 - clk0 - 125 - TXOUTCLK - true - false - gig_ethernet_pcs_pma_0_gt - true - GTHE3 - false - 1 - true - false - false - xcvu095 - false - 1 - false - true - Sync - gig_ethernet_pcs_pma_0 - Custom - 50.0 - TEMAC - Custom - 0 - false - false - false - false - X0Y0 - GTH - false - false - 625 - Custom - false - 1G - 1 - LVDS - 125 - clk0 - TXOUTCLK - DIFF_PAIR_0 - DIFF_PAIR_1 - false - 10_100_1000 - false - SGMII - Include_Shared_Logic_in_Core - Time_of_day - false - DIFF_PAIR_0 - DIFF_PAIR_1 - 1 - false - virtexu - - - xcvu095 - ffva2104 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU118/fpga_10g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile index 0a0d2dccd..20889e818 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_10g/fpga/Makefile @@ -62,8 +62,8 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci -XCI_FILES += ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl +IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl new file mode 100644 index 000000000..1a6f641e8 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl @@ -0,0 +1,13 @@ + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ + CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ + CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ + CONFIG.Tx_In_Upper_Nibble {0} \ +] [get_ips gig_ethernet_pcs_pma_0] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci deleted file mode 100644 index 1e578e860..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.xci +++ /dev/null @@ -1,365 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gig_ethernet_pcs_pma_0 - - - 1 - 1 - 1 - 1 - - - - 0 - - - - 0 - - - 0 - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - - - - 0 - - - - 0 - false - 100000000 - - - - 0 - - - - 0 - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - false - false - false - - - - 100000000 - 0 - 0.000 - 0 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - - 100000000 - 0 - 0.000 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - true - 0 - 0 - true - false - DIFF_PAIR_0 - DIFF_PAIR_1 - false - DIFF_PAIR_2 - DIFF_PAIR_1 - virtexuplus - 0 - gig_ethernet_pcs_pma_0 - 50.0 - false - . - true - false - false - true - virtexuplus - 16 - 10 - X0Y4 - 8 - 5 - GTH - false - true - false - false - false - false - true - 1 - clk0 - 125 - TXOUTCLK - true - false - gig_ethernet_pcs_pma_0_gt - true - GTHE4 - false - 0 - true - false - false - xcvu9p - false - 1 - false - true - Sync - gig_ethernet_pcs_pma_0 - Custom - 50.0 - TEMAC - Custom - 0 - false - false - false - false - X0Y4 - GTH - false - false - 625 - Custom - false - 1G - 1 - LVDS - 125 - clk0 - TXOUTCLK - DIFF_PAIR_0 - DIFF_PAIR_1 - false - 10_100_1000 - false - SGMII - Include_Shared_Logic_in_Core - Time_of_day - false - DIFF_PAIR_2 - DIFF_PAIR_1 - 0 - false - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..84ebe8978 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,21 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X1Y55 X1Y54 X1Y53 X1Y52 X1Y51 X1Y50 X1Y49 X1Y48} \ + CONFIG.TX_MASTER_CHANNEL {X1Y48} \ + CONFIG.RX_MASTER_CHANNEL {X1Y48} \ + CONFIG.TX_LINE_RATE {10.3125} \ + CONFIG.TX_REFCLK_FREQUENCY {156.25} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {10.3125} \ + CONFIG.RX_REFCLK_FREQUENCY {156.25} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 X1Y51 clk0 X1Y50 clk0 X1Y49 clk0 X1Y48 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 X1Y51 clk0 X1Y50 clk0 X1Y49 clk0 X1Y48 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index 31eeac690..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_10g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1409 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gtwizard_ultrascale_0 - - - "000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - 2 - 2578.125 - 0 - 0 - 125 - 67 - 3 - 2 - 0 - 2 - 0 - 0 - 1 - 0 - 1 - 1 - 250 - 0 - 0 - 0 - 0 - 0 - 1 - "00000000" - "00000000" - 1 - 4 - 0 - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - "00000000" - 0 - "00000000" - 1 - 0 - 5000 - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - 0 - "1010000011" - 0 - "0101111100" - 4 - 1 - 64 - 10.3125 - 144 - 1 - 156.2500000 - 4 - 0 - 0x000000000000000000000000000000000000000000000000 - 156.25 - 0 - 0 - 0 - 1 - 1 - 0 - 64 - 156.2500000 - 156.2500000 - 0 - 257.8125 - 0 - 8 - 2 - 0 - 0 - 0 - 156.25 - 0 - 0 - 1 - 4 - 1 - 64 - 10.3125 - 144 - 1 - 156.2500000 - 4 - 0 - 156.25 - 0 - 0 - 1 - 1 - 0 - 64 - 156.2500000 - 156.2500000 - 1 - X1Y55 X1Y54 X1Y53 X1Y52 X1Y51 X1Y50 X1Y49 X1Y48 - gtwizard_ultrascale_0 - 0 - 0 - - 125 - BOTH - 0 - GTY - 2 - 20 - 96 - 1 - gtye4 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 1 - 1 - -1 - -1 - -1 - -1 - 1 - 1 - -1 - 1 - 1 - 1 - -1 - 1 - 1 - 1 - -1 - -1 - -1 - -1 - -1 - 1 - -1 - -1 - -1 - -1 - -1 - -1 - -1 - 1 - 1 - 1 - 1 - 0 - 0 - -1 - -1 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - -1 - -1 - 0 - 0 - -1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 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00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - false - false - false - false - false - false - false - false - 00000000 - DISABLE - false - false - false - false - false - false - false - false - 1 - 00000000 - false - false - false - false - false - false - false - false - 0 - 5000 - ENABLE - 0 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 00000000 - 1 - false - 0000000000 - false - 1010000011 - NONE - false - 0101111100 - true - 0 - AC - 64B66B_ASYNC - true - AUTO - 64 - 6.1862627 - -20 - 10.3125 - X1Y48 - RXPROGDIVCLK - QPLL0 - 200 - 0 - - 156.25 - X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 - OFF - 0 - PROGRAMMABLE - 800 - 64 - 15 - false - 0 - 10.3125 - 257.8125 - 0 - false - QPLL0 - 156.25 - 1 - ENABLE - 64B66B_ASYNC - CUSTOM - true - 64 - 10.3125 - X1Y48 - TXPROGDIVCLK - QPLL0 - 0 - 156.25 - X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 - 64 - false - 1 - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - true - true - false - true - true - true - false - true - true - true - false - false - false - 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false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v index 6d1fd135f..c4da531d5 100644 --- a/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v +++ b/fpga/lib/eth/example/VCU118/fpga_10g/rtl/fpga.v @@ -467,67 +467,67 @@ sync_reset_156mhz_inst ( ); wire [5:0] qsfp1_gt_txheader_1; -wire [127:0] qsfp1_gt_txdata_1; +wire [63:0] qsfp1_gt_txdata_1; wire qsfp1_gt_rxgearboxslip_1; wire [5:0] qsfp1_gt_rxheader_1; wire [1:0] qsfp1_gt_rxheadervalid_1; -wire [127:0] qsfp1_gt_rxdata_1; +wire [63:0] qsfp1_gt_rxdata_1; wire [1:0] qsfp1_gt_rxdatavalid_1; wire [5:0] qsfp1_gt_txheader_2; -wire [127:0] qsfp1_gt_txdata_2; +wire [63:0] qsfp1_gt_txdata_2; wire qsfp1_gt_rxgearboxslip_2; wire [5:0] qsfp1_gt_rxheader_2; wire [1:0] qsfp1_gt_rxheadervalid_2; -wire [127:0] qsfp1_gt_rxdata_2; +wire [63:0] qsfp1_gt_rxdata_2; wire [1:0] qsfp1_gt_rxdatavalid_2; wire [5:0] qsfp1_gt_txheader_3; -wire [127:0] qsfp1_gt_txdata_3; +wire [63:0] qsfp1_gt_txdata_3; wire qsfp1_gt_rxgearboxslip_3; wire [5:0] qsfp1_gt_rxheader_3; wire [1:0] qsfp1_gt_rxheadervalid_3; -wire [127:0] qsfp1_gt_rxdata_3; +wire [63:0] qsfp1_gt_rxdata_3; wire [1:0] qsfp1_gt_rxdatavalid_3; wire [5:0] qsfp1_gt_txheader_4; -wire [127:0] qsfp1_gt_txdata_4; +wire [63:0] qsfp1_gt_txdata_4; wire qsfp1_gt_rxgearboxslip_4; wire [5:0] qsfp1_gt_rxheader_4; wire [1:0] qsfp1_gt_rxheadervalid_4; -wire [127:0] qsfp1_gt_rxdata_4; +wire [63:0] qsfp1_gt_rxdata_4; wire [1:0] qsfp1_gt_rxdatavalid_4; wire [5:0] qsfp2_gt_txheader_1; -wire [127:0] qsfp2_gt_txdata_1; +wire [63:0] qsfp2_gt_txdata_1; wire qsfp2_gt_rxgearboxslip_1; wire [5:0] qsfp2_gt_rxheader_1; wire [1:0] qsfp2_gt_rxheadervalid_1; -wire [127:0] qsfp2_gt_rxdata_1; +wire [63:0] qsfp2_gt_rxdata_1; wire [1:0] qsfp2_gt_rxdatavalid_1; wire [5:0] qsfp2_gt_txheader_2; -wire [127:0] qsfp2_gt_txdata_2; +wire [63:0] qsfp2_gt_txdata_2; wire qsfp2_gt_rxgearboxslip_2; wire [5:0] qsfp2_gt_rxheader_2; wire [1:0] qsfp2_gt_rxheadervalid_2; -wire [127:0] qsfp2_gt_rxdata_2; +wire [63:0] qsfp2_gt_rxdata_2; wire [1:0] qsfp2_gt_rxdatavalid_2; wire [5:0] qsfp2_gt_txheader_3; -wire [127:0] qsfp2_gt_txdata_3; +wire [63:0] qsfp2_gt_txdata_3; wire qsfp2_gt_rxgearboxslip_3; wire [5:0] qsfp2_gt_rxheader_3; wire [1:0] qsfp2_gt_rxheadervalid_3; -wire [127:0] qsfp2_gt_rxdata_3; +wire [63:0] qsfp2_gt_rxdata_3; wire [1:0] qsfp2_gt_rxdatavalid_3; wire [5:0] qsfp2_gt_txheader_4; -wire [127:0] qsfp2_gt_txdata_4; +wire [63:0] qsfp2_gt_txdata_4; wire qsfp2_gt_rxgearboxslip_4; wire [5:0] qsfp2_gt_rxheader_4; wire [1:0] qsfp2_gt_rxheadervalid_4; -wire [127:0] qsfp2_gt_rxdata_4; +wire [63:0] qsfp2_gt_rxdata_4; wire [1:0] qsfp2_gt_rxdatavalid_4; gtwizard_ultrascale_0 @@ -560,7 +560,7 @@ qsfp_gty_inst ( .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk), - .txdata_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), + .gtwiz_userdata_tx_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), .txheader_in({qsfp2_gt_txheader_4, qsfp2_gt_txheader_3, qsfp2_gt_txheader_2, qsfp2_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}), .txsequence_in({8{1'b0}}), @@ -573,7 +573,7 @@ qsfp_gty_inst ( .gtytxp_out({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), .rxgearboxslip_in({qsfp2_gt_rxgearboxslip_4, qsfp2_gt_rxgearboxslip_3, qsfp2_gt_rxgearboxslip_2, qsfp2_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}), - .rxdata_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), + .gtwiz_userdata_rx_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), .rxdatavalid_out({qsfp2_gt_rxdatavalid_4, qsfp2_gt_rxdatavalid_3, qsfp2_gt_rxdatavalid_2, qsfp2_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}), .rxheader_out({qsfp2_gt_rxheader_4, qsfp2_gt_rxheader_3, qsfp2_gt_rxheader_2, qsfp2_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}), .rxheadervalid_out({qsfp2_gt_rxheadervalid_4, qsfp2_gt_rxheadervalid_3, qsfp2_gt_rxheadervalid_2, qsfp2_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}), diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU118/fpga_1g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_1g/fpga/Makefile index cadfab4de..6a22bdae6 100644 --- a/fpga/lib/eth/example/VCU118/fpga_1g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_1g/fpga/Makefile @@ -46,7 +46,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl new file mode 100644 index 000000000..1a6f641e8 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl @@ -0,0 +1,13 @@ + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ + CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ + CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ + CONFIG.Tx_In_Upper_Nibble {0} \ +] [get_ips gig_ethernet_pcs_pma_0] diff --git a/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci b/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci deleted file mode 100644 index 1e578e860..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.xci +++ /dev/null @@ -1,365 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gig_ethernet_pcs_pma_0 - - - 1 - 1 - 1 - 1 - - - - 0 - - - - 0 - - - 0 - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - - - - 0 - - - - 0 - false - 100000000 - - - - 0 - - - - 0 - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - false - false - false - - - - 100000000 - 0 - 0.000 - 0 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - - 100000000 - 0 - 0.000 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - true - 0 - 0 - true - false - DIFF_PAIR_0 - DIFF_PAIR_1 - false - DIFF_PAIR_2 - DIFF_PAIR_1 - virtexuplus - 0 - gig_ethernet_pcs_pma_0 - 50.0 - false - . - true - false - false - true - virtexuplus - 16 - 10 - X0Y4 - 8 - 5 - GTH - false - true - false - false - false - false - true - 1 - clk0 - 125 - TXOUTCLK - true - false - gig_ethernet_pcs_pma_0_gt - true - GTHE4 - false - 0 - true - false - false - xcvu9p - false - 1 - false - true - Sync - gig_ethernet_pcs_pma_0 - Custom - 50.0 - TEMAC - Custom - 0 - false - false - false - false - X0Y4 - GTH - false - false - 625 - Custom - false - 1G - 1 - LVDS - 125 - clk0 - TXOUTCLK - DIFF_PAIR_0 - DIFF_PAIR_1 - false - 10_100_1000 - false - SGMII - Include_Shared_Logic_in_Core - Time_of_day - false - DIFF_PAIR_2 - DIFF_PAIR_1 - 0 - false - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk b/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU118/fpga_25g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile index 0a0d2dccd..20889e818 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU118/fpga_25g/fpga/Makefile @@ -62,8 +62,8 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gig_ethernet_pcs_pma_0.xci -XCI_FILES += ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl +IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.tcl b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.tcl new file mode 100644 index 000000000..1a6f641e8 --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.tcl @@ -0,0 +1,13 @@ + +create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 + +set_property -dict [list \ + CONFIG.Standard {SGMII} \ + CONFIG.Physical_Interface {LVDS} \ + CONFIG.Management_Interface {false} \ + CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ + CONFIG.LvdsRefClk {625} \ + CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ + CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ + CONFIG.Tx_In_Upper_Nibble {0} \ +] [get_ips gig_ethernet_pcs_pma_0] diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.xci b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.xci deleted file mode 100644 index 1e578e860..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.xci +++ /dev/null @@ -1,365 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gig_ethernet_pcs_pma_0 - - - 1 - 1 - 1 - 1 - - - - 0 - - - - 0 - - - 0 - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - - - - 0 - - - - 0 - false - 100000000 - - - - 0 - - - - 0 - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - false - false - false - false - 0 - 0 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - false - false - false - - - - 100000000 - 0 - 0.000 - 0 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - ACTIVE_LOW - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - - 100000000 - 0 - 0.000 - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - - - - 0 - true - 0 - 0 - true - false - DIFF_PAIR_0 - DIFF_PAIR_1 - false - DIFF_PAIR_2 - DIFF_PAIR_1 - virtexuplus - 0 - gig_ethernet_pcs_pma_0 - 50.0 - false - . - true - false - false - true - virtexuplus - 16 - 10 - X0Y4 - 8 - 5 - GTH - false - true - false - false - false - false - true - 1 - clk0 - 125 - TXOUTCLK - true - false - gig_ethernet_pcs_pma_0_gt - true - GTHE4 - false - 0 - true - false - false - xcvu9p - false - 1 - false - true - Sync - gig_ethernet_pcs_pma_0 - Custom - 50.0 - TEMAC - Custom - 0 - false - false - false - false - X0Y4 - GTH - false - false - 625 - Custom - false - 1G - 1 - LVDS - 125 - clk0 - TXOUTCLK - DIFF_PAIR_0 - DIFF_PAIR_1 - false - 10_100_1000 - false - SGMII - Include_Shared_Logic_in_Core - Time_of_day - false - DIFF_PAIR_2 - DIFF_PAIR_1 - 0 - false - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..82d19cd5b --- /dev/null +++ b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X1Y55 X1Y54 X1Y53 X1Y52 X1Y51 X1Y50 X1Y49 X1Y48} \ + CONFIG.TX_MASTER_CHANNEL {X1Y48} \ + CONFIG.RX_MASTER_CHANNEL {X1Y48} \ + CONFIG.TX_LINE_RATE {25.78125} \ + CONFIG.TX_REFCLK_FREQUENCY {156.25} \ + CONFIG.TX_QPLL_FRACN_NUMERATOR {8388608} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {25.78125} \ + CONFIG.RX_REFCLK_FREQUENCY {156.25} \ + CONFIG.RX_QPLL_FRACN_NUMERATOR {8388608} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 X1Y51 clk0 X1Y50 clk0 X1Y49 clk0 X1Y48 clk0} \ + CONFIG.TX_REFCLK_SOURCE {X1Y55 clk0-1 X1Y54 clk0-1 X1Y53 clk0-1 X1Y52 clk0-1 X1Y51 clk0 X1Y50 clk0 X1Y49 clk0 X1Y48 clk0} \ + CONFIG.FREERUN_FREQUENCY {125} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index cbac1c8b2..000000000 --- a/fpga/lib/eth/example/VCU118/fpga_25g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1415 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - gtwizard_ultrascale_0 - - - "000000000000000000000000000000000000000011111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" - 2 - 2578.125 - 0 - 0 - 125 - 67 - 3 - 2 - 0 - 2 - 0 - 0 - 1 - 0 - 1 - 1 - 250 - 0 - 0 - 0 - 0 - 0 - 1 - "00000000" - "00000000" - 1 - 4 - 0 - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - "00000000" - 0 - "00000000" - 1 - 0 - 5000 - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - 0 - "1010000011" - 0 - "0101111100" - 4 - 1 - 64 - 25.78125 - 144 - 1 - 390.6250000 - 4 - 0 - 0x000000000000000000000000000000000000000000000000 - 156.25 - 0 - 0 - 0 - 1 - 1 - 0 - 64 - 390.6250000 - 390.6250000 - 0 - 257.8125 - 0 - 8 - 2 - 0 - 0 - 0 - 390.625 - 0 - 0 - 1 - 4 - 1 - 64 - 25.78125 - 144 - 1 - 390.6250000 - 4 - 0 - 156.25 - 0 - 0 - 1 - 1 - 0 - 64 - 390.6250000 - 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false - true - false - false - false - false - false - false - false - false - false - false - true - false - false - false - false - false - false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v index 4b59a3464..c1f806f64 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga.v @@ -146,9 +146,9 @@ wire clk_125mhz_mmcm_out; wire clk_125mhz_int; wire rst_125mhz_int; -// Internal 156.25 MHz clock -wire clk_156mhz_int; -wire rst_156mhz_int; +// Internal 390.625 MHz clock +wire clk_390mhz_int; +wire rst_390mhz_int; wire mmcm_rst = reset; wire mmcm_locked; @@ -251,8 +251,8 @@ debounce_switch #( .RATE(156000) ) debounce_switch_inst ( - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), + .clk(clk_390mhz_int), + .rst(rst_390mhz_int), .in({btnu, btnl, btnd, @@ -275,7 +275,7 @@ sync_signal #( .N(2) ) sync_signal_inst ( - .clk(clk_156mhz_int), + .clk(clk_390mhz_int), .in({uart_rxd, uart_cts}), .out({uart_rxd_int, uart_cts_int}) ); @@ -419,7 +419,7 @@ BUFG_GT bufg_gt_tx_usrclk_inst ( .O (gt_txusrclk) ); -assign clk_156mhz_int = gt_txusrclk; +assign clk_390mhz_int = gt_txusrclk; always @(posedge gt_txusrclk, posedge gt_tx_reset) begin if (gt_tx_reset) begin @@ -460,74 +460,74 @@ endgenerate sync_reset #( .N(4) ) -sync_reset_156mhz_inst ( - .clk(clk_156mhz_int), +sync_reset_390mhz_inst ( + .clk(clk_390mhz_int), .rst(~gt_reset_tx_done), - .out(rst_156mhz_int) + .out(rst_390mhz_int) ); wire [5:0] qsfp1_gt_txheader_1; -wire [127:0] qsfp1_gt_txdata_1; +wire [63:0] qsfp1_gt_txdata_1; wire qsfp1_gt_rxgearboxslip_1; wire [5:0] qsfp1_gt_rxheader_1; wire [1:0] qsfp1_gt_rxheadervalid_1; -wire [127:0] qsfp1_gt_rxdata_1; +wire [63:0] qsfp1_gt_rxdata_1; wire [1:0] qsfp1_gt_rxdatavalid_1; wire [5:0] qsfp1_gt_txheader_2; -wire [127:0] qsfp1_gt_txdata_2; +wire [63:0] qsfp1_gt_txdata_2; wire qsfp1_gt_rxgearboxslip_2; wire [5:0] qsfp1_gt_rxheader_2; wire [1:0] qsfp1_gt_rxheadervalid_2; -wire [127:0] qsfp1_gt_rxdata_2; +wire [63:0] qsfp1_gt_rxdata_2; wire [1:0] qsfp1_gt_rxdatavalid_2; wire [5:0] qsfp1_gt_txheader_3; -wire [127:0] qsfp1_gt_txdata_3; +wire [63:0] qsfp1_gt_txdata_3; wire qsfp1_gt_rxgearboxslip_3; wire [5:0] qsfp1_gt_rxheader_3; wire [1:0] qsfp1_gt_rxheadervalid_3; -wire [127:0] qsfp1_gt_rxdata_3; +wire [63:0] qsfp1_gt_rxdata_3; wire [1:0] qsfp1_gt_rxdatavalid_3; wire [5:0] qsfp1_gt_txheader_4; -wire [127:0] qsfp1_gt_txdata_4; +wire [63:0] qsfp1_gt_txdata_4; wire qsfp1_gt_rxgearboxslip_4; wire [5:0] qsfp1_gt_rxheader_4; wire [1:0] qsfp1_gt_rxheadervalid_4; -wire [127:0] qsfp1_gt_rxdata_4; +wire [63:0] qsfp1_gt_rxdata_4; wire [1:0] qsfp1_gt_rxdatavalid_4; wire [5:0] qsfp2_gt_txheader_1; -wire [127:0] qsfp2_gt_txdata_1; +wire [63:0] qsfp2_gt_txdata_1; wire qsfp2_gt_rxgearboxslip_1; wire [5:0] qsfp2_gt_rxheader_1; wire [1:0] qsfp2_gt_rxheadervalid_1; -wire [127:0] qsfp2_gt_rxdata_1; +wire [63:0] qsfp2_gt_rxdata_1; wire [1:0] qsfp2_gt_rxdatavalid_1; wire [5:0] qsfp2_gt_txheader_2; -wire [127:0] qsfp2_gt_txdata_2; +wire [63:0] qsfp2_gt_txdata_2; wire qsfp2_gt_rxgearboxslip_2; wire [5:0] qsfp2_gt_rxheader_2; wire [1:0] qsfp2_gt_rxheadervalid_2; -wire [127:0] qsfp2_gt_rxdata_2; +wire [63:0] qsfp2_gt_rxdata_2; wire [1:0] qsfp2_gt_rxdatavalid_2; wire [5:0] qsfp2_gt_txheader_3; -wire [127:0] qsfp2_gt_txdata_3; +wire [63:0] qsfp2_gt_txdata_3; wire qsfp2_gt_rxgearboxslip_3; wire [5:0] qsfp2_gt_rxheader_3; wire [1:0] qsfp2_gt_rxheadervalid_3; -wire [127:0] qsfp2_gt_rxdata_3; +wire [63:0] qsfp2_gt_rxdata_3; wire [1:0] qsfp2_gt_rxdatavalid_3; wire [5:0] qsfp2_gt_txheader_4; -wire [127:0] qsfp2_gt_txdata_4; +wire [63:0] qsfp2_gt_txdata_4; wire qsfp2_gt_rxgearboxslip_4; wire [5:0] qsfp2_gt_rxheader_4; wire [1:0] qsfp2_gt_rxheadervalid_4; -wire [127:0] qsfp2_gt_rxdata_4; +wire [63:0] qsfp2_gt_rxdata_4; wire [1:0] qsfp2_gt_rxdatavalid_4; gtwizard_ultrascale_0 @@ -560,7 +560,7 @@ qsfp_gty_inst ( .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk), - .txdata_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), + .gtwiz_userdata_tx_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), .txheader_in({qsfp2_gt_txheader_4, qsfp2_gt_txheader_3, qsfp2_gt_txheader_2, qsfp2_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}), .txsequence_in({8{1'b0}}), @@ -573,7 +573,7 @@ qsfp_gty_inst ( .gtytxp_out({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), .rxgearboxslip_in({qsfp2_gt_rxgearboxslip_4, qsfp2_gt_rxgearboxslip_3, qsfp2_gt_rxgearboxslip_2, qsfp2_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}), - .rxdata_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), + .gtwiz_userdata_rx_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), .rxdatavalid_out({qsfp2_gt_rxdatavalid_4, qsfp2_gt_rxdatavalid_3, qsfp2_gt_rxdatavalid_2, qsfp2_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}), .rxheader_out({qsfp2_gt_rxheader_4, qsfp2_gt_rxheader_3, qsfp2_gt_rxheader_2, qsfp2_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}), .rxheadervalid_out({qsfp2_gt_rxheadervalid_4, qsfp2_gt_rxheadervalid_3, qsfp2_gt_rxheadervalid_2, qsfp2_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}), @@ -587,8 +587,8 @@ qsfp_gty_inst ( .txprgdivresetdone_out(gt_txprgdivresetdone) ); -assign qsfp1_tx_clk_1_int = clk_156mhz_int; -assign qsfp1_tx_rst_1_int = rst_156mhz_int; +assign qsfp1_tx_clk_1_int = clk_390mhz_int; +assign qsfp1_tx_rst_1_int = rst_390mhz_int; assign qsfp1_rx_clk_1_int = gt_rxusrclk[0]; @@ -625,8 +625,8 @@ qsfp1_phy_1_inst ( .rx_high_ber() ); -assign qsfp1_tx_clk_2_int = clk_156mhz_int; -assign qsfp1_tx_rst_2_int = rst_156mhz_int; +assign qsfp1_tx_clk_2_int = clk_390mhz_int; +assign qsfp1_tx_rst_2_int = rst_390mhz_int; assign qsfp1_rx_clk_2_int = gt_rxusrclk[1]; @@ -663,8 +663,8 @@ qsfp1_phy_2_inst ( .rx_high_ber() ); -assign qsfp1_tx_clk_3_int = clk_156mhz_int; -assign qsfp1_tx_rst_3_int = rst_156mhz_int; +assign qsfp1_tx_clk_3_int = clk_390mhz_int; +assign qsfp1_tx_rst_3_int = rst_390mhz_int; assign qsfp1_rx_clk_3_int = gt_rxusrclk[2]; @@ -701,8 +701,8 @@ qsfp1_phy_3_inst ( .rx_high_ber() ); -assign qsfp1_tx_clk_4_int = clk_156mhz_int; -assign qsfp1_tx_rst_4_int = rst_156mhz_int; +assign qsfp1_tx_clk_4_int = clk_390mhz_int; +assign qsfp1_tx_rst_4_int = rst_390mhz_int; assign qsfp1_rx_clk_4_int = gt_rxusrclk[3]; @@ -739,8 +739,8 @@ qsfp1_phy_4_inst ( .rx_high_ber() ); -assign qsfp2_tx_clk_1_int = clk_156mhz_int; -assign qsfp2_tx_rst_1_int = rst_156mhz_int; +assign qsfp2_tx_clk_1_int = clk_390mhz_int; +assign qsfp2_tx_rst_1_int = rst_390mhz_int; assign qsfp2_rx_clk_1_int = gt_rxusrclk[4]; @@ -777,8 +777,8 @@ qsfp2_phy_1_inst ( .rx_high_ber() ); -assign qsfp2_tx_clk_2_int = clk_156mhz_int; -assign qsfp2_tx_rst_2_int = rst_156mhz_int; +assign qsfp2_tx_clk_2_int = clk_390mhz_int; +assign qsfp2_tx_rst_2_int = rst_390mhz_int; assign qsfp2_rx_clk_2_int = gt_rxusrclk[5]; @@ -815,8 +815,8 @@ qsfp2_phy_2_inst ( .rx_high_ber() ); -assign qsfp2_tx_clk_3_int = clk_156mhz_int; -assign qsfp2_tx_rst_3_int = rst_156mhz_int; +assign qsfp2_tx_clk_3_int = clk_390mhz_int; +assign qsfp2_tx_rst_3_int = rst_390mhz_int; assign qsfp2_rx_clk_3_int = gt_rxusrclk[6]; @@ -853,8 +853,8 @@ qsfp2_phy_3_inst ( .rx_high_ber() ); -assign qsfp2_tx_clk_4_int = clk_156mhz_int; -assign qsfp2_tx_rst_4_int = rst_156mhz_int; +assign qsfp2_tx_clk_4_int = clk_390mhz_int; +assign qsfp2_tx_rst_4_int = rst_390mhz_int; assign qsfp2_rx_clk_4_int = gt_rxusrclk[7]; @@ -1206,11 +1206,11 @@ assign led = sw[0] ? {qsfp2_rx_block_lock_4, qsfp2_rx_block_lock_3, qsfp2_rx_blo fpga_core core_inst ( /* - * Clock: 156.25 MHz + * Clock: 390.625 MHz * Synchronous reset */ - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), + .clk(clk_390mhz_int), + .rst(rst_390mhz_int), /* * GPIO */ diff --git a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga_core.v index efd80d687..3bed964df 100644 --- a/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/lib/eth/example/VCU118/fpga_25g/rtl/fpga_core.v @@ -35,7 +35,7 @@ module fpga_core # ) ( /* - * Clock: 156.25MHz + * Clock: 390.625 MHz * Synchronous reset */ input wire clk, diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk b/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile b/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile index 014a888b6..8eea51831 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/fpga/Makefile @@ -55,7 +55,7 @@ XDC_FILES += lib/eth/lib/axis/syn/axis_async_fifo.tcl XDC_FILES += lib/eth/lib/axis/syn/sync_reset.tcl # IP -XCI_FILES = ip/gtwizard_ultrascale_0.xci +IP_TCL_FILES = ip/gtwizard_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.tcl b/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.tcl new file mode 100644 index 000000000..73e63d46f --- /dev/null +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.tcl @@ -0,0 +1,21 @@ + +create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 + +set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] + +set_property -dict [list \ + CONFIG.CHANNEL_ENABLE {X1Y51 X1Y50 X1Y49 X1Y48 X1Y47 X1Y46 X1Y45 X1Y44} \ + CONFIG.TX_MASTER_CHANNEL {X1Y48} \ + CONFIG.RX_MASTER_CHANNEL {X1Y48} \ + CONFIG.TX_LINE_RATE {10.3125} \ + CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.TX_USER_DATA_WIDTH {64} \ + CONFIG.TX_INT_DATA_WIDTH {64} \ + CONFIG.RX_LINE_RATE {10.3125} \ + CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ + CONFIG.RX_USER_DATA_WIDTH {64} \ + CONFIG.RX_INT_DATA_WIDTH {64} \ + CONFIG.RX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \ + CONFIG.TX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \ + CONFIG.FREERUN_FREQUENCY {125} \ +] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.xci deleted file mode 100644 index 87c2a4eef..000000000 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/ip/gtwizard_ultrascale_0.xci +++ /dev/null @@ -1,1402 +0,0 @@ - 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false - false - false - true - true - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - false - virtexuplus - - - xcvu9p - fsgd2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 6 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v b/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v index 0125162aa..90c75511a 100644 --- a/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v +++ b/fpga/lib/eth/example/VCU1525/fpga_10g/rtl/fpga.v @@ -497,67 +497,67 @@ sync_reset_156mhz_inst ( ); wire [5:0] qsfp0_gt_txheader_1; -wire [127:0] qsfp0_gt_txdata_1; +wire [63:0] qsfp0_gt_txdata_1; wire qsfp0_gt_rxgearboxslip_1; wire [5:0] qsfp0_gt_rxheader_1; wire [1:0] qsfp0_gt_rxheadervalid_1; -wire [127:0] qsfp0_gt_rxdata_1; +wire [63:0] qsfp0_gt_rxdata_1; wire [1:0] qsfp0_gt_rxdatavalid_1; wire [5:0] qsfp0_gt_txheader_2; -wire [127:0] qsfp0_gt_txdata_2; +wire [63:0] qsfp0_gt_txdata_2; wire qsfp0_gt_rxgearboxslip_2; wire [5:0] qsfp0_gt_rxheader_2; wire [1:0] qsfp0_gt_rxheadervalid_2; -wire [127:0] qsfp0_gt_rxdata_2; +wire [63:0] qsfp0_gt_rxdata_2; wire [1:0] qsfp0_gt_rxdatavalid_2; wire [5:0] qsfp0_gt_txheader_3; -wire [127:0] qsfp0_gt_txdata_3; +wire [63:0] qsfp0_gt_txdata_3; wire qsfp0_gt_rxgearboxslip_3; wire [5:0] qsfp0_gt_rxheader_3; wire [1:0] qsfp0_gt_rxheadervalid_3; -wire [127:0] qsfp0_gt_rxdata_3; +wire [63:0] qsfp0_gt_rxdata_3; wire [1:0] qsfp0_gt_rxdatavalid_3; wire [5:0] qsfp0_gt_txheader_4; -wire [127:0] qsfp0_gt_txdata_4; +wire [63:0] qsfp0_gt_txdata_4; wire qsfp0_gt_rxgearboxslip_4; wire [5:0] qsfp0_gt_rxheader_4; wire [1:0] qsfp0_gt_rxheadervalid_4; -wire [127:0] qsfp0_gt_rxdata_4; +wire [63:0] qsfp0_gt_rxdata_4; wire [1:0] qsfp0_gt_rxdatavalid_4; wire [5:0] qsfp1_gt_txheader_1; -wire [127:0] qsfp1_gt_txdata_1; +wire [63:0] qsfp1_gt_txdata_1; wire qsfp1_gt_rxgearboxslip_1; wire [5:0] qsfp1_gt_rxheader_1; wire [1:0] qsfp1_gt_rxheadervalid_1; -wire [127:0] qsfp1_gt_rxdata_1; +wire [63:0] qsfp1_gt_rxdata_1; wire [1:0] qsfp1_gt_rxdatavalid_1; wire [5:0] qsfp1_gt_txheader_2; -wire [127:0] qsfp1_gt_txdata_2; +wire [63:0] qsfp1_gt_txdata_2; wire qsfp1_gt_rxgearboxslip_2; wire [5:0] qsfp1_gt_rxheader_2; wire [1:0] qsfp1_gt_rxheadervalid_2; -wire [127:0] qsfp1_gt_rxdata_2; +wire [63:0] qsfp1_gt_rxdata_2; wire [1:0] qsfp1_gt_rxdatavalid_2; wire [5:0] qsfp1_gt_txheader_3; -wire [127:0] qsfp1_gt_txdata_3; +wire [63:0] qsfp1_gt_txdata_3; wire qsfp1_gt_rxgearboxslip_3; wire [5:0] qsfp1_gt_rxheader_3; wire [1:0] qsfp1_gt_rxheadervalid_3; -wire [127:0] qsfp1_gt_rxdata_3; +wire [63:0] qsfp1_gt_rxdata_3; wire [1:0] qsfp1_gt_rxdatavalid_3; wire [5:0] qsfp1_gt_txheader_4; -wire [127:0] qsfp1_gt_txdata_4; +wire [63:0] qsfp1_gt_txdata_4; wire qsfp1_gt_rxgearboxslip_4; wire [5:0] qsfp1_gt_rxheader_4; wire [1:0] qsfp1_gt_rxheadervalid_4; -wire [127:0] qsfp1_gt_rxdata_4; +wire [63:0] qsfp1_gt_rxdata_4; wire [1:0] qsfp1_gt_rxdatavalid_4; gtwizard_ultrascale_0 @@ -590,7 +590,7 @@ qsfp_gty_inst ( .rxusrclk_in(gt_rxusrclk), .rxusrclk2_in(gt_rxusrclk), - .txdata_in({qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), + .gtwiz_userdata_tx_in({qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), .txheader_in({qsfp0_gt_txheader_4, qsfp0_gt_txheader_3, qsfp0_gt_txheader_2, qsfp0_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}), .txsequence_in({8{1'b0}}), @@ -603,7 +603,7 @@ qsfp_gty_inst ( .gtytxp_out({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), .rxgearboxslip_in({qsfp0_gt_rxgearboxslip_4, qsfp0_gt_rxgearboxslip_3, qsfp0_gt_rxgearboxslip_2, qsfp0_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}), - .rxdata_out({qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), + .gtwiz_userdata_rx_out({qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), .rxdatavalid_out({qsfp0_gt_rxdatavalid_4, qsfp0_gt_rxdatavalid_3, qsfp0_gt_rxdatavalid_2, qsfp0_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}), .rxheader_out({qsfp0_gt_rxheader_4, qsfp0_gt_rxheader_3, qsfp0_gt_rxheader_2, qsfp0_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}), .rxheadervalid_out({qsfp0_gt_rxheadervalid_4, qsfp0_gt_rxheadervalid_3, qsfp0_gt_rxheadervalid_2, qsfp0_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}), diff --git a/fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v b/fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v index d79cfb9f1..7a2be8e1d 100644 --- a/fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v +++ b/fpga/lib/eth/lib/axis/rtl/axis_ram_switch.v @@ -922,7 +922,7 @@ generate end // process commands and issue memory reads - if (cmd_valid_reg && (!ram_rd_en_reg || ram_rd_ack) && ($unsigned(out_fifo_ctrl_wr_ptr_reg - out_fifo_rd_ptr_reg) < 32)) begin + if (cmd_valid_reg && !cmd_status_valid_next && (!ram_rd_en_reg || ram_rd_ack) && ($unsigned(out_fifo_ctrl_wr_ptr_reg - out_fifo_rd_ptr_reg) < 32)) begin // update counters rd_ptr_next[ADDR_WIDTH-1:0] = rd_ptr_reg[ADDR_WIDTH-1:0] + 1; len_next = len_reg - 1; diff --git a/fpga/lib/eth/lib/axis/syn/axis_async_fifo.sdc b/fpga/lib/eth/lib/axis/syn/axis_async_fifo.sdc new file mode 100644 index 000000000..e3a569a4f --- /dev/null +++ b/fpga/lib/eth/lib/axis/syn/axis_async_fifo.sdc @@ -0,0 +1,51 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# AXI stream asynchronous FIFO timing constraints + +proc constrain_axis_async_fifo_inst { inst } { + puts "Inserting timing constraints for axis_async_fifo instance $inst" + + # reset synchronization + set_false_path -from * -to [get_registers "$inst|s_rst_sync*_reg $inst|m_rst_sync*_reg"] + + if {[get_collection_size [get_registers -nowarn "$inst|s_rst_sync2_reg"]]} { + set_max_delay -from [get_registers "$inst|s_rst_sync2_reg"] -to [get_registers "$inst|s_rst_sync3_reg"] 8.000 + } + + if {[get_collection_size [get_registers -nowarn "$inst|m_rst_sync2_reg"]]} { + set_max_delay -from [get_registers "$inst|m_rst_sync2_reg"] -to [get_registers "$inst|m_rst_sync3_reg"] 8.000 + } + + # pointer synchronization + set_max_delay -from [get_registers "$inst|rd_ptr_reg[*] $inst|rd_ptr_gray_reg[*]"] -to [get_registers "$inst|rd_ptr_gray_sync1_reg[*]"] 8.000 + set_max_delay -from [get_registers "$inst|wr_ptr_reg[*] $inst|wr_ptr_gray_reg[*] $inst|wr_ptr_sync_gray_reg[*]"] -to [get_registers "$inst|wr_ptr_gray_sync1_reg[*]"] 8.000 + + # frame FIFO pointer update synchronization + set_max_delay -from [get_registers "$inst|wr_ptr_update_reg"] -to [get_registers "$inst|wr_ptr_update_sync1_reg"] 8.000 + set_max_delay -from [get_registers "$inst|wr_ptr_update_sync3_reg"] -to [get_registers "$inst|wr_ptr_update_ack_sync1_reg"] 8.000 + + # status synchronization + foreach i {overflow bad_frame good_frame} { + if {[get_collection_size [get_registers -nowarn "$inst|${i}_sync*_reg"]]} { + set_max_delay -from [get_registers "$inst|${i}_sync1_reg"] -to [get_registers "$inst|${i}_sync2_reg"] 8.000 + } + } +} diff --git a/fpga/lib/eth/lib/axis/syn/sync_reset.sdc b/fpga/lib/eth/lib/axis/syn/sync_reset.sdc new file mode 100644 index 000000000..fe5c6bf8b --- /dev/null +++ b/fpga/lib/eth/lib/axis/syn/sync_reset.sdc @@ -0,0 +1,28 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# reset synchronizer timing constraints + +proc constrain_sync_reset_inst { inst } { + puts "Inserting timing constraints for sync_reset instance $inst" + + # reset synchronization + set_false_path -from * -to [get_registers "$inst|sync_reg[*]"] +} diff --git a/fpga/lib/eth/rtl/axis_eth_fcs.v b/fpga/lib/eth/rtl/axis_eth_fcs.v index 16e6a193f..e09cd2084 100644 --- a/fpga/lib/eth/rtl/axis_eth_fcs.v +++ b/fpga/lib/eth/rtl/axis_eth_fcs.v @@ -29,69 +29,108 @@ THE SOFTWARE. /* * AXI4-Stream Ethernet FCS Generator */ -module axis_eth_fcs +module axis_eth_fcs # ( - input wire clk, - input wire rst, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + // If disabled, tkeep assumed to be 1'b1 + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8) +) +( + input wire clk, + input wire rst, /* * AXI input */ - input wire [7:0] s_axis_tdata, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire s_axis_tuser, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire s_axis_tuser, /* * FCS output */ - output wire [31:0] output_fcs, - output wire output_fcs_valid + output wire [31:0] output_fcs, + output wire output_fcs_valid ); +// bus width assertions +initial begin + if (KEEP_WIDTH * 8 != DATA_WIDTH) begin + $error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)"); + $finish; + end +end + reg [31:0] crc_state = 32'hFFFFFFFF; reg [31:0] fcs_reg = 32'h00000000; reg fcs_valid_reg = 1'b0; -wire [31:0] crc_next; +wire [31:0] crc_next[KEEP_WIDTH-1:0]; assign s_axis_tready = 1; assign output_fcs = fcs_reg; assign output_fcs_valid = fcs_valid_reg; -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(8), - .STYLE("AUTO") -) -eth_crc_8 ( - .data_in(s_axis_tdata), - .state_in(crc_state), - .data_out(), - .state_out(crc_next) -); +generate + + genvar n; + + for (n = 0; n < KEEP_WIDTH; n = n + 1) begin : crc + + lfsr #( + .LFSR_WIDTH(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_CONFIG("GALOIS"), + .LFSR_FEED_FORWARD(0), + .REVERSE(1), + .DATA_WIDTH(DATA_WIDTH/KEEP_WIDTH*(n+1)), + .STYLE("AUTO") + ) + eth_crc_inst ( + .data_in(s_axis_tdata[DATA_WIDTH/KEEP_WIDTH*(n+1)-1:0]), + .state_in(crc_state), + .data_out(), + .state_out(crc_next[n]) + ); + + end + +endgenerate + +integer i; always @(posedge clk) begin + fcs_valid_reg <= 1'b0; + + if (s_axis_tvalid) begin + crc_state <= crc_next[KEEP_WIDTH-1]; + + if (s_axis_tlast) begin + crc_state <= 32'hFFFFFFFF; + if (KEEP_ENABLE) begin + fcs_reg <= ~crc_next[0]; + for (i = 0; i < KEEP_WIDTH; i = i + 1) begin + if (s_axis_tkeep[i]) begin + fcs_reg <= ~crc_next[i]; + end + end + end else begin + fcs_reg <= ~crc_next[KEEP_WIDTH-1]; + end + fcs_valid_reg <= 1'b1; + end + end + if (rst) begin crc_state <= 32'hFFFFFFFF; - fcs_reg <= 32'h00000000; fcs_valid_reg <= 1'b0; - end else begin - fcs_valid_reg <= 1'b0; - if (s_axis_tvalid) begin - if (s_axis_tlast) begin - crc_state <= 32'hFFFFFFFF; - fcs_reg <= ~crc_next; - fcs_valid_reg <= 1'b1; - end else begin - crc_state <= crc_next; - end - end end end diff --git a/fpga/lib/eth/rtl/axis_eth_fcs_64.v b/fpga/lib/eth/rtl/axis_eth_fcs_64.v deleted file mode 100644 index e2fa4e371..000000000 --- a/fpga/lib/eth/rtl/axis_eth_fcs_64.v +++ /dev/null @@ -1,227 +0,0 @@ -/* - -Copyright (c) 2015-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`timescale 1ns / 1ps - -/* - * AXI4-Stream Ethernet FCS Generator (64 bit datapath) - */ -module axis_eth_fcs_64 -( - input wire clk, - input wire rst, - - /* - * AXI input - */ - input wire [63:0] s_axis_tdata, - input wire [7:0] s_axis_tkeep, - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire s_axis_tlast, - input wire s_axis_tuser, - - /* - * FCS output - */ - output wire [31:0] output_fcs, - output wire output_fcs_valid -); - -reg [31:0] crc_state = 32'hFFFFFFFF; -reg [31:0] fcs_reg = 32'h00000000; -reg fcs_valid_reg = 1'b0; - -wire [31:0] crc_next0; -wire [31:0] crc_next1; -wire [31:0] crc_next2; -wire [31:0] crc_next3; -wire [31:0] crc_next4; -wire [31:0] crc_next5; -wire [31:0] crc_next6; -wire [31:0] crc_next7; - -assign s_axis_tready = 1'b1; -assign output_fcs = fcs_reg; -assign output_fcs_valid = fcs_valid_reg; - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(8), - .STYLE("AUTO") -) -eth_crc_8 ( - .data_in(s_axis_tdata[7:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next0) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(16), - .STYLE("AUTO") -) -eth_crc_16 ( - .data_in(s_axis_tdata[15:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next1) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(24), - .STYLE("AUTO") -) -eth_crc_24 ( - .data_in(s_axis_tdata[23:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next2) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(32), - .STYLE("AUTO") -) -eth_crc_32 ( - .data_in(s_axis_tdata[31:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next3) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(40), - .STYLE("AUTO") -) -eth_crc_40 ( - .data_in(s_axis_tdata[39:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next4) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(48), - .STYLE("AUTO") -) -eth_crc_48 ( - .data_in(s_axis_tdata[47:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next5) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(56), - .STYLE("AUTO") -) -eth_crc_56 ( - .data_in(s_axis_tdata[55:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next6) -); - -lfsr #( - .LFSR_WIDTH(32), - .LFSR_POLY(32'h4c11db7), - .LFSR_CONFIG("GALOIS"), - .LFSR_FEED_FORWARD(0), - .REVERSE(1), - .DATA_WIDTH(64), - .STYLE("AUTO") -) -eth_crc_64 ( - .data_in(s_axis_tdata[63:0]), - .state_in(crc_state), - .data_out(), - .state_out(crc_next7) -); - -always @(posedge clk) begin - if (rst) begin - crc_state <= 32'hFFFFFFFF; - fcs_reg <= 1'b0; - fcs_valid_reg <= 1'b0; - end else begin - fcs_valid_reg <= 1'b0; - if (s_axis_tvalid) begin - if (s_axis_tlast) begin - crc_state <= 32'hFFFFFFFF; - case (s_axis_tkeep) - 8'b00000001: fcs_reg <= ~crc_next0; - 8'b00000011: fcs_reg <= ~crc_next1; - 8'b00000111: fcs_reg <= ~crc_next2; - 8'b00001111: fcs_reg <= ~crc_next3; - 8'b00011111: fcs_reg <= ~crc_next4; - 8'b00111111: fcs_reg <= ~crc_next5; - 8'b01111111: fcs_reg <= ~crc_next6; - 8'b11111111: fcs_reg <= ~crc_next7; - endcase - fcs_valid_reg <= 1'b1; - end else begin - crc_state <= crc_next7; - end - end - end -end - -endmodule diff --git a/fpga/lib/eth/rtl/eth_arb_mux.v b/fpga/lib/eth/rtl/eth_arb_mux.v index 8e5784f39..8aa662646 100644 --- a/fpga/lib/eth/rtl/eth_arb_mux.v +++ b/fpga/lib/eth/rtl/eth_arb_mux.v @@ -89,7 +89,7 @@ parameter CL_S_COUNT = $clog2(S_COUNT); reg frame_reg = 1'b0, frame_next; -reg s_eth_hdr_ready_mask_reg = 1'b0, s_eth_hdr_ready_mask_next; +reg [S_COUNT-1:0] s_eth_hdr_ready_reg = {S_COUNT{1'b0}}, s_eth_hdr_ready_next; reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next; reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next; @@ -113,7 +113,7 @@ reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int; reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int; wire m_eth_payload_axis_tready_int_early; -assign s_eth_hdr_ready = (!s_eth_hdr_ready_mask_reg && grant_valid) << grant_encoded; +assign s_eth_hdr_ready = s_eth_hdr_ready_reg; assign s_eth_payload_axis_tready = (m_eth_payload_axis_tready_int_reg && grant_valid) << grant_encoded; @@ -155,7 +155,7 @@ assign acknowledge = grant & s_eth_payload_axis_tvalid & s_eth_payload_axis_trea always @* begin frame_next = frame_reg; - s_eth_hdr_ready_mask_next = s_eth_hdr_ready_mask_reg; + s_eth_hdr_ready_next = {S_COUNT{1'b0}}; m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready; m_eth_dest_mac_next = m_eth_dest_mac_reg; @@ -166,15 +166,14 @@ always @* begin // end of frame detection if (s_eth_payload_axis_tlast[grant_encoded]) begin frame_next = 1'b0; - s_eth_hdr_ready_mask_next = 1'b0; end end - if (!frame_reg && grant_valid) begin + if (!frame_reg && grant_valid && (m_eth_hdr_ready || !m_eth_hdr_valid)) begin // start of frame frame_next = 1'b1; - s_eth_hdr_ready_mask_next = 1'b1; + s_eth_hdr_ready_next = grant; m_eth_hdr_valid_next = 1'b1; m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48]; @@ -193,19 +192,20 @@ always @* begin end always @(posedge clk) begin - if (rst) begin - frame_reg <= 1'b0; - s_eth_hdr_ready_mask_reg <= 1'b0; - m_eth_hdr_valid_reg <= 1'b0; - end else begin - frame_reg <= frame_next; - s_eth_hdr_ready_mask_reg <= s_eth_hdr_ready_mask_next; - m_eth_hdr_valid_reg <= m_eth_hdr_valid_next; - end + frame_reg <= frame_next; + s_eth_hdr_ready_reg <= s_eth_hdr_ready_next; + + m_eth_hdr_valid_reg <= m_eth_hdr_valid_next; m_eth_dest_mac_reg <= m_eth_dest_mac_next; m_eth_src_mac_reg <= m_eth_src_mac_next; m_eth_type_reg <= m_eth_type_next; + + if (rst) begin + frame_reg <= 1'b0; + s_eth_hdr_ready_reg <= {S_COUNT{1'b0}}; + m_eth_hdr_valid_reg <= 1'b0; + end end // output datapath logic diff --git a/fpga/lib/eth/rtl/eth_mac_1g_fifo.v b/fpga/lib/eth/rtl/eth_mac_1g_fifo.v index 0110bbdd1..ab20e7782 100644 --- a/fpga/lib/eth/rtl/eth_mac_1g_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_1g_fifo.v @@ -276,11 +276,11 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .FRAME_FIFO(TX_FRAME_FIFO), + .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(TX_DROP_BAD_FRAME), - .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) + .DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( // AXI input diff --git a/fpga/lib/eth/rtl/eth_mac_1g_gmii_fifo.v b/fpga/lib/eth/rtl/eth_mac_1g_gmii_fifo.v index 845aad575..f627beeb6 100644 --- a/fpga/lib/eth/rtl/eth_mac_1g_gmii_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_1g_gmii_fifo.v @@ -303,11 +303,11 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .FRAME_FIFO(TX_FRAME_FIFO), + .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(TX_DROP_BAD_FRAME), - .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) + .DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( // AXI input diff --git a/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v b/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v index 640dbe624..d54428dc9 100644 --- a/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v @@ -302,11 +302,11 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .FRAME_FIFO(TX_FRAME_FIFO), + .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(TX_DROP_BAD_FRAME), - .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) + .DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( // AXI input diff --git a/fpga/lib/eth/rtl/eth_mac_mii_fifo.v b/fpga/lib/eth/rtl/eth_mac_mii_fifo.v index 5f33c240c..e63f00adf 100644 --- a/fpga/lib/eth/rtl/eth_mac_mii_fifo.v +++ b/fpga/lib/eth/rtl/eth_mac_mii_fifo.v @@ -280,11 +280,11 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .FRAME_FIFO(TX_FRAME_FIFO), + .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(TX_DROP_BAD_FRAME), - .DROP_WHEN_FULL(TX_DROP_WHEN_FULL) + .DROP_BAD_FRAME(RX_DROP_BAD_FRAME), + .DROP_WHEN_FULL(RX_DROP_WHEN_FULL) ) rx_fifo ( // AXI input diff --git a/fpga/lib/eth/rtl/ip_arb_mux.v b/fpga/lib/eth/rtl/ip_arb_mux.v index 7e99ece31..ec88c5262 100644 --- a/fpga/lib/eth/rtl/ip_arb_mux.v +++ b/fpga/lib/eth/rtl/ip_arb_mux.v @@ -115,7 +115,7 @@ parameter CL_S_COUNT = $clog2(S_COUNT); reg frame_reg = 1'b0, frame_next; -reg s_ip_hdr_ready_mask_reg = 1'b0, s_ip_hdr_ready_mask_next; +reg [S_COUNT-1:0] s_ip_hdr_ready_reg = {S_COUNT{1'b0}}, s_ip_hdr_ready_next; reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next; reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next; @@ -152,7 +152,7 @@ reg [DEST_WIDTH-1:0] m_ip_payload_axis_tdest_int; reg [USER_WIDTH-1:0] m_ip_payload_axis_tuser_int; wire m_ip_payload_axis_tready_int_early; -assign s_ip_hdr_ready = (!s_ip_hdr_ready_mask_reg && grant_valid) << grant_encoded; +assign s_ip_hdr_ready = s_ip_hdr_ready_reg; assign s_ip_payload_axis_tready = (m_ip_payload_axis_tready_int_reg && grant_valid) << grant_encoded; @@ -207,7 +207,7 @@ assign acknowledge = grant & s_ip_payload_axis_tvalid & s_ip_payload_axis_tready always @* begin frame_next = frame_reg; - s_ip_hdr_ready_mask_next = s_ip_hdr_ready_mask_reg; + s_ip_hdr_ready_next = {S_COUNT{1'b0}}; m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready; m_eth_dest_mac_next = m_eth_dest_mac_reg; @@ -231,15 +231,14 @@ always @* begin // end of frame detection if (s_ip_payload_axis_tlast[grant_encoded]) begin frame_next = 1'b0; - s_ip_hdr_ready_mask_next = 1'b0; end end - if (!frame_reg && grant_valid) begin + if (!frame_reg && grant_valid && (m_ip_hdr_ready || !m_ip_hdr_valid)) begin // start of frame frame_next = 1'b1; - s_ip_hdr_ready_mask_next = 1'b1; + s_ip_hdr_ready_next = grant; m_ip_hdr_valid_next = 1'b1; m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48]; @@ -271,16 +270,11 @@ always @* begin end always @(posedge clk) begin - if (rst) begin - frame_reg <= 1'b0; - s_ip_hdr_ready_mask_reg <= 1'b0; - m_ip_hdr_valid_reg <= 1'b0; - end else begin - frame_reg <= frame_next; - s_ip_hdr_ready_mask_reg <= s_ip_hdr_ready_mask_next; - m_ip_hdr_valid_reg <= m_ip_hdr_valid_next; - end + frame_reg <= frame_next; + s_ip_hdr_ready_reg <= s_ip_hdr_ready_next; + + m_ip_hdr_valid_reg <= m_ip_hdr_valid_next; m_eth_dest_mac_reg <= m_eth_dest_mac_next; m_eth_src_mac_reg <= m_eth_src_mac_next; m_eth_type_reg <= m_eth_type_next; @@ -297,6 +291,12 @@ always @(posedge clk) begin m_ip_header_checksum_reg <= m_ip_header_checksum_next; m_ip_source_ip_reg <= m_ip_source_ip_next; m_ip_dest_ip_reg <= m_ip_dest_ip_next; + + if (rst) begin + frame_reg <= 1'b0; + s_ip_hdr_ready_reg <= {S_COUNT{1'b0}}; + m_ip_hdr_valid_reg <= 1'b0; + end end // output datapath logic diff --git a/fpga/lib/eth/rtl/udp_arb_mux.v b/fpga/lib/eth/rtl/udp_arb_mux.v index 2969b1b4d..9b285ee97 100644 --- a/fpga/lib/eth/rtl/udp_arb_mux.v +++ b/fpga/lib/eth/rtl/udp_arb_mux.v @@ -123,7 +123,7 @@ parameter CL_S_COUNT = $clog2(S_COUNT); reg frame_reg = 1'b0, frame_next; -reg s_udp_hdr_ready_mask_reg = 1'b0, s_udp_hdr_ready_mask_next; +reg [S_COUNT-1:0] s_udp_hdr_ready_reg = {S_COUNT{1'b0}}, s_udp_hdr_ready_next; reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next; reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next; @@ -164,7 +164,7 @@ reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_int; reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_int; wire m_udp_payload_axis_tready_int_early; -assign s_udp_hdr_ready = (!s_udp_hdr_ready_mask_reg && grant_valid) << grant_encoded; +assign s_udp_hdr_ready = s_udp_hdr_ready_reg; assign s_udp_payload_axis_tready = (m_udp_payload_axis_tready_int_reg && grant_valid) << grant_encoded; @@ -223,7 +223,7 @@ assign acknowledge = grant & s_udp_payload_axis_tvalid & s_udp_payload_axis_trea always @* begin frame_next = frame_reg; - s_udp_hdr_ready_mask_next = s_udp_hdr_ready_mask_reg; + s_udp_hdr_ready_next = {S_COUNT{1'b0}}; m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready; m_eth_dest_mac_next = m_eth_dest_mac_reg; @@ -251,15 +251,14 @@ always @* begin // end of frame detection if (s_udp_payload_axis_tlast[grant_encoded]) begin frame_next = 1'b0; - s_udp_hdr_ready_mask_next = 1'b0; end end - if (!frame_reg && grant_valid) begin + if (!frame_reg && grant_valid && (m_udp_hdr_ready || !m_udp_hdr_valid)) begin // start of frame frame_next = 1'b1; - s_udp_hdr_ready_mask_next = 1'b1; + s_udp_hdr_ready_next = grant; m_udp_hdr_valid_next = 1'b1; m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48]; @@ -295,16 +294,11 @@ always @* begin end always @(posedge clk) begin - if (rst) begin - frame_reg <= 1'b0; - s_udp_hdr_ready_mask_reg <= 1'b0; - m_udp_hdr_valid_reg <= 1'b0; - end else begin - frame_reg <= frame_next; - s_udp_hdr_ready_mask_reg <= s_udp_hdr_ready_mask_next; - m_udp_hdr_valid_reg <= m_udp_hdr_valid_next; - end + frame_reg <= frame_next; + s_udp_hdr_ready_reg <= s_udp_hdr_ready_next; + + m_udp_hdr_valid_reg <= m_udp_hdr_valid_next; m_eth_dest_mac_reg <= m_eth_dest_mac_next; m_eth_src_mac_reg <= m_eth_src_mac_next; m_eth_type_reg <= m_eth_type_next; @@ -325,6 +319,12 @@ always @(posedge clk) begin m_udp_dest_port_reg <= m_udp_dest_port_next; m_udp_length_reg <= m_udp_length_next; m_udp_checksum_reg <= m_udp_checksum_next; + + if (rst) begin + frame_reg <= 1'b0; + s_udp_hdr_ready_reg <= {S_COUNT{1'b0}}; + m_udp_hdr_valid_reg <= 1'b0; + end end // output datapath logic diff --git a/fpga/lib/eth/syn/eth_mac_1g_gmii.sdc b/fpga/lib/eth/syn/eth_mac_1g_gmii.sdc new file mode 100644 index 000000000..13b94b711 --- /dev/null +++ b/fpga/lib/eth/syn/eth_mac_1g_gmii.sdc @@ -0,0 +1,34 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# GMII Gigabit Ethernet MAC timing constraints + +proc constrain_eth_mac_1g_gmii_inst { inst } { + puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst" + + # MII select sync + set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] 8.000 + set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] 8.000 + + # RX prescale sync + set_max_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] 8.000 + + constrain_gmii_phy_if_inst "$inst|gmii_phy_if_inst" +} diff --git a/fpga/lib/eth/syn/eth_mac_1g_rgmii.sdc b/fpga/lib/eth/syn/eth_mac_1g_rgmii.sdc new file mode 100644 index 000000000..ed77accaf --- /dev/null +++ b/fpga/lib/eth/syn/eth_mac_1g_rgmii.sdc @@ -0,0 +1,34 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# RGMII Gigabit Ethernet MAC timing constraints + +proc constrain_eth_mac_1g_rgmii_inst { inst } { + puts "Inserting timing constraints for eth_mac_1g_rgmii instance $inst" + + # MII select sync + set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] 8.000 + set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] 8.000 + + # RX prescale sync + set_max_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] 8.000 + + constrain_rgmii_phy_if_inst "$inst|rgmii_phy_if_inst" +} diff --git a/fpga/lib/eth/syn/gmii_phy_if.sdc b/fpga/lib/eth/syn/gmii_phy_if.sdc new file mode 100644 index 000000000..d3bb04f75 --- /dev/null +++ b/fpga/lib/eth/syn/gmii_phy_if.sdc @@ -0,0 +1,28 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# GMII PHY IF timing constraints + +proc constrain_gmii_phy_if_inst { inst } { + puts "Inserting timing constraints for gmii_phy_if instance $inst" + + # reset synchronization + set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] +} diff --git a/fpga/lib/eth/syn/mii_phy_if.sdc b/fpga/lib/eth/syn/mii_phy_if.sdc new file mode 100644 index 000000000..8be4570c3 --- /dev/null +++ b/fpga/lib/eth/syn/mii_phy_if.sdc @@ -0,0 +1,28 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# MII PHY IF timing constraints + +proc constrain_mii_phy_if_inst { inst } { + puts "Inserting timing constraints for mii_phy_if instance $inst" + + # reset synchronization + set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] +} diff --git a/fpga/lib/eth/syn/rgmii_io.sdc b/fpga/lib/eth/syn/rgmii_io.sdc new file mode 100644 index 000000000..9cd04ec52 --- /dev/null +++ b/fpga/lib/eth/syn/rgmii_io.sdc @@ -0,0 +1,148 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# RGMII IO timing constraints + +proc constrain_rgmii_input_pins { name clk_pin data_pins } { + puts "Inserting timing constraints for RGMII input pins $name" + puts "RGMII clock pin: $clk_pin" + puts "RGMII data pins: $data_pins" + + #Virtual clock has no phase shift + create_clock -name "virt_${name}_rx_clk_125m" -period 8.000 + # create_clock -name "virt_${name}_rx_clk_25m" -period 40.000 + # create_clock -name "virt_${name}_rx_clk_2m5" -period 400.000 + + #input clock has 90 degree phase shift + create_clock -name "${name}_rx_clk_125m" -period 8.000 "$clk_pin" -waveform {2 6} + # create_clock -name "${name}_rx_clk_25m" -period 40.000 "$clk_pin" -waveform {10 30} -add + # create_clock -name "${name}_rx_clk_2m5" -period 400.000 "$clk_pin" -waveform {100 300} -add + + ## Constraint the path to the rising/falling edge of the phy clock + ## setup time: 2ns-0.75ns=1.25ns, 0.75ns skew, + ## hold time: 0.75ns skew, 2-1.5-0.75=-0.25ns + ## clock edge is 1.5 ns delay with data + set_input_delay -add_delay -clock "virt_${name}_rx_clk_125m" -max 1.25 [get_ports "$data_pins"] + set_input_delay -add_delay -clock "virt_${name}_rx_clk_125m" -min -0.25 [get_ports "$data_pins"] + set_input_delay -add_delay -clock "virt_${name}_rx_clk_125m" -clock_fall -max 1.25 [get_ports "$data_pins"] + set_input_delay -add_delay -clock "virt_${name}_rx_clk_125m" -clock_fall -min -0.25 [get_ports "$data_pins"] + + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_25m" -max 1.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_25m" -min -0.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_25m" -clock_fall -max 1.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_25m" -clock_fall -min -0.25 [get_ports "$data_pins"] + + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_2m5" -max 1.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_2m5" -min -0.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_2m5" -clock_fall -max 1.25 [get_ports "$data_pins"] + # set_input_delay -add_delay -clock "virt_${name}_rx_clk_2m5" -clock_fall -min -0.25 [get_ports "$data_pins"] + + # set_clock_groups \ + # -exclusive \ + # -group [get_clocks "${name}_rx_clk_125m"] \ + # -group [get_clocks "${name}_rx_clk_25m"] \ + # -group [get_clocks "${name}_rx_clk_2m5"] + + # set_clock_groups \ + # -exclusive \ + # -group "virt_${name}_rx_clk_125m ${name}_rx_clk_125m" \ + # -group "virt_${name}_rx_clk_25m ${name}_rx_clk_25m" \ + # -group "virt_${name}_rx_clk_2m5 ${name}_rx_clk_2m5" + + ##setup time, set false path, rise-->fall, fall-->rise + set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_125m"] -fall_to [get_clocks "${name}_rx_clk_125m"] -setup + set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_125m"] -rise_to [get_clocks "${name}_rx_clk_125m"] -setup + + # set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_25m"] -fall_to [get_clocks "${name}_rx_clk_25m"] -setup + # set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_25m"] -rise_to [get_clocks "${name}_rx_clk_25m"] -setup + + # set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_2m5"] -fall_to [get_clocks "${name}_rx_clk_2m5"] -setup + # set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_2m5"] -rise_to [get_clocks "${name}_rx_clk_2m5"] -setup + + + ##hold time, set false path, rise-->rise, fall-->fall + set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_125m"] -rise_to [get_clocks "${name}_rx_clk_125m"] -hold + set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_125m"] -fall_to [get_clocks "${name}_rx_clk_125m"] -hold + + # set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_25m"] -rise_to [get_clocks "${name}_rx_clk_25m"] -hold + # set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_25m"] -fall_to [get_clocks "${name}_rx_clk_25m"] -hold + + # set_false_path -rise_from [get_clocks "virt_${name}_rx_clk_2m5"] -rise_to [get_clocks "${name}_rx_clk_2m5"] -hold + # set_false_path -fall_from [get_clocks "virt_${name}_rx_clk_2m5"] -fall_to [get_clocks "${name}_rx_clk_2m5"] -hold +} + +proc constrain_rgmii_output_pins { name clk_src clk_pin data_pins } { + puts "Inserting timing constraints for RGMII output pins $name" + puts "RGMII clock source: $clk_src" + puts "RGMII clock pin: $clk_pin" + puts "RGMII data pins: $data_pins" + + ##1ns setup time and 1ns hold time + ## + create_generated_clock -name "${name}_tx_clk_125m" -source [get_pins "$clk_src"] [get_ports "$clk_pin"] + # create_generated_clock -name "${name}_tx_clk_25m" -source [get_pins "$clk_src"] [get_ports "$clk_pin"] -divide_by 5 -add + # create_generated_clock -name "${name}_tx_clk_2m5" -source [get_pins "$clk_src"] [get_ports "$clk_pin"] -divide_by 50 -add + + set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_125m"] -max 1 [get_ports "$data_pins"] + set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_125m"] -min -1 [get_ports "$data_pins"] + set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_125m"] -max 1 -clock_fall [get_ports "$data_pins"] + set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_125m"] -min -1 -clock_fall [get_ports "$data_pins"] + + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_25m"] -max 1 [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_25m"] -min -1 [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_25m"] -max 1 -clock_fall [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_25m"] -min -1 -clock_fall [get_ports "$data_pins"] + + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_2m5"] -max 1 [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_2m5"] -min -1 [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_2m5"] -max 1 -clock_fall [get_ports "$data_pins"] + #set_output_delay -add_delay -clock [get_clocks "${name}_tx_clk_2m5"] -min -1 -clock_fall [get_ports "$data_pins"] + + #set_clock_groups \ + # -exclusive \ + # -group {get_clocks "$clk_src" "${name}_tx_clk_125m"} \ + # -group {get_clocks "$clk_src" "${name}_tx_clk_25m"} \ + # -group {get_clocks "$clk_src" "${name}_tx_clk_2m5"} + + # set_clock_groups \ + # -exclusive \ + # -group [get_clocks "$clk_src" "${name}_tx_clk_125m"] + + ##setup time, set false path, rise-->fall, fall-->rise + set_false_path -rise_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_125m"] -setup + set_false_path -fall_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_125m"] -setup + + #set_false_path -rise_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_25m"] -setup + #set_false_path -fall_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_25m"] -setup + + #set_false_path -rise_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_2m5"] -setup + #set_false_path -fall_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_2m5"] -setup + + + ##hold time, set false path, rise-->rise, fall-->fall + set_false_path -rise_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_125m"] -hold + set_false_path -fall_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_125m"] -hold + + #set_false_path -rise_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_25m"] -hold + #set_false_path -fall_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_25m"] -hold + + #set_false_path -rise_from [get_clocks "$clk_src"] -rise_to [get_clocks "${name}_tx_clk_2m5"] -hold + #set_false_path -fall_from [get_clocks "$clk_src"] -fall_to [get_clocks "${name}_tx_clk_2m5"] -hold +} diff --git a/fpga/lib/eth/syn/rgmii_phy_if.sdc b/fpga/lib/eth/syn/rgmii_phy_if.sdc new file mode 100644 index 000000000..e08b478b2 --- /dev/null +++ b/fpga/lib/eth/syn/rgmii_phy_if.sdc @@ -0,0 +1,32 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# RGMII PHY IF timing constraints + +proc constrain_rgmii_phy_if_inst { inst } { + puts "Inserting timing constraints for rgmii_phy_if instance $inst" + + # reset synchronization + set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] + + # clock output + # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_1"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 + # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_2"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 +} diff --git a/fpga/lib/eth/tb/test_axis_eth_fcs.py b/fpga/lib/eth/tb/test_axis_eth_fcs.py index 15fe19ba8..104234627 100755 --- a/fpga/lib/eth/tb/test_axis_eth_fcs.py +++ b/fpga/lib/eth/tb/test_axis_eth_fcs.py @@ -45,14 +45,17 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): # Parameters - + DATA_WIDTH = 8 + KEEP_ENABLE = (DATA_WIDTH>8) + KEEP_WIDTH = int(DATA_WIDTH/8) # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - s_axis_tdata = Signal(intbv(0)[8:]) + s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) + s_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:]) s_axis_tvalid = Signal(bool(0)) s_axis_tlast = Signal(bool(0)) s_axis_tuser = Signal(bool(0)) @@ -71,6 +74,7 @@ def bench(): clk, rst, tdata=s_axis_tdata, + tkeep=s_axis_tkeep, tvalid=s_axis_tvalid, tready=s_axis_tready, tlast=s_axis_tlast, @@ -90,6 +94,7 @@ def bench(): current_test=current_test, s_axis_tdata=s_axis_tdata, + s_axis_tkeep=s_axis_tkeep, s_axis_tvalid=s_axis_tvalid, s_axis_tready=s_axis_tready, s_axis_tlast=s_axis_tlast, diff --git a/fpga/lib/eth/tb/test_axis_eth_fcs.v b/fpga/lib/eth/tb/test_axis_eth_fcs.v index 785ab4e3f..7099ab233 100644 --- a/fpga/lib/eth/tb/test_axis_eth_fcs.v +++ b/fpga/lib/eth/tb/test_axis_eth_fcs.v @@ -32,13 +32,17 @@ THE SOFTWARE. module test_axis_eth_fcs; // Parameters +parameter DATA_WIDTH = 8; +parameter KEEP_ENABLE = (DATA_WIDTH>8); +parameter KEEP_WIDTH = (DATA_WIDTH/8); // Inputs reg clk = 0; reg rst = 0; reg [7:0] current_test = 0; -reg [7:0] s_axis_tdata = 0; +reg [DATA_WIDTH-1:0] s_axis_tdata = 0; +reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0; reg s_axis_tvalid = 0; reg s_axis_tlast = 0; reg s_axis_tuser = 0; @@ -55,6 +59,7 @@ initial begin rst, current_test, s_axis_tdata, + s_axis_tkeep, s_axis_tvalid, s_axis_tlast, s_axis_tuser @@ -70,11 +75,16 @@ initial begin $dumpvars(0, test_axis_eth_fcs); end -axis_eth_fcs +axis_eth_fcs #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH) +) UUT ( .clk(clk), .rst(rst), .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), .s_axis_tvalid(s_axis_tvalid), .s_axis_tready(s_axis_tready), .s_axis_tlast(s_axis_tlast), diff --git a/fpga/lib/eth/tb/test_axis_eth_fcs_64.py b/fpga/lib/eth/tb/test_axis_eth_fcs_64.py index c592dab04..5eef3f12c 100755 --- a/fpga/lib/eth/tb/test_axis_eth_fcs_64.py +++ b/fpga/lib/eth/tb/test_axis_eth_fcs_64.py @@ -29,8 +29,8 @@ import os import axis_ep import eth_ep -module = 'axis_eth_fcs_64' -testbench = 'test_%s' % module +module = 'axis_eth_fcs' +testbench = 'test_%s_64' % module srcs = [] @@ -45,15 +45,17 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) def bench(): # Parameters - + DATA_WIDTH = 64 + KEEP_ENABLE = (DATA_WIDTH>8) + KEEP_WIDTH = int(DATA_WIDTH/8) # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) - s_axis_tdata = Signal(intbv(0)[64:]) - s_axis_tkeep = Signal(intbv(0)[8:]) + s_axis_tdata = Signal(intbv(0)[DATA_WIDTH:]) + s_axis_tkeep = Signal(intbv(1)[KEEP_WIDTH:]) s_axis_tvalid = Signal(bool(0)) s_axis_tlast = Signal(bool(0)) s_axis_tuser = Signal(bool(0)) diff --git a/fpga/lib/eth/tb/test_axis_eth_fcs_64.v b/fpga/lib/eth/tb/test_axis_eth_fcs_64.v index 1d137b1fe..0faf33b82 100644 --- a/fpga/lib/eth/tb/test_axis_eth_fcs_64.v +++ b/fpga/lib/eth/tb/test_axis_eth_fcs_64.v @@ -27,11 +27,14 @@ THE SOFTWARE. `timescale 1ns / 1ps /* - * Testbench for axis_eth_fcs_64 + * Testbench for axis_eth_fcs */ module test_axis_eth_fcs_64; // Parameters +parameter DATA_WIDTH = 64; +parameter KEEP_ENABLE = (DATA_WIDTH>8); +parameter KEEP_WIDTH = (DATA_WIDTH/8); // Inputs reg clk = 0; @@ -72,7 +75,11 @@ initial begin $dumpvars(0, test_axis_eth_fcs_64); end -axis_eth_fcs_64 +axis_eth_fcs #( + .DATA_WIDTH(DATA_WIDTH), + .KEEP_ENABLE(KEEP_ENABLE), + .KEEP_WIDTH(KEEP_WIDTH) +) UUT ( .clk(clk), .rst(rst),