Minor reorganization

rtl/axis_demux.py

@@ -132,7 +132,12 @@ module {{name}} #
     input  wire [{{w-1}}:0]             select
 );
 
-// // internal datapath
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+
+// internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg                  output_axis_tvalid_int;
 reg                  output_axis_tready_int = 0;
@@ -140,10 +145,6 @@ reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
 
-reg [{{w-1}}:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-
-reg input_axis_tready_reg = 0, input_axis_tready_next;
 assign input_axis_tready = input_axis_tready_reg;
 
 // mux for output control signals

rtl/axis_demux_4.v

@@ -79,7 +79,12 @@ module axis_demux_4 #
     input  wire [1:0]             select
 );
 
-// // internal datapath
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+
+// internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg                  output_axis_tvalid_int;
 reg                  output_axis_tready_int = 0;
@@ -87,10 +92,6 @@ reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
 
-reg [1:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-
-reg input_axis_tready_reg = 0, input_axis_tready_next;
 assign input_axis_tready = input_axis_tready_reg;
 
 // mux for output control signals

rtl/axis_demux_64.py

@@ -135,7 +135,12 @@ module {{name}} #
     input  wire [{{w-1}}:0]             select
 );
 
-// // internal datapath
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+
+// internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
 reg                  output_axis_tvalid_int;
@@ -144,10 +149,6 @@ reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
 
-reg [{{w-1}}:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-
-reg input_axis_tready_reg = 0, input_axis_tready_next;
 assign input_axis_tready = input_axis_tready_reg;
 
 // mux for output control signals

rtl/axis_demux_64_4.v

@@ -85,7 +85,12 @@ module axis_demux_64_4 #
     input  wire [1:0]             select
 );
 
-// // internal datapath
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_axis_tready_reg = 0, input_axis_tready_next;
+
+// internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
 reg                  output_axis_tvalid_int;
@@ -94,10 +99,6 @@ reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
 
-reg [1:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-
-reg input_axis_tready_reg = 0, input_axis_tready_next;
 assign input_axis_tready = input_axis_tready_reg;
 
 // mux for output control signals

rtl/axis_mux.py

@@ -132,6 +132,12 @@ module {{name}} #
     input  wire [{{w-1}}:0]             select
 );
 
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+{% for p in ports %}
+reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
+{%- endfor %}
+
 // internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg                  output_axis_tvalid_int;
@@ -139,12 +145,6 @@ reg                  output_axis_tready_int = 0;
 reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
-
-reg [{{w-1}}:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-{% for p in ports %}
-reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
-{%- endfor %}
 {% for p in ports %}
 assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
 {%- endfor %}

rtl/axis_mux_4.v

@@ -79,14 +79,6 @@ module axis_mux_4 #
     input  wire [1:0]             select
 );
 
-// internal datapath
-reg [DATA_WIDTH-1:0] output_axis_tdata_int;
-reg                  output_axis_tvalid_int;
-reg                  output_axis_tready_int = 0;
-reg                  output_axis_tlast_int;
-reg                  output_axis_tuser_int;
-wire                 output_axis_tready_int_early;
-
 reg [1:0] select_reg = 0, select_next;
 reg frame_reg = 0, frame_next;
 
@@ -95,6 +87,14 @@ reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
 reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
 reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
 
+// internal datapath
+reg [DATA_WIDTH-1:0] output_axis_tdata_int;
+reg                  output_axis_tvalid_int;
+reg                  output_axis_tready_int = 0;
+reg                  output_axis_tlast_int;
+reg                  output_axis_tuser_int;
+wire                 output_axis_tready_int_early;
+
 assign input_0_axis_tready = input_0_axis_tready_reg;
 assign input_1_axis_tready = input_1_axis_tready_reg;
 assign input_2_axis_tready = input_2_axis_tready_reg;

rtl/axis_mux_64.py

@@ -135,6 +135,12 @@ module {{name}} #
     input  wire [{{w-1}}:0]             select
 );
 
+reg [{{w-1}}:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+{% for p in ports %}
+reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
+{%- endfor %}
+
 // internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
@@ -143,12 +149,6 @@ reg                  output_axis_tready_int = 0;
 reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
-
-reg [{{w-1}}:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-{% for p in ports %}
-reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
-{%- endfor %}
 {% for p in ports %}
 assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
 {%- endfor %}

rtl/axis_mux_64_4.v

@@ -85,6 +85,14 @@ module axis_mux_64_4 #
     input  wire [1:0]             select
 );
 
+reg [1:0] select_reg = 0, select_next;
+reg frame_reg = 0, frame_next;
+
+reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
+reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
+reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
+reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
+
 // internal datapath
 reg [DATA_WIDTH-1:0] output_axis_tdata_int;
 reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
@@ -94,14 +102,6 @@ reg                  output_axis_tlast_int;
 reg                  output_axis_tuser_int;
 wire                 output_axis_tready_int_early;
 
-reg [1:0] select_reg = 0, select_next;
-reg frame_reg = 0, frame_next;
-
-reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
-reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
-reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
-reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
-
 assign input_0_axis_tready = input_0_axis_tready_reg;
 assign input_1_axis_tready = input_1_axis_tready_reg;
 assign input_2_axis_tready = input_2_axis_tready_reg;