From 7d2f77a30b990df0888fdf3e66e61c3d25bd299d Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Mon, 17 Jul 2023 18:44:42 -0700
Subject: [PATCH] fpga/common: Connect xcvr_ctrl_rst to QPLLs

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 fpga/common/rtl/cmac_gty_ch_wrapper.v         | 19 +++++++++++++++++++
 .../common/rtl/eth_xcvr_phy_10g_gty_wrapper.v | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/fpga/common/rtl/cmac_gty_ch_wrapper.v b/fpga/common/rtl/cmac_gty_ch_wrapper.v
index de2822510..d26b072f8 100644
--- a/fpga/common/rtl/cmac_gty_ch_wrapper.v
+++ b/fpga/common/rtl/cmac_gty_ch_wrapper.v
@@ -152,6 +152,17 @@ wire gt_rxprbslocked;
 
 wire [15:0] gt_dmonitorout;
 
+wire common_reset_in_int;
+
+sync_reset #(
+    .N(4)
+)
+sync_reset_common_reset_inst (
+    .clk(drp_clk),
+    .rst(drp_rst || xcvr_ctrl_rst),
+    .out(common_reset_in_int)
+);
+
 // QPLL0 reset and power down
 reg qpll0_reset_drp_reg = 1'b0;
 reg qpll0_reset_reg = 1'b1;
@@ -174,6 +185,10 @@ always @(posedge drp_clk) begin
         qpll0_reset_counter_reg <= 0;
     end
 
+    if (common_reset_in_int) begin
+        qpll0_reset_counter_reg <= 0;
+    end
+
     if (drp_rst) begin
         qpll0_reset_reg <= 1'b1;
         qpll0_pd_reg <= QPLL0_PD;
@@ -210,6 +225,10 @@ always @(posedge drp_clk) begin
         qpll1_reset_counter_reg <= 0;
     end
 
+    if (common_reset_in_int) begin
+        qpll1_reset_counter_reg <= 0;
+    end
+
     if (drp_rst) begin
         qpll1_reset_reg <= 1'b1;
         qpll1_pd_reg <= QPLL1_PD;
diff --git a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
index fe35e2d7d..e23a101eb 100644
--- a/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
+++ b/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
@@ -212,6 +212,17 @@ always @(posedge drp_clk) begin
     phy_rx_status_sync_2_reg <= phy_rx_status_sync_1_reg;
 end
 
+wire common_reset_in_int;
+
+sync_reset #(
+    .N(4)
+)
+sync_reset_common_reset_inst (
+    .clk(drp_clk),
+    .rst(drp_rst || xcvr_ctrl_rst),
+    .out(common_reset_in_int)
+);
+
 // QPLL0 reset and power down
 reg qpll0_reset_drp_reg = 1'b0;
 reg qpll0_reset_reg = 1'b1;
@@ -234,6 +245,10 @@ always @(posedge drp_clk) begin
         qpll0_reset_counter_reg <= 0;
     end
 
+    if (common_reset_in_int) begin
+        qpll0_reset_counter_reg <= 0;
+    end
+
     if (drp_rst) begin
         qpll0_reset_reg <= 1'b1;
         qpll0_pd_reg <= QPLL0_PD;
@@ -270,6 +285,10 @@ always @(posedge drp_clk) begin
         qpll1_reset_counter_reg <= 0;
     end
 
+    if (common_reset_in_int) begin
+        qpll1_reset_counter_reg <= 0;
+    end
+
     if (drp_rst) begin
         qpll1_reset_reg <= 1'b1;
         qpll1_pd_reg <= QPLL1_PD;