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fpga/common: Connect xcvr_ctrl_rst to QPLLs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-17 18:44:42 -07:00
parent a99815800b
commit 7d2f77a30b
2 changed files with 38 additions and 0 deletions
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19
fpga/common/rtl/cmac_gty_ch_wrapper.v
View File

@ -152,6 +152,17 @@ wire gt_rxprbslocked;
wire [15:0] gt_dmonitorout; wire [15:0] gt_dmonitorout;
wire common_reset_in_int;
sync_reset #(
.N(4)
)
sync_reset_common_reset_inst (
.clk(drp_clk),
.rst(drp_rst || xcvr_ctrl_rst),
.out(common_reset_in_int)
);
// QPLL0 reset and power down // QPLL0 reset and power down
reg qpll0_reset_drp_reg = 1'b0; reg qpll0_reset_drp_reg = 1'b0;
reg qpll0_reset_reg = 1'b1; reg qpll0_reset_reg = 1'b1;
@ -174,6 +185,10 @@ always @(posedge drp_clk) begin
qpll0_reset_counter_reg <= 0; qpll0_reset_counter_reg <= 0;
end end
if (common_reset_in_int) begin
qpll0_reset_counter_reg <= 0;
end
if (drp_rst) begin if (drp_rst) begin
qpll0_reset_reg <= 1'b1; qpll0_reset_reg <= 1'b1;
qpll0_pd_reg <= QPLL0_PD; qpll0_pd_reg <= QPLL0_PD;
@ -210,6 +225,10 @@ always @(posedge drp_clk) begin
qpll1_reset_counter_reg <= 0; qpll1_reset_counter_reg <= 0;
end end
if (common_reset_in_int) begin
qpll1_reset_counter_reg <= 0;
end
if (drp_rst) begin if (drp_rst) begin
qpll1_reset_reg <= 1'b1; qpll1_reset_reg <= 1'b1;
qpll1_pd_reg <= QPLL1_PD; qpll1_pd_reg <= QPLL1_PD;

19
fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
View File

@ -212,6 +212,17 @@ always @(posedge drp_clk) begin
phy_rx_status_sync_2_reg <= phy_rx_status_sync_1_reg; phy_rx_status_sync_2_reg <= phy_rx_status_sync_1_reg;
end end
wire common_reset_in_int;
sync_reset #(
.N(4)
)
sync_reset_common_reset_inst (
.clk(drp_clk),
.rst(drp_rst || xcvr_ctrl_rst),
.out(common_reset_in_int)
);
// QPLL0 reset and power down // QPLL0 reset and power down
reg qpll0_reset_drp_reg = 1'b0; reg qpll0_reset_drp_reg = 1'b0;
reg qpll0_reset_reg = 1'b1; reg qpll0_reset_reg = 1'b1;
@ -234,6 +245,10 @@ always @(posedge drp_clk) begin
qpll0_reset_counter_reg <= 0; qpll0_reset_counter_reg <= 0;
end end
if (common_reset_in_int) begin
qpll0_reset_counter_reg <= 0;
end
if (drp_rst) begin if (drp_rst) begin
qpll0_reset_reg <= 1'b1; qpll0_reset_reg <= 1'b1;
qpll0_pd_reg <= QPLL0_PD; qpll0_pd_reg <= QPLL0_PD;
@ -270,6 +285,10 @@ always @(posedge drp_clk) begin
qpll1_reset_counter_reg <= 0; qpll1_reset_counter_reg <= 0;
end end
if (common_reset_in_int) begin
qpll1_reset_counter_reg <= 0;
end
if (drp_rst) begin if (drp_rst) begin
qpll1_reset_reg <= 1'b1; qpll1_reset_reg <= 1'b1;
qpll1_pd_reg <= QPLL1_PD; qpll1_pd_reg <= QPLL1_PD;