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Code Issues Projects Releases Wiki Activity

Update example designs

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This commit is contained in:
Alex Forencich 2018-10-30 21:32:32 -07:00
parent 6ffdc5f53d
commit 7d6889add6
40 changed files with 456 additions and 3891 deletions
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2
example/ATLYS/fpga/fpga/Makefile
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@ -47,7 +47,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

44
example/ATLYS/fpga/rtl/fpga_core.v
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@ -317,7 +317,9 @@ eth_mac_1g_gmii_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
@ -550,31 +552,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/ATLYS/fpga/tb/test_fpga_core.py
View File

@ -70,7 +70,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/DE5-Net/fpga/fpga/Makefile
View File

@ -41,7 +41,7 @@ SYN_FILES += lib/eth/rtl/xgmii_deinterleave.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += cores/phy/phy.qip
SYN_FILES += cores/phy_reconfig/phy_reconfig.qip

44
example/DE5-Net/fpga/rtl/fpga_core.v
View File

@ -336,7 +336,9 @@ eth_mac_10g_fifo #(
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_ADDR_WIDTH(9)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(clk),
@ -578,31 +580,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(rx_fifo_udp_payload_tkeep),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(tx_fifo_udp_payload_tkeep),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/DE5-Net/fpga/tb/test_fpga_core.py
View File

@ -64,7 +64,7 @@ srcs.append("../lib/eth/rtl/eth_mux_64_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/HXT100G/fpga/fpga/Makefile
View File

@ -44,7 +44,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_64_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

44
example/HXT100G/fpga/rtl/fpga_core.v
View File

@ -480,7 +480,9 @@ eth_mac_10g_fifo #(
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_ADDR_WIDTH(9)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(clk),
@ -722,31 +724,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(rx_fifo_udp_payload_tkeep),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(tx_fifo_udp_payload_tkeep),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/HXT100G/fpga/tb/test_fpga_core.py
View File

@ -64,7 +64,7 @@ srcs.append("../lib/eth/rtl/eth_mux_64_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

4
example/HXT100G/fpga_cxpt16/fpga/Makefile
View File

@ -17,7 +17,6 @@ SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/i2c_master.v
SYN_FILES += rtl/gth_i2c_init.v
SYN_FILES += rtl/eth_gth_phy_quad.v
SYN_FILES += rtl/axis_crosspoint_16x16.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
@ -25,7 +24,8 @@ SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_crosspoint.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6/ten_gig_eth_pcs_pma_v2_6/example_design/ten_gig_eth_pcs_pma_v2_6_management_arbiter.v
SYN_FILES += coregen/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper/ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper_quad.v

3334
example/HXT100G/fpga_cxpt16/rtl/axis_crosspoint_16x16.v
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File diff suppressed because it is too large Load Diff

137
example/HXT100G/fpga_cxpt16/rtl/fpga_core.v
View File

@ -213,7 +213,9 @@ reg [7:0] select_reg_14 = 14;
reg [7:0] select_reg_15 = 15;
axis_crosspoint_16x16 #(
axis_crosspoint #(
.S_COUNT(16),
.M_COUNT(16),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
@ -226,120 +228,23 @@ axis_crosspoint_inst (
.clk(clk),
.rst(rst),
.input_0_axis_tdata(eth_l0_rxd),
.input_0_axis_tkeep(eth_l0_rxc),
.input_0_axis_tvalid(1'b1),
.input_1_axis_tdata(eth_l1_rxd),
.input_1_axis_tkeep(eth_l1_rxc),
.input_1_axis_tvalid(1'b1),
.input_2_axis_tdata(eth_l2_rxd),
.input_2_axis_tkeep(eth_l2_rxc),
.input_2_axis_tvalid(1'b1),
.input_3_axis_tdata(eth_l3_rxd),
.input_3_axis_tkeep(eth_l3_rxc),
.input_3_axis_tvalid(1'b1),
.input_4_axis_tdata(eth_l4_rxd),
.input_4_axis_tkeep(eth_l4_rxc),
.input_4_axis_tvalid(1'b1),
.input_5_axis_tdata(eth_l5_rxd),
.input_5_axis_tkeep(eth_l5_rxc),
.input_5_axis_tvalid(1'b1),
.input_6_axis_tdata(eth_l6_rxd),
.input_6_axis_tkeep(eth_l6_rxc),
.input_6_axis_tvalid(1'b1),
.input_7_axis_tdata(eth_l7_rxd),
.input_7_axis_tkeep(eth_l7_rxc),
.input_7_axis_tvalid(1'b1),
.input_8_axis_tdata(eth_r0_rxd),
.input_8_axis_tkeep(eth_r0_rxc),
.input_8_axis_tvalid(1'b1),
.input_9_axis_tdata(eth_r1_rxd),
.input_9_axis_tkeep(eth_r1_rxc),
.input_9_axis_tvalid(1'b1),
.input_10_axis_tdata(eth_r2_rxd),
.input_10_axis_tkeep(eth_r2_rxc),
.input_10_axis_tvalid(1'b1),
.input_11_axis_tdata(eth_r3_rxd),
.input_11_axis_tkeep(eth_r3_rxc),
.input_11_axis_tvalid(1'b1),
.input_12_axis_tdata(eth_r4_rxd),
.input_12_axis_tkeep(eth_r4_rxc),
.input_12_axis_tvalid(1'b1),
.input_13_axis_tdata(eth_r5_rxd),
.input_13_axis_tkeep(eth_r5_rxc),
.input_13_axis_tvalid(1'b1),
.input_14_axis_tdata(eth_r6_rxd),
.input_14_axis_tkeep(eth_r6_rxc),
.input_14_axis_tvalid(1'b1),
.input_15_axis_tdata(eth_r7_rxd),
.input_15_axis_tkeep(eth_r7_rxc),
.input_15_axis_tvalid(1'b1),
.s_axis_tdata({eth_r7_rxd, eth_r6_rxd, eth_r5_rxd, eth_r4_rxd, eth_r3_rxd, eth_r2_rxd, eth_r1_rxd, eth_r0_rxd, eth_l7_rxd, eth_l6_rxd, eth_l5_rxd, eth_l4_rxd, eth_l3_rxd, eth_l2_rxd, eth_l1_rxd, eth_l0_rxd}),
.s_axis_tkeep({eth_r7_rxc, eth_r6_rxc, eth_r5_rxc, eth_r4_rxc, eth_r3_rxc, eth_r2_rxc, eth_r1_rxc, eth_r0_rxc, eth_l7_rxc, eth_l6_rxc, eth_l5_rxc, eth_l4_rxc, eth_l3_rxc, eth_l2_rxc, eth_l1_rxc, eth_l0_rxc}),
.s_axis_tvalid(16'hffff),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
.output_0_axis_tdata(eth_l0_txd),
.output_0_axis_tkeep(eth_l0_txc),
.output_0_axis_tvalid(),
.output_1_axis_tdata(eth_l1_txd),
.output_1_axis_tkeep(eth_l1_txc),
.output_1_axis_tvalid(),
.output_2_axis_tdata(eth_l2_txd),
.output_2_axis_tkeep(eth_l2_txc),
.output_2_axis_tvalid(),
.output_3_axis_tdata(eth_l3_txd),
.output_3_axis_tkeep(eth_l3_txc),
.output_3_axis_tvalid(),
.output_4_axis_tdata(eth_l4_txd),
.output_4_axis_tkeep(eth_l4_txc),
.output_4_axis_tvalid(),
.output_5_axis_tdata(eth_l5_txd),
.output_5_axis_tkeep(eth_l5_txc),
.output_5_axis_tvalid(),
.output_6_axis_tdata(eth_l6_txd),
.output_6_axis_tkeep(eth_l6_txc),
.output_6_axis_tvalid(),
.output_7_axis_tdata(eth_l7_txd),
.output_7_axis_tkeep(eth_l7_txc),
.output_7_axis_tvalid(),
.output_8_axis_tdata(eth_r0_txd),
.output_8_axis_tkeep(eth_r0_txc),
.output_8_axis_tvalid(),
.output_9_axis_tdata(eth_r1_txd),
.output_9_axis_tkeep(eth_r1_txc),
.output_9_axis_tvalid(),
.output_10_axis_tdata(eth_r2_txd),
.output_10_axis_tkeep(eth_r2_txc),
.output_10_axis_tvalid(),
.output_11_axis_tdata(eth_r3_txd),
.output_11_axis_tkeep(eth_r3_txc),
.output_11_axis_tvalid(),
.output_12_axis_tdata(eth_r4_txd),
.output_12_axis_tkeep(eth_r4_txc),
.output_12_axis_tvalid(),
.output_13_axis_tdata(eth_r5_txd),
.output_13_axis_tkeep(eth_r5_txc),
.output_13_axis_tvalid(),
.output_14_axis_tdata(eth_r6_txd),
.output_14_axis_tkeep(eth_r6_txc),
.output_14_axis_tvalid(),
.output_15_axis_tdata(eth_r7_txd),
.output_15_axis_tkeep(eth_r7_txc),
.output_15_axis_tvalid(),
.m_axis_tdata({eth_r7_txd, eth_r6_txd, eth_r5_txd, eth_r4_txd, eth_r3_txd, eth_r2_txd, eth_r1_txd, eth_r0_txd, eth_l7_txd, eth_l6_txd, eth_l5_txd, eth_l4_txd, eth_l3_txd, eth_l2_txd, eth_l1_txd, eth_l0_txd}),
.m_axis_tkeep({eth_r7_txc, eth_r6_txc, eth_r5_txc, eth_r4_txc, eth_r3_txc, eth_r2_txc, eth_r1_txc, eth_r0_txc, eth_l7_txc, eth_l6_txc, eth_l5_txc, eth_l4_txc, eth_l3_txc, eth_l2_txc, eth_l1_txc, eth_l0_txc}),
.m_axis_tvalid(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.output_0_select(select_reg_0),
.output_1_select(select_reg_1),
.output_2_select(select_reg_2),
.output_3_select(select_reg_3),
.output_4_select(select_reg_4),
.output_5_select(select_reg_5),
.output_6_select(select_reg_6),
.output_7_select(select_reg_7),
.output_8_select(select_reg_8),
.output_9_select(select_reg_9),
.output_10_select(select_reg_10),
.output_11_select(select_reg_11),
.output_12_select(select_reg_12),
.output_13_select(select_reg_13),
.output_14_select(select_reg_14),
.output_15_select(select_reg_15)
.select({select_reg_15[3:0], select_reg_14[3:0], select_reg_13[3:0], select_reg_12[3:0], select_reg_11[3:0], select_reg_10[3:0], select_reg_9[3:0], select_reg_8[3:0], select_reg_7[3:0], select_reg_6[3:0], select_reg_5[3:0], select_reg_4[3:0], select_reg_3[3:0], select_reg_2[3:0], select_reg_1[3:0], select_reg_0[3:0]})
);
wire [63:0] eth_rx_axis_tdata;
@ -364,7 +269,11 @@ wire eth_rx_payload_tuser;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64)
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FRAME_FIFO(1)
)
eth_mac_fifo_inst (
.rx_clk(clk),

4
example/HXT100G/fpga_cxpt16/tb/test_fpga_core.py
View File

@ -35,7 +35,6 @@ testbench = 'test_%s' % module
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/axis_crosspoint_16x16.v")
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
@ -43,7 +42,8 @@ srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
srcs.append("../lib/eth/rtl/lfsr.v")
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_crosspoint.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/ML605/fpga_gmii/fpga_130t/Makefile
View File

@ -47,7 +47,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_gmii/fpga_240t/Makefile
View File

@ -47,7 +47,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

44
example/ML605/fpga_gmii/rtl/fpga_core.v
View File

@ -330,7 +330,9 @@ eth_mac_1g_gmii_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
@ -563,31 +565,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/ML605/fpga_gmii/tb/test_fpga_core.py
View File

@ -70,7 +70,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/ML605/fpga_rgmii/fpga_130t/Makefile
View File

@ -47,7 +47,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

2
example/ML605/fpga_rgmii/fpga_240t/Makefile
View File

@ -47,7 +47,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
#SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v
# UCF files

44
example/ML605/fpga_rgmii/rtl/fpga_core.v
View File

@ -329,7 +329,9 @@ eth_mac_1g_rgmii_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
@ -560,31 +562,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/ML605/fpga_rgmii/tb/test_fpga_core.py
View File

@ -70,7 +70,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/ML605/fpga_sgmii/fpga_130t/Makefile
View File

@ -41,7 +41,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

2
example/ML605/fpga_sgmii/fpga_240t/Makefile
View File

@ -41,7 +41,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_clk_gen.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_johnson_cntr.v
SYN_FILES += coregen/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/sgmii_adapt/gig_eth_pcs_pma_v11_5_rx_rate_adapt.v

44
example/ML605/fpga_sgmii/rtl/fpga_core.v
View File

@ -324,7 +324,9 @@ eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rx_clk(phy_gmii_clk),
@ -560,31 +562,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/ML605/fpga_sgmii/tb/test_fpga_core.py
View File

@ -64,7 +64,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/NexysVideo/fpga/fpga/Makefile
View File

@ -43,7 +43,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc

44
example/NexysVideo/fpga/rtl/fpga_core.v
View File

@ -318,7 +318,9 @@ eth_mac_1g_rgmii_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
@ -549,31 +551,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/NexysVideo/fpga/tb/test_fpga_core.py
View File

@ -70,7 +70,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

5
example/VCU108/fpga_10g/fpga/Makefile
View File

@ -44,8 +44,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch_4x4.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc

205
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -366,7 +366,9 @@ eth_mac_10g_fifo #(
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_ADDR_WIDTH(9)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(clk),
@ -438,7 +440,9 @@ eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
.rx_clk(phy_gmii_clk),
@ -485,8 +489,8 @@ eth_mac_1g_inst (
);
axis_adapter #(
.INPUT_DATA_WIDTH(8),
.OUTPUT_DATA_WIDTH(64),
.S_DATA_WIDTH(8),
.M_DATA_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
@ -496,24 +500,24 @@ gig_rx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(gig_rx_axis_tdata),
.input_axis_tkeep(1'b1),
.input_axis_tvalid(gig_rx_axis_tvalid),
.input_axis_tready(gig_rx_axis_tready),
.input_axis_tlast(gig_rx_axis_tlast),
.input_axis_tuser(gig_rx_axis_tuser),
.s_axis_tdata(gig_rx_axis_tdata),
.s_axis_tkeep(1'b1),
.s_axis_tvalid(gig_rx_axis_tvalid),
.s_axis_tready(gig_rx_axis_tready),
.s_axis_tlast(gig_rx_axis_tlast),
.s_axis_tuser(gig_rx_axis_tuser),
// AXI output
.output_axis_tdata(gig_rx_axis_tdata_64),
.output_axis_tkeep(gig_rx_axis_tkeep_64),
.output_axis_tvalid(gig_rx_axis_tvalid_64),
.output_axis_tready(gig_rx_axis_tready_64),
.output_axis_tlast(gig_rx_axis_tlast_64),
.output_axis_tuser(gig_rx_axis_tuser_64)
.m_axis_tdata(gig_rx_axis_tdata_64),
.m_axis_tkeep(gig_rx_axis_tkeep_64),
.m_axis_tvalid(gig_rx_axis_tvalid_64),
.m_axis_tready(gig_rx_axis_tready_64),
.m_axis_tlast(gig_rx_axis_tlast_64),
.m_axis_tuser(gig_rx_axis_tuser_64)
);
axis_adapter #(
.INPUT_DATA_WIDTH(64),
.OUTPUT_DATA_WIDTH(8),
.S_DATA_WIDTH(64),
.M_DATA_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
@ -523,19 +527,19 @@ gig_tx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(gig_tx_axis_tdata_64),
.input_axis_tkeep(gig_tx_axis_tkeep_64),
.input_axis_tvalid(gig_tx_axis_tvalid_64),
.input_axis_tready(gig_tx_axis_tready_64),
.input_axis_tlast(gig_tx_axis_tlast_64),
.input_axis_tuser(gig_tx_axis_tuser_64),
.s_axis_tdata(gig_tx_axis_tdata_64),
.s_axis_tkeep(gig_tx_axis_tkeep_64),
.s_axis_tvalid(gig_tx_axis_tvalid_64),
.s_axis_tready(gig_tx_axis_tready_64),
.s_axis_tlast(gig_tx_axis_tlast_64),
.s_axis_tuser(gig_tx_axis_tuser_64),
// AXI output
.output_axis_tdata(gig_tx_axis_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(gig_tx_axis_tvalid),
.output_axis_tready(gig_tx_axis_tready),
.output_axis_tlast(gig_tx_axis_tlast),
.output_axis_tuser(gig_tx_axis_tuser)
.m_axis_tdata(gig_tx_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(gig_tx_axis_tvalid),
.m_axis_tready(gig_tx_axis_tready),
.m_axis_tlast(gig_tx_axis_tlast),
.m_axis_tuser(gig_tx_axis_tuser)
);
// tap port mux logic
@ -576,25 +580,20 @@ always @* begin
end
end
axis_switch_4x4 #(
axis_switch #(
.S_COUNT(3),
.M_COUNT(3),
.DATA_WIDTH(64),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_WIDTH(2),
.USER_ENABLE(1),
.USER_WIDTH(1),
.OUT_0_BASE(0),
.OUT_0_TOP(0),
.OUT_0_CONNECT(4'b1111),
.OUT_1_BASE(1),
.OUT_1_TOP(1),
.OUT_1_CONNECT(4'b1111),
.OUT_2_BASE(2),
.OUT_2_TOP(2),
.OUT_2_CONNECT(4'b1111),
.OUT_3_BASE(3),
.OUT_3_TOP(3),
.OUT_3_CONNECT(4'b1111),
.M_BASE({32'd2, 32'd1, 32'd0}),
.M_TOP({32'd2, 32'd1, 32'd0}),
.M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0),
.M_REG_TYPE(1),
.ARB_TYPE("PRIORITY"),
.LSB_PRIORITY("HIGH")
)
@ -602,71 +601,23 @@ axis_switch_inst (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(mac_rx_axis_tdata),
.input_0_axis_tkeep(mac_rx_axis_tkeep),
.input_0_axis_tvalid(mac_rx_axis_tvalid),
.input_0_axis_tready(mac_rx_axis_tready),
.input_0_axis_tlast(mac_rx_axis_tlast),
.input_0_axis_tid(0),
.input_0_axis_tdest(mac_rx_tdest),
.input_0_axis_tuser(mac_rx_axis_tuser),
.input_1_axis_tdata(tx_axis_tdata),
.input_1_axis_tkeep(tx_axis_tkeep),
.input_1_axis_tvalid(tx_axis_tvalid),
.input_1_axis_tready(tx_axis_tready),
.input_1_axis_tlast(tx_axis_tlast),
.input_1_axis_tid(0),
.input_1_axis_tdest(tx_tdest),
.input_1_axis_tuser(tx_axis_tuser),
.input_2_axis_tdata(gig_rx_axis_tdata_64),
.input_2_axis_tkeep(gig_rx_axis_tkeep_64),
.input_2_axis_tvalid(gig_rx_axis_tvalid_64),
.input_2_axis_tready(gig_rx_axis_tready_64),
.input_2_axis_tlast(gig_rx_axis_tlast_64),
.input_2_axis_tid(0),
.input_2_axis_tdest(gig_rx_tdest),
.input_2_axis_tuser(gig_rx_axis_tuser_64),
.input_3_axis_tdata(64'd0),
.input_3_axis_tkeep(8'd0),
.input_3_axis_tvalid(1'b0),
.input_3_axis_tready(),
.input_3_axis_tlast(1'b0),
.input_3_axis_tid(0),
.input_3_axis_tdest(2'd0),
.input_3_axis_tuser(1'b0),
.s_axis_tdata({ gig_rx_axis_tdata_64, tx_axis_tdata, mac_rx_axis_tdata}),
.s_axis_tkeep({ gig_rx_axis_tkeep_64, tx_axis_tkeep, mac_rx_axis_tkeep}),
.s_axis_tvalid({gig_rx_axis_tvalid_64, tx_axis_tvalid, mac_rx_axis_tvalid}),
.s_axis_tready({gig_rx_axis_tready_64, tx_axis_tready, mac_rx_axis_tready}),
.s_axis_tlast({ gig_rx_axis_tlast_64, tx_axis_tlast, mac_rx_axis_tlast}),
.s_axis_tid(0),
.s_axis_tdest({ gig_rx_tdest, tx_tdest, mac_rx_tdest}),
.s_axis_tuser({ gig_rx_axis_tuser_64, tx_axis_tuser, mac_rx_axis_tuser}),
// AXI outputs
.output_0_axis_tdata(mac_tx_axis_tdata),
.output_0_axis_tkeep(mac_tx_axis_tkeep),
.output_0_axis_tvalid(mac_tx_axis_tvalid),
.output_0_axis_tready(mac_tx_axis_tready),
.output_0_axis_tlast(mac_tx_axis_tlast),
.output_0_axis_tid(),
.output_0_axis_tdest(),
.output_0_axis_tuser(mac_tx_axis_tuser),
.output_1_axis_tdata(rx_axis_tdata),
.output_1_axis_tkeep(rx_axis_tkeep),
.output_1_axis_tvalid(rx_axis_tvalid),
.output_1_axis_tready(rx_axis_tready),
.output_1_axis_tlast(rx_axis_tlast),
.output_1_axis_tid(),
.output_1_axis_tdest(),
.output_1_axis_tuser(rx_axis_tuser),
.output_2_axis_tdata(gig_tx_axis_tdata_64),
.output_2_axis_tkeep(gig_tx_axis_tkeep_64),
.output_2_axis_tvalid(gig_tx_axis_tvalid_64),
.output_2_axis_tready(gig_tx_axis_tready_64),
.output_2_axis_tlast(gig_tx_axis_tlast_64),
.output_2_axis_tid(),
.output_2_axis_tdest(),
.output_2_axis_tuser(gig_tx_axis_tuser_64),
.output_3_axis_tdata(),
.output_3_axis_tkeep(),
.output_3_axis_tvalid(),
.output_3_axis_tready(1'b1),
.output_3_axis_tlast(),
.output_3_axis_tid(),
.output_3_axis_tdest(),
.output_3_axis_tuser()
.m_axis_tdata({ gig_tx_axis_tdata_64, rx_axis_tdata, mac_tx_axis_tdata}),
.m_axis_tkeep({ gig_tx_axis_tkeep_64, rx_axis_tkeep, mac_tx_axis_tkeep}),
.m_axis_tvalid({gig_tx_axis_tvalid_64, rx_axis_tvalid, mac_tx_axis_tvalid}),
.m_axis_tready({gig_tx_axis_tready_64, rx_axis_tready, mac_tx_axis_tready}),
.m_axis_tlast({ gig_tx_axis_tlast_64, rx_axis_tlast, mac_tx_axis_tlast}),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser({ gig_tx_axis_tuser_64, rx_axis_tuser, mac_tx_axis_tuser})
);
eth_axis_rx_64
@ -870,31 +821,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(rx_fifo_udp_payload_tkeep),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(tx_fifo_udp_payload_tkeep),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

5
example/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -72,8 +72,9 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_adapter.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch_4x4.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_register.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/VCU108/fpga_1g/fpga/Makefile
View File

@ -37,7 +37,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc

44
example/VCU108/fpga_1g/rtl/fpga_core.v
View File

@ -315,7 +315,9 @@ eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rx_clk(phy_gmii_clk),
@ -551,31 +553,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/VCU108/fpga_1g/tb/test_fpga_core.py
View File

@ -64,7 +64,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

5
example/VCU118/fpga_10g/fpga/Makefile
View File

@ -43,8 +43,9 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch_4x4.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc

205
example/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -423,7 +423,9 @@ eth_mac_10g_fifo #(
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(9),
.RX_FIFO_ADDR_WIDTH(9)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(9),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp1_rx_clk_1),
@ -495,7 +497,9 @@ eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_1g_inst (
.rx_clk(phy_gmii_clk),
@ -542,8 +546,8 @@ eth_mac_1g_inst (
);
axis_adapter #(
.INPUT_DATA_WIDTH(8),
.OUTPUT_DATA_WIDTH(64),
.S_DATA_WIDTH(8),
.M_DATA_WIDTH(64),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
@ -553,24 +557,24 @@ gig_rx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(gig_rx_axis_tdata),
.input_axis_tkeep(1'b1),
.input_axis_tvalid(gig_rx_axis_tvalid),
.input_axis_tready(gig_rx_axis_tready),
.input_axis_tlast(gig_rx_axis_tlast),
.input_axis_tuser(gig_rx_axis_tuser),
.s_axis_tdata(gig_rx_axis_tdata),
.s_axis_tkeep(1'b1),
.s_axis_tvalid(gig_rx_axis_tvalid),
.s_axis_tready(gig_rx_axis_tready),
.s_axis_tlast(gig_rx_axis_tlast),
.s_axis_tuser(gig_rx_axis_tuser),
// AXI output
.output_axis_tdata(gig_rx_axis_tdata_64),
.output_axis_tkeep(gig_rx_axis_tkeep_64),
.output_axis_tvalid(gig_rx_axis_tvalid_64),
.output_axis_tready(gig_rx_axis_tready_64),
.output_axis_tlast(gig_rx_axis_tlast_64),
.output_axis_tuser(gig_rx_axis_tuser_64)
.m_axis_tdata(gig_rx_axis_tdata_64),
.m_axis_tkeep(gig_rx_axis_tkeep_64),
.m_axis_tvalid(gig_rx_axis_tvalid_64),
.m_axis_tready(gig_rx_axis_tready_64),
.m_axis_tlast(gig_rx_axis_tlast_64),
.m_axis_tuser(gig_rx_axis_tuser_64)
);
axis_adapter #(
.INPUT_DATA_WIDTH(64),
.OUTPUT_DATA_WIDTH(8),
.S_DATA_WIDTH(64),
.M_DATA_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
@ -580,19 +584,19 @@ gig_tx_axis_adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(gig_tx_axis_tdata_64),
.input_axis_tkeep(gig_tx_axis_tkeep_64),
.input_axis_tvalid(gig_tx_axis_tvalid_64),
.input_axis_tready(gig_tx_axis_tready_64),
.input_axis_tlast(gig_tx_axis_tlast_64),
.input_axis_tuser(gig_tx_axis_tuser_64),
.s_axis_tdata(gig_tx_axis_tdata_64),
.s_axis_tkeep(gig_tx_axis_tkeep_64),
.s_axis_tvalid(gig_tx_axis_tvalid_64),
.s_axis_tready(gig_tx_axis_tready_64),
.s_axis_tlast(gig_tx_axis_tlast_64),
.s_axis_tuser(gig_tx_axis_tuser_64),
// AXI output
.output_axis_tdata(gig_tx_axis_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(gig_tx_axis_tvalid),
.output_axis_tready(gig_tx_axis_tready),
.output_axis_tlast(gig_tx_axis_tlast),
.output_axis_tuser(gig_tx_axis_tuser)
.m_axis_tdata(gig_tx_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(gig_tx_axis_tvalid),
.m_axis_tready(gig_tx_axis_tready),
.m_axis_tlast(gig_tx_axis_tlast),
.m_axis_tuser(gig_tx_axis_tuser)
);
// tap port mux logic
@ -633,25 +637,20 @@ always @* begin
end
end
axis_switch_4x4 #(
axis_switch #(
.S_COUNT(3),
.M_COUNT(3),
.DATA_WIDTH(64),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_WIDTH(2),
.USER_ENABLE(1),
.USER_WIDTH(1),
.OUT_0_BASE(0),
.OUT_0_TOP(0),
.OUT_0_CONNECT(4'b1111),
.OUT_1_BASE(1),
.OUT_1_TOP(1),
.OUT_1_CONNECT(4'b1111),
.OUT_2_BASE(2),
.OUT_2_TOP(2),
.OUT_2_CONNECT(4'b1111),
.OUT_3_BASE(3),
.OUT_3_TOP(3),
.OUT_3_CONNECT(4'b1111),
.M_BASE({32'd2, 32'd1, 32'd0}),
.M_TOP({32'd2, 32'd1, 32'd0}),
.M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0),
.M_REG_TYPE(1),
.ARB_TYPE("PRIORITY"),
.LSB_PRIORITY("HIGH")
)
@ -659,71 +658,23 @@ axis_switch_inst (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(mac_rx_axis_tdata),
.input_0_axis_tkeep(mac_rx_axis_tkeep),
.input_0_axis_tvalid(mac_rx_axis_tvalid),
.input_0_axis_tready(mac_rx_axis_tready),
.input_0_axis_tlast(mac_rx_axis_tlast),
.input_0_axis_tid(0),
.input_0_axis_tdest(mac_rx_tdest),
.input_0_axis_tuser(mac_rx_axis_tuser),
.input_1_axis_tdata(tx_axis_tdata),
.input_1_axis_tkeep(tx_axis_tkeep),
.input_1_axis_tvalid(tx_axis_tvalid),
.input_1_axis_tready(tx_axis_tready),
.input_1_axis_tlast(tx_axis_tlast),
.input_1_axis_tid(0),
.input_1_axis_tdest(tx_tdest),
.input_1_axis_tuser(tx_axis_tuser),
.input_2_axis_tdata(gig_rx_axis_tdata_64),
.input_2_axis_tkeep(gig_rx_axis_tkeep_64),
.input_2_axis_tvalid(gig_rx_axis_tvalid_64),
.input_2_axis_tready(gig_rx_axis_tready_64),
.input_2_axis_tlast(gig_rx_axis_tlast_64),
.input_2_axis_tid(0),
.input_2_axis_tdest(gig_rx_tdest),
.input_2_axis_tuser(gig_rx_axis_tuser_64),
.input_3_axis_tdata(64'd0),
.input_3_axis_tkeep(8'd0),
.input_3_axis_tvalid(1'b0),
.input_3_axis_tready(),
.input_3_axis_tlast(1'b0),
.input_3_axis_tid(0),
.input_3_axis_tdest(2'd0),
.input_3_axis_tuser(1'b0),
.s_axis_tdata({ gig_rx_axis_tdata_64, tx_axis_tdata, mac_rx_axis_tdata}),
.s_axis_tkeep({ gig_rx_axis_tkeep_64, tx_axis_tkeep, mac_rx_axis_tkeep}),
.s_axis_tvalid({gig_rx_axis_tvalid_64, tx_axis_tvalid, mac_rx_axis_tvalid}),
.s_axis_tready({gig_rx_axis_tready_64, tx_axis_tready, mac_rx_axis_tready}),
.s_axis_tlast({ gig_rx_axis_tlast_64, tx_axis_tlast, mac_rx_axis_tlast}),
.s_axis_tid(0),
.s_axis_tdest({ gig_rx_tdest, tx_tdest, mac_rx_tdest}),
.s_axis_tuser({ gig_rx_axis_tuser_64, tx_axis_tuser, mac_rx_axis_tuser}),
// AXI outputs
.output_0_axis_tdata(mac_tx_axis_tdata),
.output_0_axis_tkeep(mac_tx_axis_tkeep),
.output_0_axis_tvalid(mac_tx_axis_tvalid),
.output_0_axis_tready(mac_tx_axis_tready),
.output_0_axis_tlast(mac_tx_axis_tlast),
.output_0_axis_tid(),
.output_0_axis_tdest(),
.output_0_axis_tuser(mac_tx_axis_tuser),
.output_1_axis_tdata(rx_axis_tdata),
.output_1_axis_tkeep(rx_axis_tkeep),
.output_1_axis_tvalid(rx_axis_tvalid),
.output_1_axis_tready(rx_axis_tready),
.output_1_axis_tlast(rx_axis_tlast),
.output_1_axis_tid(),
.output_1_axis_tdest(),
.output_1_axis_tuser(rx_axis_tuser),
.output_2_axis_tdata(gig_tx_axis_tdata_64),
.output_2_axis_tkeep(gig_tx_axis_tkeep_64),
.output_2_axis_tvalid(gig_tx_axis_tvalid_64),
.output_2_axis_tready(gig_tx_axis_tready_64),
.output_2_axis_tlast(gig_tx_axis_tlast_64),
.output_2_axis_tid(),
.output_2_axis_tdest(),
.output_2_axis_tuser(gig_tx_axis_tuser_64),
.output_3_axis_tdata(),
.output_3_axis_tkeep(),
.output_3_axis_tvalid(),
.output_3_axis_tready(1'b1),
.output_3_axis_tlast(),
.output_3_axis_tid(),
.output_3_axis_tdest(),
.output_3_axis_tuser()
.m_axis_tdata({ gig_tx_axis_tdata_64, rx_axis_tdata, mac_tx_axis_tdata}),
.m_axis_tkeep({ gig_tx_axis_tkeep_64, rx_axis_tkeep, mac_tx_axis_tkeep}),
.m_axis_tvalid({gig_tx_axis_tvalid_64, rx_axis_tvalid, mac_tx_axis_tvalid}),
.m_axis_tready({gig_tx_axis_tready_64, rx_axis_tready, mac_tx_axis_tready}),
.m_axis_tlast({ gig_tx_axis_tlast_64, rx_axis_tlast, mac_tx_axis_tlast}),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser({ gig_tx_axis_tuser_64, rx_axis_tuser, mac_tx_axis_tuser})
);
eth_axis_rx_64
@ -927,31 +878,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(rx_fifo_udp_payload_tkeep),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(tx_fifo_udp_payload_tkeep),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

5
example/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -72,8 +72,9 @@ srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_adapter.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch_4x4.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_switch.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_register.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)

2
example/VCU118/fpga_1g/fpga/Makefile
View File

@ -38,7 +38,7 @@ SYN_FILES += lib/eth/rtl/eth_mux_2.v
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_frame_fifo.v
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
# XDC files
XDC_FILES = fpga.xdc

44
example/VCU118/fpga_1g/rtl/fpga_core.v
View File

@ -315,7 +315,9 @@ eth_mac_1g_fifo #(
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_ADDR_WIDTH(12),
.RX_FIFO_ADDR_WIDTH(12)
.TX_FRAME_FIFO(1),
.RX_FIFO_ADDR_WIDTH(12),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.rx_clk(phy_gmii_clk),
@ -551,31 +553,37 @@ axis_fifo #(
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1)
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(rx_fifo_udp_payload_tdata),
.input_axis_tkeep(0),
.input_axis_tvalid(rx_fifo_udp_payload_tvalid),
.input_axis_tready(rx_fifo_udp_payload_tready),
.input_axis_tlast(rx_fifo_udp_payload_tlast),
.input_axis_tid(0),
.input_axis_tdest(0),
.input_axis_tuser(rx_fifo_udp_payload_tuser),
.s_axis_tdata(rx_fifo_udp_payload_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_tvalid),
.s_axis_tready(rx_fifo_udp_payload_tready),
.s_axis_tlast(rx_fifo_udp_payload_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_tuser),
// AXI output
.output_axis_tdata(tx_fifo_udp_payload_tdata),
.output_axis_tkeep(),
.output_axis_tvalid(tx_fifo_udp_payload_tvalid),
.output_axis_tready(tx_fifo_udp_payload_tready),
.output_axis_tlast(tx_fifo_udp_payload_tlast),
.output_axis_tid(),
.output_axis_tdest(),
.output_axis_tuser(tx_fifo_udp_payload_tuser)
.m_axis_tdata(tx_fifo_udp_payload_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_tvalid),
.m_axis_tready(tx_fifo_udp_payload_tready),
.m_axis_tlast(tx_fifo_udp_payload_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule

2
example/VCU118/fpga_1g/tb/test_fpga_core.py
View File

@ -64,7 +64,7 @@ srcs.append("../lib/eth/rtl/eth_mux_2.v")
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_frame_fifo.v")
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
srcs.append("%s.v" % testbench)
src = ' '.join(srcs)