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mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00

fpga/mqnic: Clean up PCIe core instances

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-09-04 23:04:58 -07:00
parent 36576d8981
commit 7e497db017
11 changed files with 0 additions and 39 deletions

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@ -674,9 +674,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -681,9 +681,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1060,9 +1060,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1067,9 +1067,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1060,9 +1060,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1067,9 +1067,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -930,20 +930,11 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),
.sys_reset(pcie_reset_n),
// .int_qpll0lock_out(),
// .int_qpll0outrefclk_out(),
// .int_qpll0outclk_out(),
// .int_qpll1lock_out(),
// .int_qpll1outrefclk_out(),
// .int_qpll1outclk_out(),
.phy_rdy_out()
);

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@ -905,9 +905,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -912,9 +912,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1000,9 +1000,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),

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@ -1007,9 +1007,6 @@ pcie4_uscale_plus_inst (
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
//.cfg_ds_function_number(3'd0),
//.cfg_subsys_vend_id(16'h1234),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),