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Add ARP cache module

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Alex Forencich 2014-11-20 22:54:08 -08:00
parent f35ecece83
commit 7fdb7b4f35
3 changed files with 824 additions and 0 deletions
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178
rtl/arp_cache.v Normal file
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP cache block
*/
module arp_cache #(
parameter CACHE_ADDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* Query cache
*/
input wire query_request_valid,
input wire [31:0] query_request_ip,
output wire query_response_valid,
output wire query_response_error,
output wire [47:0] query_response_mac,
/*
* Write cache
*/
input wire write_request_valid,
input wire [31:0] write_request_ip,
input wire [47:0] write_request_mac,
output wire write_in_progress,
output wire write_complete,
/*
* Configuration
*/
input wire clear_cache
);
// bit LRU cache
reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
reg [(2**CACHE_ADDR_WIDTH)-1:0] lru_bit = 0;
reg query_response_valid_reg = 0;
reg query_response_error_reg = 0;
reg [47:0] query_response_mac_reg = 0;
reg write_complete_reg = 0;
localparam [2:0]
WRITE_STATE_IDLE = 0,
WRITE_STATE_SEARCH = 1,
WRITE_STATE_NOTFOUND = 2;
reg [2:0] write_state = WRITE_STATE_IDLE;
reg [31:0] write_ip_reg = 0;
reg [47:0] write_mac_reg = 0;
reg [CACHE_ADDR_WIDTH-1:0] write_addr = 0;
reg [CACHE_ADDR_WIDTH-1:0] write_ptr = 0;
wire write_state_idle = (write_state == WRITE_STATE_IDLE);
wire write_state_search = (write_state == WRITE_STATE_SEARCH);
wire write_state_notfound = (write_state == WRITE_STATE_NOTFOUND);
reg clear_cache_operation = 0;
assign query_response_valid = query_response_valid_reg;
assign query_response_error = query_response_error_reg;
assign query_response_mac = query_response_mac_reg;
assign write_in_progress = ~write_state_idle;
assign write_complete = write_complete_reg;
wire lru_full = &lru_bit;
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
query_response_valid_reg <= 0;
query_response_error_reg <= 0;
write_complete_reg <= 0;
write_state <= WRITE_STATE_IDLE;
write_addr <= 0;
write_ptr <= 0;
clear_cache_operation <= 1;
lru_bit <= 0;
end else begin
write_complete_reg <= 0;
query_response_valid_reg <= 0;
query_response_error_reg <= 0;
// clear LRU bits when full
if (lru_full) begin
lru_bit <= 0;
end
// fast IP match and readout
if (query_request_valid) begin
query_response_valid_reg <= 1;
query_response_error_reg <= 1;
for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
if (ip_addr_mem[i] == query_request_ip) begin
query_response_error_reg <= 0;
query_response_mac_reg <= mac_addr_mem[i];
lru_bit[i] <= 1'b1;
end
end
end
// manage writes
if (write_state_idle) begin
if (write_request_valid) begin
write_state <= WRITE_STATE_SEARCH;
write_ip_reg <= write_request_ip;
write_mac_reg <= write_request_mac;
end
write_addr <= 0;
end else if (write_state_search) begin
write_addr <= write_addr + 1;
if (&write_addr) begin
write_state <= WRITE_STATE_NOTFOUND;
end
if (ip_addr_mem[write_addr] == write_ip_reg) begin
write_state <= WRITE_STATE_IDLE;
mac_addr_mem[write_addr] <= write_mac_reg;
write_complete_reg <= 1;
end
end else if (write_state_notfound) begin
write_ptr <= write_ptr + 1;
if (~lru_bit[write_ptr]) begin
ip_addr_mem[write_ptr] <= write_ip_reg;
mac_addr_mem[write_ptr] <= write_mac_reg;
write_state <= WRITE_STATE_IDLE;
write_complete_reg <= 1;
end
end
// clear cache
if (clear_cache & ~clear_cache_operation) begin
clear_cache_operation <= 1;
write_addr <= 0;
end
if (clear_cache_operation) begin
write_addr <= write_addr + 1;
ip_addr_mem[write_addr] <= 0;
mac_addr_mem[write_addr] <= 0;
clear_cache_operation <= ~&write_addr;
end
end
end
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
module = 'arp_cache'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_arp_cache(clk,
rst,
current_test,
query_request_valid,
query_request_ip,
query_response_valid,
query_response_error,
query_response_mac,
write_request_valid,
write_request_ip,
write_request_mac,
write_in_progress,
write_complete,
clear_cache):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
query_request_valid=query_request_valid,
query_request_ip=query_request_ip,
query_response_valid=query_response_valid,
query_response_error=query_response_error,
query_response_mac=query_response_mac,
write_request_valid=write_request_valid,
write_request_ip=write_request_ip,
write_request_mac=write_request_mac,
write_in_progress=write_in_progress,
write_complete=write_complete,
clear_cache=clear_cache)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
query_request_valid = Signal(bool(0))
query_request_ip = Signal(intbv(0)[32:])
write_request_valid = Signal(bool(0))
write_request_ip = Signal(intbv(0)[32:])
write_request_mac = Signal(intbv(0)[48:])
clear_cache = Signal(bool(0))
# Outputs
query_response_valid = Signal(bool(0))
query_response_error = Signal(bool(0))
query_response_mac = Signal(intbv(0)[48:])
write_in_progress = Signal(bool(0))
write_complete = Signal(bool(0))
# DUT
dut = dut_arp_cache(clk,
rst,
current_test,
query_request_valid,
query_request_ip,
query_response_valid,
query_response_error,
query_response_mac,
write_request_valid,
write_request_ip,
write_request_mac,
write_in_progress,
write_complete,
clear_cache)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: write")
current_test.next = 1
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80111
write_request_mac.next = 0x0000c0a80111
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80112
write_request_mac.next = 0x0000c0a80112
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 2: read")
current_test.next = 2
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80111
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80112
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80112
# not in cache; was not written
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80113
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield delay(100)
yield clk.posedge
print("test 3: write more")
current_test.next = 3
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80121
write_request_mac.next = 0x0000c0a80121
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80122
write_request_mac.next = 0x0000c0a80122
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
# overwrites 0xc0a80121 due to LRU
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80123
write_request_mac.next = 0x0000c0a80123
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield delay(100)
yield clk.posedge
print("test 4: read more")
current_test.next = 4
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80111
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80112
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80112
# not in cache; was overwritten
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80121
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80122
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80122
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80123
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80123
# LRU reset by previous operation
yield delay(100)
yield clk.posedge
print("test 5: LRU test")
current_test.next = 5
# read to set LRU bit
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80111
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80131
write_request_mac.next = 0x0000c0a80131
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80132
write_request_mac.next = 0x0000c0a80132
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80133
write_request_mac.next = 0x0000c0a80133
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
# read values
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80111
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80112
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80121
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80122
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80123
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80131
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80131
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80132
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80132
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80133
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80133
# LRU reset by previous operation
yield delay(100)
yield clk.posedge
print("test 6: Test overwrite")
current_test.next = 6
yield clk.posedge
write_request_valid.next = True
write_request_ip.next = 0xc0a80133
write_request_mac.next = 0x0000c0a80164
yield clk.posedge
write_request_valid.next = False
yield write_complete.posedge
yield clk.posedge
# read values
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80111
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80112
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80121
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80122
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80123
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80131
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80131
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80132
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80132
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80133
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert not bool(query_response_error)
assert int(query_response_mac) == 0x0000c0a80164
# LRU reset by previous operation
yield delay(100)
yield clk.posedge
print("test 7: clear cache")
current_test.next = 7
yield clk.posedge
clear_cache.next = True
yield clk.posedge
clear_cache.next = False
yield delay(100)
yield clk.posedge
query_request_valid.next = True
query_request_ip.next = 0xc0a80111
yield clk.posedge
query_request_valid.next = False
yield query_response_valid.posedge
assert bool(query_response_error)
yield delay(100)
raise StopSimulation
return dut, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_arp_cache;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg query_request_valid = 0;
reg [31:0] query_request_ip = 0;
reg write_request_valid = 0;
reg [31:0] write_request_ip = 0;
reg [47:0] write_request_mac = 0;
reg clear_cache = 0;
// Outputs
wire query_response_valid;
wire query_response_error;
wire [47:0] query_response_mac;
wire write_in_progress;
wire write_complete;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
query_request_valid,
query_request_ip,
write_request_valid,
write_request_ip,
write_request_mac,
clear_cache);
$to_myhdl(query_response_valid,
query_response_error,
query_response_mac,
write_in_progress,
write_complete);
// dump file
$dumpfile("test_arp_cache.lxt");
$dumpvars(0, test_arp_cache);
end
arp_cache #(
.CACHE_ADDR_WIDTH(2)
)
UUT (
.clk(clk),
.rst(rst),
// Query cache
.query_request_valid(query_request_valid),
.query_request_ip(query_request_ip),
.query_response_valid(query_response_valid),
.query_response_error(query_response_error),
.query_response_mac(query_response_mac),
// Write cache
.write_request_valid(write_request_valid),
.write_request_ip(write_request_ip),
.write_request_mac(write_request_mac),
.write_in_progress(write_in_progress),
.write_complete(write_complete),
// Configuration
.clear_cache(clear_cache)
);
endmodule