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Add ARP cache module
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178
rtl/arp_cache.v
Normal file
178
rtl/arp_cache.v
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/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* ARP cache block
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*/
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module arp_cache #(
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parameter CACHE_ADDR_WIDTH = 2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Query cache
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*/
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input wire query_request_valid,
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input wire [31:0] query_request_ip,
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output wire query_response_valid,
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output wire query_response_error,
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output wire [47:0] query_response_mac,
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/*
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* Write cache
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*/
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input wire write_request_valid,
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input wire [31:0] write_request_ip,
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input wire [47:0] write_request_mac,
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output wire write_in_progress,
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output wire write_complete,
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/*
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* Configuration
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*/
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input wire clear_cache
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);
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// bit LRU cache
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reg [31:0] ip_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
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reg [47:0] mac_addr_mem[(2**CACHE_ADDR_WIDTH)-1:0];
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reg [(2**CACHE_ADDR_WIDTH)-1:0] lru_bit = 0;
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reg query_response_valid_reg = 0;
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reg query_response_error_reg = 0;
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reg [47:0] query_response_mac_reg = 0;
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reg write_complete_reg = 0;
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localparam [2:0]
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WRITE_STATE_IDLE = 0,
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WRITE_STATE_SEARCH = 1,
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WRITE_STATE_NOTFOUND = 2;
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reg [2:0] write_state = WRITE_STATE_IDLE;
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reg [31:0] write_ip_reg = 0;
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reg [47:0] write_mac_reg = 0;
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reg [CACHE_ADDR_WIDTH-1:0] write_addr = 0;
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reg [CACHE_ADDR_WIDTH-1:0] write_ptr = 0;
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wire write_state_idle = (write_state == WRITE_STATE_IDLE);
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wire write_state_search = (write_state == WRITE_STATE_SEARCH);
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wire write_state_notfound = (write_state == WRITE_STATE_NOTFOUND);
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reg clear_cache_operation = 0;
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assign query_response_valid = query_response_valid_reg;
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assign query_response_error = query_response_error_reg;
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assign query_response_mac = query_response_mac_reg;
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assign write_in_progress = ~write_state_idle;
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assign write_complete = write_complete_reg;
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wire lru_full = &lru_bit;
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integer i;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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query_response_valid_reg <= 0;
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query_response_error_reg <= 0;
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write_complete_reg <= 0;
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write_state <= WRITE_STATE_IDLE;
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write_addr <= 0;
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write_ptr <= 0;
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clear_cache_operation <= 1;
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lru_bit <= 0;
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end else begin
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write_complete_reg <= 0;
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query_response_valid_reg <= 0;
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query_response_error_reg <= 0;
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// clear LRU bits when full
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if (lru_full) begin
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lru_bit <= 0;
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end
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// fast IP match and readout
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if (query_request_valid) begin
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query_response_valid_reg <= 1;
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query_response_error_reg <= 1;
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for (i = 0; i < 2**CACHE_ADDR_WIDTH; i = i + 1) begin
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if (ip_addr_mem[i] == query_request_ip) begin
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query_response_error_reg <= 0;
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query_response_mac_reg <= mac_addr_mem[i];
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lru_bit[i] <= 1'b1;
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end
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end
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end
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// manage writes
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if (write_state_idle) begin
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if (write_request_valid) begin
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write_state <= WRITE_STATE_SEARCH;
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write_ip_reg <= write_request_ip;
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write_mac_reg <= write_request_mac;
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end
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write_addr <= 0;
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end else if (write_state_search) begin
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write_addr <= write_addr + 1;
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if (&write_addr) begin
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write_state <= WRITE_STATE_NOTFOUND;
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end
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if (ip_addr_mem[write_addr] == write_ip_reg) begin
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write_state <= WRITE_STATE_IDLE;
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mac_addr_mem[write_addr] <= write_mac_reg;
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write_complete_reg <= 1;
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end
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end else if (write_state_notfound) begin
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write_ptr <= write_ptr + 1;
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if (~lru_bit[write_ptr]) begin
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ip_addr_mem[write_ptr] <= write_ip_reg;
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mac_addr_mem[write_ptr] <= write_mac_reg;
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write_state <= WRITE_STATE_IDLE;
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write_complete_reg <= 1;
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end
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end
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// clear cache
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if (clear_cache & ~clear_cache_operation) begin
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clear_cache_operation <= 1;
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write_addr <= 0;
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end
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if (clear_cache_operation) begin
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write_addr <= write_addr + 1;
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ip_addr_mem[write_addr] <= 0;
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mac_addr_mem[write_addr] <= 0;
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clear_cache_operation <= ~&write_addr;
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end
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end
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end
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endmodule
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549
tb/test_arp_cache.py
Executable file
549
tb/test_arp_cache.py
Executable file
@ -0,0 +1,549 @@
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#!/usr/bin/env python2
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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|
copies of the Software, and to permit persons to whom the Software is
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|
furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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module = 'arp_cache'
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("test_%s.v" % module)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_arp_cache(clk,
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rst,
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current_test,
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query_request_valid,
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query_request_ip,
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query_response_valid,
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query_response_error,
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query_response_mac,
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write_request_valid,
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write_request_ip,
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write_request_mac,
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write_in_progress,
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write_complete,
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clear_cache):
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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clk=clk,
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rst=rst,
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current_test=current_test,
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query_request_valid=query_request_valid,
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query_request_ip=query_request_ip,
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query_response_valid=query_response_valid,
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query_response_error=query_response_error,
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query_response_mac=query_response_mac,
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write_request_valid=write_request_valid,
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write_request_ip=write_request_ip,
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write_request_mac=write_request_mac,
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write_in_progress=write_in_progress,
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write_complete=write_complete,
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clear_cache=clear_cache)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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query_request_valid = Signal(bool(0))
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query_request_ip = Signal(intbv(0)[32:])
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write_request_valid = Signal(bool(0))
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write_request_ip = Signal(intbv(0)[32:])
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write_request_mac = Signal(intbv(0)[48:])
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clear_cache = Signal(bool(0))
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# Outputs
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query_response_valid = Signal(bool(0))
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query_response_error = Signal(bool(0))
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query_response_mac = Signal(intbv(0)[48:])
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write_in_progress = Signal(bool(0))
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write_complete = Signal(bool(0))
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# DUT
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dut = dut_arp_cache(clk,
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rst,
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current_test,
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query_request_valid,
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query_request_ip,
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query_response_valid,
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query_response_error,
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query_response_mac,
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write_request_valid,
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write_request_ip,
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write_request_mac,
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write_in_progress,
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write_complete,
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clear_cache)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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print("test 1: write")
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current_test.next = 1
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80111
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write_request_mac.next = 0x0000c0a80111
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80112
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write_request_mac.next = 0x0000c0a80112
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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print("test 2: read")
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current_test.next = 2
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80111
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80111
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80112
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert not bool(query_response_error)
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assert int(query_response_mac) == 0x0000c0a80112
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# not in cache; was not written
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yield clk.posedge
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query_request_valid.next = True
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query_request_ip.next = 0xc0a80113
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yield clk.posedge
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query_request_valid.next = False
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yield query_response_valid.posedge
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assert bool(query_response_error)
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yield delay(100)
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yield clk.posedge
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print("test 3: write more")
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current_test.next = 3
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80121
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write_request_mac.next = 0x0000c0a80121
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80122
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write_request_mac.next = 0x0000c0a80122
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yield clk.posedge
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write_request_valid.next = False
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yield write_complete.posedge
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yield clk.posedge
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# overwrites 0xc0a80121 due to LRU
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yield clk.posedge
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write_request_valid.next = True
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write_request_ip.next = 0xc0a80123
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||||||
|
write_request_mac.next = 0x0000c0a80123
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = False
|
||||||
|
|
||||||
|
yield write_complete.posedge
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 4: read more")
|
||||||
|
current_test.next = 4
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80111
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80111
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80112
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80112
|
||||||
|
|
||||||
|
# not in cache; was overwritten
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80121
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80122
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80122
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80123
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80123
|
||||||
|
|
||||||
|
# LRU reset by previous operation
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 5: LRU test")
|
||||||
|
current_test.next = 5
|
||||||
|
|
||||||
|
# read to set LRU bit
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80111
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80111
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = True
|
||||||
|
write_request_ip.next = 0xc0a80131
|
||||||
|
write_request_mac.next = 0x0000c0a80131
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = False
|
||||||
|
|
||||||
|
yield write_complete.posedge
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = True
|
||||||
|
write_request_ip.next = 0xc0a80132
|
||||||
|
write_request_mac.next = 0x0000c0a80132
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = False
|
||||||
|
|
||||||
|
yield write_complete.posedge
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = True
|
||||||
|
write_request_ip.next = 0xc0a80133
|
||||||
|
write_request_mac.next = 0x0000c0a80133
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = False
|
||||||
|
|
||||||
|
yield write_complete.posedge
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
# read values
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80111
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80111
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80112
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80121
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80122
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80123
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80131
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80131
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80132
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80132
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80133
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80133
|
||||||
|
|
||||||
|
# LRU reset by previous operation
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 6: Test overwrite")
|
||||||
|
current_test.next = 6
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = True
|
||||||
|
write_request_ip.next = 0xc0a80133
|
||||||
|
write_request_mac.next = 0x0000c0a80164
|
||||||
|
yield clk.posedge
|
||||||
|
write_request_valid.next = False
|
||||||
|
|
||||||
|
yield write_complete.posedge
|
||||||
|
yield clk.posedge
|
||||||
|
|
||||||
|
# read values
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80111
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80111
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80112
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80121
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80122
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80123
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80131
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80131
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80132
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80132
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80133
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert not bool(query_response_error)
|
||||||
|
assert int(query_response_mac) == 0x0000c0a80164
|
||||||
|
|
||||||
|
# LRU reset by previous operation
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
print("test 7: clear cache")
|
||||||
|
current_test.next = 7
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
clear_cache.next = True
|
||||||
|
yield clk.posedge
|
||||||
|
clear_cache.next = False
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = True
|
||||||
|
query_request_ip.next = 0xc0a80111
|
||||||
|
yield clk.posedge
|
||||||
|
query_request_valid.next = False
|
||||||
|
|
||||||
|
yield query_response_valid.posedge
|
||||||
|
assert bool(query_response_error)
|
||||||
|
|
||||||
|
yield delay(100)
|
||||||
|
|
||||||
|
raise StopSimulation
|
||||||
|
|
||||||
|
return dut, clkgen, check
|
||||||
|
|
||||||
|
def test_bench():
|
||||||
|
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
||||||
|
sim = Simulation(bench())
|
||||||
|
sim.run()
|
||||||
|
|
||||||
|
if __name__ == '__main__':
|
||||||
|
print("Running test...")
|
||||||
|
test_bench()
|
||||||
|
|
97
tb/test_arp_cache.v
Executable file
97
tb/test_arp_cache.v
Executable file
@ -0,0 +1,97 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014 Alex Forencich
|
||||||
|
|
||||||
|
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
of this software and associated documentation files (the "Software"), to deal
|
||||||
|
in the Software without restriction, including without limitation the rights
|
||||||
|
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
copies of the Software, and to permit persons to whom the Software is
|
||||||
|
furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
|
The above copyright notice and this permission notice shall be included in
|
||||||
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||||
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||||
|
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
THE SOFTWARE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
// Language: Verilog 2001
|
||||||
|
|
||||||
|
`timescale 1 ns / 1 ps
|
||||||
|
|
||||||
|
module test_arp_cache;
|
||||||
|
|
||||||
|
// Inputs
|
||||||
|
reg clk = 0;
|
||||||
|
reg rst = 0;
|
||||||
|
reg [7:0] current_test = 0;
|
||||||
|
|
||||||
|
reg query_request_valid = 0;
|
||||||
|
reg [31:0] query_request_ip = 0;
|
||||||
|
|
||||||
|
reg write_request_valid = 0;
|
||||||
|
reg [31:0] write_request_ip = 0;
|
||||||
|
reg [47:0] write_request_mac = 0;
|
||||||
|
|
||||||
|
reg clear_cache = 0;
|
||||||
|
|
||||||
|
// Outputs
|
||||||
|
wire query_response_valid;
|
||||||
|
wire query_response_error;
|
||||||
|
wire [47:0] query_response_mac;
|
||||||
|
|
||||||
|
wire write_in_progress;
|
||||||
|
wire write_complete;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
// myhdl integration
|
||||||
|
$from_myhdl(clk,
|
||||||
|
rst,
|
||||||
|
current_test,
|
||||||
|
query_request_valid,
|
||||||
|
query_request_ip,
|
||||||
|
write_request_valid,
|
||||||
|
write_request_ip,
|
||||||
|
write_request_mac,
|
||||||
|
clear_cache);
|
||||||
|
$to_myhdl(query_response_valid,
|
||||||
|
query_response_error,
|
||||||
|
query_response_mac,
|
||||||
|
write_in_progress,
|
||||||
|
write_complete);
|
||||||
|
|
||||||
|
// dump file
|
||||||
|
$dumpfile("test_arp_cache.lxt");
|
||||||
|
$dumpvars(0, test_arp_cache);
|
||||||
|
end
|
||||||
|
|
||||||
|
arp_cache #(
|
||||||
|
.CACHE_ADDR_WIDTH(2)
|
||||||
|
)
|
||||||
|
UUT (
|
||||||
|
.clk(clk),
|
||||||
|
.rst(rst),
|
||||||
|
// Query cache
|
||||||
|
.query_request_valid(query_request_valid),
|
||||||
|
.query_request_ip(query_request_ip),
|
||||||
|
.query_response_valid(query_response_valid),
|
||||||
|
.query_response_error(query_response_error),
|
||||||
|
.query_response_mac(query_response_mac),
|
||||||
|
// Write cache
|
||||||
|
.write_request_valid(write_request_valid),
|
||||||
|
.write_request_ip(write_request_ip),
|
||||||
|
.write_request_mac(write_request_mac),
|
||||||
|
.write_in_progress(write_in_progress),
|
||||||
|
.write_complete(write_complete),
|
||||||
|
// Configuration
|
||||||
|
.clear_cache(clear_cache)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
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Reference in New Issue
Block a user