FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master

Browse Source 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
This commit is contained in:
Joachim Foerster 2021-11-16 10:47:25 +01:00
parent 62879ff3ea
commit 80d5bda23f
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
View File

@ -150,7 +150,11 @@ dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_mm]
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_PIPELINE "2"
dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm]
# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface
# pin) yields 256 for the maximum burst length, instead of 16, which is
# the actually supported length (due to ZynqMP using AXI3 internally).
#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm]
dict set params AXI_DMA_MAX_BURST_LEN "16"
# AXI lite interface configuration (control)
set m_axil_0 [get_bd_intf_pins /axi_protocol_convert_0/M_AXI]