From 80d5bda23f431e6159586154e8fbffeda7295590 Mon Sep 17 00:00:00 2001 From: Joachim Foerster Date: Tue, 16 Nov 2021 10:47:25 +0100 Subject: [PATCH] ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master Signed-off-by: Joachim Foerster --- fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index 80d696539..a81389024 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -150,7 +150,11 @@ dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_mm] dict set params DMA_LEN_WIDTH "16" dict set params DMA_TAG_WIDTH "16" dict set params RAM_PIPELINE "2" -dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm] +# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface +# pin) yields 256 for the maximum burst length, instead of 16, which is +# the actually supported length (due to ZynqMP using AXI3 internally). +#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm] +dict set params AXI_DMA_MAX_BURST_LEN "16" # AXI lite interface configuration (control) set m_axil_0 [get_bd_intf_pins /axi_protocol_convert_0/M_AXI]