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Update testbenches

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This commit is contained in:
Alex Forencich 2019-08-13 00:39:28 -07:00
parent d99f40db08
commit 80f06e1fcc
8 changed files with 108 additions and 108 deletions
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4
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -844,8 +844,8 @@ def bench():
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

4
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -657,8 +657,8 @@ def bench():
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

4
fpga/mqnic/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -728,8 +728,8 @@ def bench():
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

4
fpga/mqnic/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -845,8 +845,8 @@ def bench():
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

50
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
View File

@ -844,8 +844,8 @@ def bench():
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
@ -963,34 +963,34 @@ def bench():
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00100, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00100, 0x00000001)
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00200, 0xffffffff)
# disable global enable
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00300, 0x00000000)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00300, 0x00000000)
# configure slots
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

50
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -657,8 +657,8 @@ def bench():
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
@ -756,34 +756,34 @@ def bench():
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00100, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00100, 0x00000001)
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00200, 0xffffffff)
# disable global enable
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00300, 0x00000000)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00300, 0x00000000)
# configure slots
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

50
fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py
View File

@ -728,8 +728,8 @@ def bench():
yield from driver.interfaces[0].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
@ -827,34 +827,34 @@ def bench():
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00100, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00100, 0x00000001)
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00200, 0xffffffff)
# disable global enable
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00300, 0x00000000)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00300, 0x00000000)
# configure slots
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete

50
fpga/mqnic_tdma/VCU118/fpga_10g/tb/test_fpga_core.py
View File

@ -845,8 +845,8 @@ def bench():
#yield from driver.interfaces[1].open()
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0300, 0xffffffff)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
@ -964,34 +964,34 @@ def bench():
# configure TDMA
# configure TDMA scheduler
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00100, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00120, 0) # schedule period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00124, 40000) # schedule period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00128, 0) # schedule period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0012c, 0) # schedule period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00130, 0) # timeslot period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00134, 10000) # timeslot period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00138, 0) # timeslot period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0013c, 0) # timeslot period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00140, 0) # active period fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00144, 5000) # active period ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00148, 0) # active period sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0014c, 0) # active period sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00110, 0) # schedule start fns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00114, 200000) # schedule start ns
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00118, 0) # schedule start sec (low)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x0011c, 0) # schedule start sec (high)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00100, 0x00000001)
# enable queues
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00200, 0xffffffff)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00200, 0xffffffff)
# disable global enable
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00300, 0x00000000)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x00300, 0x00000000)
# configure slots
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10000, 0x00000001)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10100, 0x00000002)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10200, 0x00000004)
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+0x10300, 0x00000008)
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete