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Add ExaNIC X10 example design
This commit is contained in:
Alex Forencich
parent
8b8cfd96fd
commit
82454e4ae1
25
example/ExaNIC_X10/fpga/Makefile
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25
example/ExaNIC_X10/fpga/Makefile
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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26
example/ExaNIC_X10/fpga/README.md
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example/ExaNIC_X10/fpga/README.md
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# Verilog Ethernet ExaNIC X10 Example Design
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## Introduction
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This example design targets the Exablaze ExaNIC X10 FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests. The design also enables the gigabit Ethernet interface for
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testing with a QSFP loopback adapter.
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FPGA: xcku035-fbva676-2-c
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PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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## How to test
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Run make program to program the ExaNIC X10 board with Vivado. Then run
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netcat -u 192.168.1.128 1234 to open a UDP connection to port 1234. Any text
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entered into netcat will be echoed back after pressing enter.
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118
example/ExaNIC_X10/fpga/common/vivado.mk
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118
example/ExaNIC_X10/fpga/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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155
example/ExaNIC_X10/fpga/fpga.xdc
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155
example/ExaNIC_X10/fpga/fpga.xdc
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# XDC constraints for the ExaNIC X10
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# part: xcku035-fbva676-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
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set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
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set_property CONFIG_MODE BPI16 [current_design]
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# 100 MHz system clock
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set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p]
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set_property -dict {LOC C18 IOSTANDARD LVDS} [get_ports clk_100mhz_n]
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create_clock -period 10 -name clk_100mhz [get_ports clk_100mhz_p]
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set_clock_groups -asynchronous -group [get_clocks clk_100mhz -include_generated_clocks]
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# LEDs
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set_property -dict {LOC A25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
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set_property -dict {LOC A24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
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set_property -dict {LOC E23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
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set_property -dict {LOC D26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
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set_property -dict {LOC C23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
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set_property -dict {LOC D23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
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# GPIO
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#set_property -dict {LOC W26 IOSTANDARD LVCMOS18} [get_ports gpio[0]]
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#set_property -dict {LOC Y26 IOSTANDARD LVCMOS18} [get_ports gpio[1]]
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#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18} [get_ports gpio[2]]
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#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18} [get_ports gpio[3]]
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# SMA
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#set_property -dict {LOC B17 IOSTANDARD LVCMOS18} [get_ports sma_in]
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#set_property -dict {LOC B16 IOSTANDARD LVCMOS18} [get_ports sma_out]
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#set_property -dict {LOC B19 IOSTANDARD LVCMOS18} [get_ports sma_out_en]
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#set_property -dict {LOC C16 IOSTANDARD LVCMOS18} [get_ports sma_term_en]
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# SFP+ Interface
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set_property -dict {LOC D2 } [get_ports sfp_1_rx_p] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
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#set_property -dict {LOC D1 } [get_ports sfp_1_rx_n] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
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set_property -dict {LOC E4 } [get_ports sfp_1_tx_p] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
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#set_property -dict {LOC E3 } [get_ports sfp_1_tx_n] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3
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set_property -dict {LOC C4 } [get_ports sfp_2_rx_p] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
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#set_property -dict {LOC C3 } [get_ports sfp_2_rx_n] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
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set_property -dict {LOC D6 } [get_ports sfp_2_tx_p] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
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#set_property -dict {LOC D5 } [get_ports sfp_2_tx_n] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3
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set_property -dict {LOC H6 } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
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#set_property -dict {LOC H5 } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
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set_property -dict {LOC AA12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
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set_property -dict {LOC W14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
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set_property -dict {LOC C24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_npres]
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set_property -dict {LOC D24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_npres]
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set_property -dict {LOC W13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
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set_property -dict {LOC AB12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
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set_property -dict {LOC B25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
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set_property -dict {LOC D25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
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#set_property -dict {LOC W11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
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#set_property -dict {LOC Y11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
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#set_property -dict {LOC Y13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
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set_clock_groups -asynchronous -group [get_clocks sfp_mgt_refclk -include_generated_clocks]
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# I2C interface
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#set_property -dict {LOC B26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
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#set_property -dict {LOC C26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
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# PCIe Interface
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#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AF6 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AF5 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AD6 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AD5 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AC4 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AC3 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AB6 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC AB5 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
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#set_property -dict {LOC Y2 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC Y1 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC AA4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC AA3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC V2 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC V1 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC W4 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC W3 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC T2 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC T1 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC U4 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC U3 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC P2 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC P1 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC R4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC R3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
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#set_property -dict {LOC T6 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225
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#set_property -dict {LOC T5 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225
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#set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
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# 100 MHz MGT reference clock
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#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p]
|
||||
#set_clock_groups -asynchronous -group [get_clocks pcie_mgt_refclk -include_generated_clocks]
|
||||
|
||||
# Flash
|
||||
#set_property -dict {LOC AE10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[0]}]
|
||||
#set_property -dict {LOC AC8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[1]}]
|
||||
#set_property -dict {LOC AD10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[2]}]
|
||||
#set_property -dict {LOC AD9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[3]}]
|
||||
#set_property -dict {LOC AC11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[4]}]
|
||||
#set_property -dict {LOC AF10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[5]}]
|
||||
#set_property -dict {LOC AF14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[6]}]
|
||||
#set_property -dict {LOC AE12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[7]}]
|
||||
#set_property -dict {LOC AD14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[8]}]
|
||||
#set_property -dict {LOC AF13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[9]}]
|
||||
#set_property -dict {LOC AE13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[10]}]
|
||||
#set_property -dict {LOC AD8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[11]}]
|
||||
#set_property -dict {LOC AC13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[12]}]
|
||||
#set_property -dict {LOC AD13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[13]}]
|
||||
#set_property -dict {LOC AA14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[14]}]
|
||||
#set_property -dict {LOC AB15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_dq[15]}]
|
||||
#set_property -dict {LOC AD11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[0]}]
|
||||
#set_property -dict {LOC AE11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[1]}]
|
||||
#set_property -dict {LOC AF12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[2]}]
|
||||
#set_property -dict {LOC AB11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[3]}]
|
||||
#set_property -dict {LOC AB9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[4]}]
|
||||
#set_property -dict {LOC AB14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[5]}]
|
||||
#set_property -dict {LOC AA10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[6]}]
|
||||
#set_property -dict {LOC AA9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[7]}]
|
||||
#set_property -dict {LOC W10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[8]}]
|
||||
#set_property -dict {LOC AA13 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[9]}]
|
||||
#set_property -dict {LOC Y15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[10]}]
|
||||
#set_property -dict {LOC AC12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[11]}]
|
||||
#set_property -dict {LOC V12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[12]}]
|
||||
#set_property -dict {LOC V11 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[13]}]
|
||||
#set_property -dict {LOC Y12 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[14]}]
|
||||
#set_property -dict {LOC W9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[15]}]
|
||||
#set_property -dict {LOC Y8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[16]}]
|
||||
#set_property -dict {LOC W8 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[17]}]
|
||||
#set_property -dict {LOC W15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[18]}]
|
||||
#set_property -dict {LOC AA15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[19]}]
|
||||
#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[20]}]
|
||||
#set_property -dict {LOC AF15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[21]}]
|
||||
#set_property -dict {LOC AE15 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_addr[22]}]
|
||||
#set_property -dict {LOC AD15 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
|
||||
#set_property -dict {LOC AC9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_ce_n}]
|
||||
#set_property -dict {LOC AC14 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_oe_n}]
|
||||
#set_property -dict {LOC AB10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_we_n}]
|
||||
#set_property -dict {LOC Y10 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {flash_adv_n}]
|
||||
58
example/ExaNIC_X10/fpga/fpga/Makefile
Normal file
58
example/ExaNIC_X10/fpga/fpga/Makefile
Normal file
@ -0,0 +1,58 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku035-fbva676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexu
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_reset.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp_64.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
|
||||
# IP
|
||||
XCI_FILES = ip/gtwizard_ultrascale_0.xci
|
||||
XCI_FILES += ip/ten_gig_eth_pcs_pma_0.xci
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "program_hw_devices [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -mode batch -source program.tcl
|
||||
|
||||
1401
example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci
Normal file
1401
example/ExaNIC_X10/fpga/ip/gtwizard_ultrascale_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
132
example/ExaNIC_X10/fpga/ip/ten_gig_eth_pcs_pma_0.xci
Normal file
132
example/ExaNIC_X10/fpga/ip/ten_gig_eth_pcs_pma_0.xci
Normal file
@ -0,0 +1,132 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>ten_gig_eth_pcs_pma_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xxv_ethernet" spirit:version="2.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ANLT_CLK_IN_MHZ">75</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASE_R_KR">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCKING">Asynchronous</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINE_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TIME_STAMPING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY_CHK">kintexu</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAST_SIM_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DRP_CLK">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_GROUP_SELECT">Quad X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_LOCATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_REF_CLK_FREQ">161.1328125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_TYPE">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_USER_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE1_GT_LOC">X0Y12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE2_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE3_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE4_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LINE_RATE">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_CORES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_CLOCKING_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PTP_OPERATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RUNTIME_SWITCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_LATENCY_ADJUST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_TOTAL_BYTES_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XGMII_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_BOARD_PROJECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ANLT_CLK_IN_MHZ">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASE_R_KR">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCKING">Asynchronous</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ten_gig_eth_pcs_pma_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PIPELINE_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TIME_STAMPING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TX_FLOW_CONTROL_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAST_SIM_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DRP_CLK">125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_GROUP_SELECT">Quad_X0Y3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_LOCATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ">161.1328125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_TYPE">GTH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AUTO_NEG_LT_LOGIC">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_AXI4_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_FEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_RSFEC_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE1_GT_LOC">X0Y12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE2_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE3_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LANE4_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LINE_RATE">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_CORES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_CLOCKING_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PTP_OPERATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUNTIME_SWITCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TX_LATENCY_ADJUST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XGMII_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintexu</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xcku035</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbva676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.2.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BASE_R_KR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CORE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_DRP_CLK" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_GROUP_SELECT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_LOCATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.GT_REF_CLK_FREQ" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_SHARED_LOGIC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.INCLUDE_USER_FIFO" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE1_GT_LOC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE2_GT_LOC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE3_GT_LOC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE4_GT_LOC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_CORES" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
1
example/ExaNIC_X10/fpga/lib/eth
Symbolic link
1
example/ExaNIC_X10/fpga/lib/eth
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../
|
||||
553
example/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
553
example/ExaNIC_X10/fpga/rtl/fpga.v
Normal file
@ -0,0 +1,553 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga (
|
||||
/*
|
||||
* Clock: 100MHz LVDS
|
||||
*/
|
||||
input wire clk_100mhz_p,
|
||||
input wire clk_100mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] sfp_1_led,
|
||||
output wire [1:0] sfp_2_led,
|
||||
output wire [1:0] sma_led,
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
input wire sfp_1_rx_p,
|
||||
input wire sfp_1_rx_n,
|
||||
output wire sfp_1_tx_p,
|
||||
output wire sfp_1_tx_n,
|
||||
input wire sfp_2_rx_p,
|
||||
input wire sfp_2_rx_n,
|
||||
output wire sfp_2_tx_p,
|
||||
output wire sfp_2_tx_n,
|
||||
input wire sfp_mgt_refclk_p,
|
||||
input wire sfp_mgt_refclk_n,
|
||||
output wire sfp_1_tx_disable,
|
||||
output wire sfp_2_tx_disable,
|
||||
input wire sfp_1_npres,
|
||||
input wire sfp_2_npres,
|
||||
input wire sfp_1_los,
|
||||
input wire sfp_2_los,
|
||||
output wire sfp_1_rs,
|
||||
output wire sfp_2_rs
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_100mhz_ibufg;
|
||||
wire clk_125mhz_mmcm_out;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 156.25 MHz clock
|
||||
wire clk_156mhz_int;
|
||||
wire rst_156mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_100mhz_ibufg_inst (
|
||||
.O (clk_100mhz_ibufg),
|
||||
.I (clk_100mhz_p),
|
||||
.IB (clk_100mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
// 100 MHz in, 125 MHz out
|
||||
// PFD range: 10 MHz to 500 MHz
|
||||
// VCO range: 600 MHz to 1440 MHz
|
||||
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
|
||||
// Divide by 8 to get output frequency of 125 MHz
|
||||
MMCME3_BASE #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKOUT0_DIVIDE_F(8),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
.CLKFBOUT_MULT_F(10),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
.DIVCLK_DIVIDE(1),
|
||||
.REF_JITTER1(0.010),
|
||||
.CLKIN1_PERIOD(8.0),
|
||||
.STARTUP_WAIT("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
.CLKIN1(clk_100mhz_ibufg),
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.RST(mmcm_rst),
|
||||
.PWRDWN(1'b0),
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.CLKOUT6(),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.sync_reset_out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [1:0] sfp_1_led_int;
|
||||
wire [1:0] sfp_2_led_int;
|
||||
wire [1:0] sma_led_int;
|
||||
|
||||
// XGMII 10G PHY
|
||||
|
||||
assign sfp_1_tx_disable = 1'b0;
|
||||
assign sfp_2_tx_disable = 1'b0;
|
||||
assign sfp_1_rs = 1'b1;
|
||||
assign sfp_2_rs = 1'b1;
|
||||
|
||||
wire sfp_1_tx_clk_int = clk_156mhz_int;
|
||||
wire sfp_1_tx_rst_int = rst_156mhz_int;
|
||||
wire [63:0] sfp_1_txd_int;
|
||||
wire [7:0] sfp_1_txc_int;
|
||||
wire sfp_1_rx_clk_int = clk_156mhz_int;
|
||||
wire sfp_1_rx_rst_int = rst_156mhz_int;
|
||||
wire [63:0] sfp_1_rxd_int;
|
||||
wire [7:0] sfp_1_rxc_int;
|
||||
wire sfp_2_tx_clk_int = clk_156mhz_int;
|
||||
wire sfp_2_tx_rst_int = rst_156mhz_int;
|
||||
wire [63:0] sfp_2_txd_int;
|
||||
wire [7:0] sfp_2_txc_int;
|
||||
wire sfp_2_rx_clk_int = clk_156mhz_int;
|
||||
wire sfp_2_rx_rst_int = rst_156mhz_int;
|
||||
wire [63:0] sfp_2_rxd_int;
|
||||
wire [7:0] sfp_2_rxc_int;
|
||||
|
||||
wire sfp_1_rx_block_lock;
|
||||
wire sfp_2_rx_block_lock;
|
||||
|
||||
wire sfp_mgt_refclk;
|
||||
|
||||
wire [1:0] gt_txclkout;
|
||||
wire gt_txusrclk;
|
||||
wire gt_txusrclk2;
|
||||
|
||||
wire [1:0] gt_rxclkout;
|
||||
wire [1:0] gt_rxusrclk;
|
||||
wire [1:0] gt_rxusrclk2;
|
||||
|
||||
wire gt_reset_tx_done;
|
||||
wire gt_reset_rx_done;
|
||||
|
||||
wire [1:0] gt_txprgdivresetdone;
|
||||
wire [1:0] gt_txpmaresetdone;
|
||||
wire [1:0] gt_rxprgdivresetdone;
|
||||
wire [1:0] gt_rxpmaresetdone;
|
||||
|
||||
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
|
||||
wire gt_rx_reset = ~>_rxpmaresetdone;
|
||||
|
||||
reg gt_userclk_tx_active = 1'b0;
|
||||
reg [1:0] gt_userclk_rx_active = 1'b0;
|
||||
|
||||
IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_inst (
|
||||
.I (sfp_mgt_refclk_p),
|
||||
.IB (sfp_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (sfp_mgt_refclk),
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_tx_usrclk2_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_tx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd1),
|
||||
.I (gt_txclkout[0]),
|
||||
.O (gt_txusrclk2)
|
||||
);
|
||||
|
||||
assign clk_156mhz_int = gt_txusrclk2;
|
||||
|
||||
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
|
||||
if (gt_tx_reset) begin
|
||||
gt_userclk_tx_active <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_tx_active <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
genvar n;
|
||||
|
||||
generate
|
||||
|
||||
for (n = 0 ; n < 2; n = n + 1) begin
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk_0_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd0),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk[n])
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_rx_usrclk2_0_inst (
|
||||
.CE (1'b1),
|
||||
.CEMASK (1'b0),
|
||||
.CLR (gt_rx_reset),
|
||||
.CLRMASK (1'b0),
|
||||
.DIV (3'd1),
|
||||
.I (gt_rxclkout[n]),
|
||||
.O (gt_rxusrclk2[n])
|
||||
);
|
||||
|
||||
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
|
||||
if (gt_rx_reset) begin
|
||||
gt_userclk_rx_active[n] <= 1'b0;
|
||||
end else begin
|
||||
gt_userclk_rx_active[n] <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_156mhz_inst (
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(~gt_reset_tx_done),
|
||||
.sync_reset_out(rst_156mhz_int)
|
||||
);
|
||||
|
||||
wire [5:0] sfp_1_gt_txheader;
|
||||
wire [127:0] sfp_1_gt_txdata;
|
||||
wire sfp_1_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_1_gt_rxheader;
|
||||
wire [1:0] sfp_1_gt_rxheadervalid;
|
||||
wire [127:0] sfp_1_gt_rxdata;
|
||||
wire [1:0] sfp_1_gt_rxdatavalid;
|
||||
|
||||
wire [5:0] sfp_2_gt_txheader;
|
||||
wire [127:0] sfp_2_gt_txdata;
|
||||
wire sfp_2_gt_rxgearboxslip;
|
||||
wire [5:0] sfp_2_gt_rxheader;
|
||||
wire [1:0] sfp_2_gt_rxheadervalid;
|
||||
wire [127:0] sfp_2_gt_rxdata;
|
||||
wire [1:0] sfp_2_gt_rxdatavalid;
|
||||
|
||||
gtwizard_ultrascale_0
|
||||
sfp_gth_inst (
|
||||
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
|
||||
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
|
||||
|
||||
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
|
||||
.gtwiz_reset_all_in(rst_125mhz_int),
|
||||
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(1'b0),
|
||||
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
|
||||
.gtrefclk00_in(sfp_mgt_refclk),
|
||||
|
||||
.qpll0outclk_out(),
|
||||
.qpll0outrefclk_out(),
|
||||
|
||||
.gthrxn_in({sfp_2_rx_n, sfp_1_rx_n}),
|
||||
.gthrxp_in({sfp_2_rx_p, sfp_1_rx_p}),
|
||||
|
||||
.rxusrclk_in(gt_rxusrclk),
|
||||
.rxusrclk2_in(gt_rxusrclk2),
|
||||
|
||||
.txdata_in({sfp_2_gt_txdata, sfp_1_gt_txdata}),
|
||||
.txheader_in({sfp_2_gt_txheader, sfp_1_gt_txheader}),
|
||||
.txsequence_in({2{7'b0}}),
|
||||
|
||||
.txusrclk_in({2{gt_txusrclk}}),
|
||||
.txusrclk2_in({2{gt_txusrclk2}}),
|
||||
|
||||
.gtpowergood_out(),
|
||||
|
||||
.gthtxn_out({sfp_2_tx_n, sfp_1_tx_n}),
|
||||
.gthtxp_out({sfp_2_tx_p, sfp_1_tx_p}),
|
||||
|
||||
.txpolarity_in(2'b11),
|
||||
.rxpolarity_in(2'b00),
|
||||
|
||||
.rxgearboxslip_in({sfp_2_gt_rxgearboxslip, sfp_1_gt_rxgearboxslip}),
|
||||
.rxdata_out({sfp_2_gt_rxdata, sfp_1_gt_rxdata}),
|
||||
.rxdatavalid_out({sfp_2_gt_rxdatavalid, sfp_1_gt_rxdatavalid}),
|
||||
.rxheader_out({sfp_2_gt_rxheader, sfp_1_gt_rxheader}),
|
||||
.rxheadervalid_out({sfp_2_gt_rxheadervalid, sfp_1_gt_rxheadervalid}),
|
||||
.rxoutclk_out(gt_rxclkout),
|
||||
.rxpmaresetdone_out(gt_rxpmaresetdone),
|
||||
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
|
||||
.rxstartofseq_out(),
|
||||
|
||||
.txoutclk_out(gt_txclkout),
|
||||
.txpmaresetdone_out(gt_txpmaresetdone),
|
||||
.txprgdivresetdone_out(gt_txprgdivresetdone)
|
||||
);
|
||||
|
||||
wire sfp_1_serdes_reset;
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_1_pcs_pma_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[0]),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_1_serdes_reset)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
sfp_pcs_pma_1 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(sfp_1_rxd_int),
|
||||
.rx_mii_c_0(sfp_1_rxc_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(sfp_1_rx_block_lock),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(sfp_1_txd_int),
|
||||
.tx_mii_c_0(sfp_1_txc_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTH interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk2[0]),
|
||||
.rx_serdes_reset_0(sfp_1_serdes_reset),
|
||||
.rxgearboxslip_in_0(sfp_1_gt_rxgearboxslip),
|
||||
.rxdatavalid_out_0(sfp_1_gt_rxdatavalid),
|
||||
.rxheader_out_0(sfp_1_gt_rxheader),
|
||||
.rxheadervalid_out_0(sfp_1_gt_rxheadervalid),
|
||||
.rx_serdes_data_out_0(sfp_1_gt_rxdata),
|
||||
.tx_serdes_data_in_0(sfp_1_gt_txdata),
|
||||
.txheader_in_0(sfp_1_gt_txheader)
|
||||
);
|
||||
|
||||
wire sfp_2_serdes_reset;
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sfp_2_pcs_pma_rx_serdes_reset_sync_inst (
|
||||
.clk(gt_rxusrclk[1]),
|
||||
.rst(~gt_reset_rx_done),
|
||||
.sync_reset_out(sfp_2_serdes_reset)
|
||||
);
|
||||
|
||||
ten_gig_eth_pcs_pma_0
|
||||
sfp_pcs_pma_2 (
|
||||
.rx_reset_0(rst_156mhz_int),
|
||||
.rx_mii_d_0(sfp_2_rxd_int),
|
||||
.rx_mii_c_0(sfp_2_rxc_int),
|
||||
|
||||
.ctl_rx_test_pattern_0(1'b0),
|
||||
.ctl_rx_test_pattern_enable_0(1'b0),
|
||||
.ctl_rx_data_pattern_select_0(1'b0),
|
||||
.ctl_rx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_rx_block_lock_0(sfp_2_rx_block_lock),
|
||||
.stat_rx_framing_err_valid_0(),
|
||||
.stat_rx_framing_err_0(),
|
||||
.stat_rx_hi_ber_0(),
|
||||
.stat_rx_valid_ctrl_code_0(),
|
||||
.stat_rx_bad_code_0(),
|
||||
.stat_rx_bad_code_valid_0(),
|
||||
.stat_rx_error_valid_0(),
|
||||
.stat_rx_error_0(),
|
||||
.stat_rx_fifo_error_0(),
|
||||
.stat_rx_local_fault_0(),
|
||||
.stat_rx_status_0(),
|
||||
|
||||
.tx_reset_0(rst_156mhz_int),
|
||||
.tx_mii_d_0(sfp_2_txd_int),
|
||||
.tx_mii_c_0(sfp_2_txc_int),
|
||||
|
||||
.ctl_tx_test_pattern_0(1'b0),
|
||||
.ctl_tx_test_pattern_enable_0(1'b0),
|
||||
.ctl_tx_test_pattern_select_0(1'b0),
|
||||
.ctl_tx_data_pattern_select_0(1'b0),
|
||||
.ctl_tx_test_pattern_seed_a_0(58'd0),
|
||||
.ctl_tx_test_pattern_seed_b_0(58'd0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0(1'b0),
|
||||
|
||||
.stat_tx_local_fault_0(),
|
||||
|
||||
// GTH interface
|
||||
.tx_core_clk_0(clk_156mhz_int),
|
||||
.rx_core_clk_0(clk_156mhz_int),
|
||||
.rx_serdes_clk_0(gt_rxusrclk2[1]),
|
||||
.rx_serdes_reset_0(sfp_2_serdes_reset),
|
||||
.rxgearboxslip_in_0(sfp_2_gt_rxgearboxslip),
|
||||
.rxdatavalid_out_0(sfp_2_gt_rxdatavalid),
|
||||
.rxheader_out_0(sfp_2_gt_rxheader),
|
||||
.rxheadervalid_out_0(sfp_2_gt_rxheadervalid),
|
||||
.rx_serdes_data_out_0(sfp_2_gt_rxdata),
|
||||
.tx_serdes_data_in_0(sfp_2_gt_txdata),
|
||||
.txheader_in_0(sfp_2_gt_txheader)
|
||||
);
|
||||
|
||||
assign sfp_1_led[0] = sfp_1_rx_block_lock;
|
||||
assign sfp_1_led[1] = 1'b0;
|
||||
assign sfp_2_led[0] = sfp_2_rx_block_lock;
|
||||
assign sfp_2_led[1] = 1'b0;
|
||||
assign sma_led = sma_led_int;
|
||||
|
||||
fpga_core
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 156.25 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(rst_156mhz_int),
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sfp_1_led(sfp_1_led_int),
|
||||
.sfp_2_led(sfp_2_led_int),
|
||||
.sma_led(sma_led_int),
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk_int),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst_int),
|
||||
.sfp_1_txd(sfp_1_txd_int),
|
||||
.sfp_1_txc(sfp_1_txc_int),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk_int),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst_int),
|
||||
.sfp_1_rxd(sfp_1_rxd_int),
|
||||
.sfp_1_rxc(sfp_1_rxc_int),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk_int),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst_int),
|
||||
.sfp_2_txd(sfp_2_txd_int),
|
||||
.sfp_2_txc(sfp_2_txc_int),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk_int),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst_int),
|
||||
.sfp_2_rxd(sfp_2_rxd_int),
|
||||
.sfp_2_rxc(sfp_2_rxc_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
588
example/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
588
example/ExaNIC_X10/fpga/rtl/fpga_core.v
Normal file
@ -0,0 +1,588 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core
|
||||
(
|
||||
/*
|
||||
* Clock: 156.25MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [1:0] sfp_1_led,
|
||||
output wire [1:0] sfp_2_led,
|
||||
output wire [1:0] sma_led,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire sfp_1_tx_clk,
|
||||
input wire sfp_1_tx_rst,
|
||||
output wire [63:0] sfp_1_txd,
|
||||
output wire [7:0] sfp_1_txc,
|
||||
input wire sfp_1_rx_clk,
|
||||
input wire sfp_1_rx_rst,
|
||||
input wire [63:0] sfp_1_rxd,
|
||||
input wire [7:0] sfp_1_rxc,
|
||||
input wire sfp_2_tx_clk,
|
||||
input wire sfp_2_tx_rst,
|
||||
output wire [63:0] sfp_2_txd,
|
||||
output wire [7:0] sfp_2_txc,
|
||||
input wire sfp_2_rx_clk,
|
||||
input wire sfp_2_rx_rst,
|
||||
input wire [63:0] sfp_2_rxd,
|
||||
input wire [7:0] sfp_2_rxc
|
||||
);
|
||||
|
||||
// AXI between MAC and Ethernet modules
|
||||
wire [63:0] rx_axis_tdata;
|
||||
wire [7:0] rx_axis_tkeep;
|
||||
wire rx_axis_tvalid;
|
||||
wire rx_axis_tready;
|
||||
wire rx_axis_tlast;
|
||||
wire rx_axis_tuser;
|
||||
|
||||
wire [63:0] tx_axis_tdata;
|
||||
wire [7:0] tx_axis_tkeep;
|
||||
wire tx_axis_tvalid;
|
||||
wire tx_axis_tready;
|
||||
wire tx_axis_tlast;
|
||||
wire tx_axis_tuser;
|
||||
|
||||
// Ethernet frame between Ethernet modules and UDP stack
|
||||
wire rx_eth_hdr_ready;
|
||||
wire rx_eth_hdr_valid;
|
||||
wire [47:0] rx_eth_dest_mac;
|
||||
wire [47:0] rx_eth_src_mac;
|
||||
wire [15:0] rx_eth_type;
|
||||
wire [63:0] rx_eth_payload_axis_tdata;
|
||||
wire [7:0] rx_eth_payload_axis_tkeep;
|
||||
wire rx_eth_payload_axis_tvalid;
|
||||
wire rx_eth_payload_axis_tready;
|
||||
wire rx_eth_payload_axis_tlast;
|
||||
wire rx_eth_payload_axis_tuser;
|
||||
|
||||
wire tx_eth_hdr_ready;
|
||||
wire tx_eth_hdr_valid;
|
||||
wire [47:0] tx_eth_dest_mac;
|
||||
wire [47:0] tx_eth_src_mac;
|
||||
wire [15:0] tx_eth_type;
|
||||
wire [63:0] tx_eth_payload_axis_tdata;
|
||||
wire [7:0] tx_eth_payload_axis_tkeep;
|
||||
wire tx_eth_payload_axis_tvalid;
|
||||
wire tx_eth_payload_axis_tready;
|
||||
wire tx_eth_payload_axis_tlast;
|
||||
wire tx_eth_payload_axis_tuser;
|
||||
|
||||
// IP frame connections
|
||||
wire rx_ip_hdr_valid;
|
||||
wire rx_ip_hdr_ready;
|
||||
wire [47:0] rx_ip_eth_dest_mac;
|
||||
wire [47:0] rx_ip_eth_src_mac;
|
||||
wire [15:0] rx_ip_eth_type;
|
||||
wire [3:0] rx_ip_version;
|
||||
wire [3:0] rx_ip_ihl;
|
||||
wire [5:0] rx_ip_dscp;
|
||||
wire [1:0] rx_ip_ecn;
|
||||
wire [15:0] rx_ip_length;
|
||||
wire [15:0] rx_ip_identification;
|
||||
wire [2:0] rx_ip_flags;
|
||||
wire [12:0] rx_ip_fragment_offset;
|
||||
wire [7:0] rx_ip_ttl;
|
||||
wire [7:0] rx_ip_protocol;
|
||||
wire [15:0] rx_ip_header_checksum;
|
||||
wire [31:0] rx_ip_source_ip;
|
||||
wire [31:0] rx_ip_dest_ip;
|
||||
wire [63:0] rx_ip_payload_axis_tdata;
|
||||
wire [7:0] rx_ip_payload_axis_tkeep;
|
||||
wire rx_ip_payload_axis_tvalid;
|
||||
wire rx_ip_payload_axis_tready;
|
||||
wire rx_ip_payload_axis_tlast;
|
||||
wire rx_ip_payload_axis_tuser;
|
||||
|
||||
wire tx_ip_hdr_valid;
|
||||
wire tx_ip_hdr_ready;
|
||||
wire [5:0] tx_ip_dscp;
|
||||
wire [1:0] tx_ip_ecn;
|
||||
wire [15:0] tx_ip_length;
|
||||
wire [7:0] tx_ip_ttl;
|
||||
wire [7:0] tx_ip_protocol;
|
||||
wire [31:0] tx_ip_source_ip;
|
||||
wire [31:0] tx_ip_dest_ip;
|
||||
wire [63:0] tx_ip_payload_axis_tdata;
|
||||
wire [7:0] tx_ip_payload_axis_tkeep;
|
||||
wire tx_ip_payload_axis_tvalid;
|
||||
wire tx_ip_payload_axis_tready;
|
||||
wire tx_ip_payload_axis_tlast;
|
||||
wire tx_ip_payload_axis_tuser;
|
||||
|
||||
// UDP frame connections
|
||||
wire rx_udp_hdr_valid;
|
||||
wire rx_udp_hdr_ready;
|
||||
wire [47:0] rx_udp_eth_dest_mac;
|
||||
wire [47:0] rx_udp_eth_src_mac;
|
||||
wire [15:0] rx_udp_eth_type;
|
||||
wire [3:0] rx_udp_ip_version;
|
||||
wire [3:0] rx_udp_ip_ihl;
|
||||
wire [5:0] rx_udp_ip_dscp;
|
||||
wire [1:0] rx_udp_ip_ecn;
|
||||
wire [15:0] rx_udp_ip_length;
|
||||
wire [15:0] rx_udp_ip_identification;
|
||||
wire [2:0] rx_udp_ip_flags;
|
||||
wire [12:0] rx_udp_ip_fragment_offset;
|
||||
wire [7:0] rx_udp_ip_ttl;
|
||||
wire [7:0] rx_udp_ip_protocol;
|
||||
wire [15:0] rx_udp_ip_header_checksum;
|
||||
wire [31:0] rx_udp_ip_source_ip;
|
||||
wire [31:0] rx_udp_ip_dest_ip;
|
||||
wire [15:0] rx_udp_source_port;
|
||||
wire [15:0] rx_udp_dest_port;
|
||||
wire [15:0] rx_udp_length;
|
||||
wire [15:0] rx_udp_checksum;
|
||||
wire [63:0] rx_udp_payload_axis_tdata;
|
||||
wire [7:0] rx_udp_payload_axis_tkeep;
|
||||
wire rx_udp_payload_axis_tvalid;
|
||||
wire rx_udp_payload_axis_tready;
|
||||
wire rx_udp_payload_axis_tlast;
|
||||
wire rx_udp_payload_axis_tuser;
|
||||
|
||||
wire tx_udp_hdr_valid;
|
||||
wire tx_udp_hdr_ready;
|
||||
wire [5:0] tx_udp_ip_dscp;
|
||||
wire [1:0] tx_udp_ip_ecn;
|
||||
wire [7:0] tx_udp_ip_ttl;
|
||||
wire [31:0] tx_udp_ip_source_ip;
|
||||
wire [31:0] tx_udp_ip_dest_ip;
|
||||
wire [15:0] tx_udp_source_port;
|
||||
wire [15:0] tx_udp_dest_port;
|
||||
wire [15:0] tx_udp_length;
|
||||
wire [15:0] tx_udp_checksum;
|
||||
wire [63:0] tx_udp_payload_axis_tdata;
|
||||
wire [7:0] tx_udp_payload_axis_tkeep;
|
||||
wire tx_udp_payload_axis_tvalid;
|
||||
wire tx_udp_payload_axis_tready;
|
||||
wire tx_udp_payload_axis_tlast;
|
||||
wire tx_udp_payload_axis_tuser;
|
||||
|
||||
wire [63:0] rx_fifo_udp_payload_axis_tdata;
|
||||
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
|
||||
wire rx_fifo_udp_payload_axis_tvalid;
|
||||
wire rx_fifo_udp_payload_axis_tready;
|
||||
wire rx_fifo_udp_payload_axis_tlast;
|
||||
wire rx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
wire [63:0] tx_fifo_udp_payload_axis_tdata;
|
||||
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
|
||||
wire tx_fifo_udp_payload_axis_tvalid;
|
||||
wire tx_fifo_udp_payload_axis_tready;
|
||||
wire tx_fifo_udp_payload_axis_tlast;
|
||||
wire tx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
// Configuration
|
||||
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
|
||||
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
|
||||
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
|
||||
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
|
||||
|
||||
// IP ports not used
|
||||
assign rx_ip_hdr_ready = 1;
|
||||
assign rx_ip_payload_axis_tready = 1;
|
||||
|
||||
assign tx_ip_hdr_valid = 0;
|
||||
assign tx_ip_dscp = 0;
|
||||
assign tx_ip_ecn = 0;
|
||||
assign tx_ip_length = 0;
|
||||
assign tx_ip_ttl = 0;
|
||||
assign tx_ip_protocol = 0;
|
||||
assign tx_ip_source_ip = 0;
|
||||
assign tx_ip_dest_ip = 0;
|
||||
assign tx_ip_payload_axis_tdata = 0;
|
||||
assign tx_ip_payload_axis_tkeep = 0;
|
||||
assign tx_ip_payload_axis_tvalid = 0;
|
||||
assign tx_ip_payload_axis_tlast = 0;
|
||||
assign tx_ip_payload_axis_tuser = 0;
|
||||
|
||||
// Loop back UDP
|
||||
wire match_cond = rx_udp_dest_port == 1234;
|
||||
wire no_match = ~match_cond;
|
||||
|
||||
reg match_cond_reg = 0;
|
||||
reg no_match_reg = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
match_cond_reg <= 0;
|
||||
no_match_reg <= 0;
|
||||
end else begin
|
||||
if (rx_udp_payload_axis_tvalid) begin
|
||||
if ((~match_cond_reg & ~no_match_reg) |
|
||||
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
|
||||
match_cond_reg <= match_cond;
|
||||
no_match_reg <= no_match;
|
||||
end
|
||||
end else begin
|
||||
match_cond_reg <= 0;
|
||||
no_match_reg <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign tx_udp_hdr_valid = rx_udp_hdr_valid & match_cond;
|
||||
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
|
||||
assign tx_udp_ip_dscp = 0;
|
||||
assign tx_udp_ip_ecn = 0;
|
||||
assign tx_udp_ip_ttl = 64;
|
||||
assign tx_udp_ip_source_ip = local_ip;
|
||||
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
|
||||
assign tx_udp_source_port = rx_udp_dest_port;
|
||||
assign tx_udp_dest_port = rx_udp_source_port;
|
||||
assign tx_udp_length = rx_udp_length;
|
||||
assign tx_udp_checksum = 0;
|
||||
|
||||
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
|
||||
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
|
||||
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
|
||||
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
|
||||
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
|
||||
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
|
||||
|
||||
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
|
||||
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
|
||||
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
|
||||
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
|
||||
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
|
||||
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
|
||||
|
||||
// Place first payload byte onto LEDs
|
||||
reg valid_last = 0;
|
||||
reg [7:0] led_reg = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
led_reg <= 0;
|
||||
end else begin
|
||||
valid_last <= tx_udp_payload_axis_tvalid;
|
||||
if (tx_udp_payload_axis_tvalid & ~valid_last) begin
|
||||
led_reg <= tx_udp_payload_axis_tdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign led = led_reg;
|
||||
|
||||
assign sfp_2_txd = 64'h0707070707070707;
|
||||
assign sfp_2_txc = 8'hff;
|
||||
|
||||
eth_mac_10g_fifo #(
|
||||
.ENABLE_PADDING(1),
|
||||
.ENABLE_DIC(1),
|
||||
.MIN_FRAME_LENGTH(64),
|
||||
.TX_FIFO_ADDR_WIDTH(9),
|
||||
.RX_FIFO_ADDR_WIDTH(9)
|
||||
)
|
||||
eth_mac_10g_fifo_inst (
|
||||
.rx_clk(sfp_1_rx_clk),
|
||||
.rx_rst(sfp_1_rx_rst),
|
||||
.tx_clk(sfp_1_tx_clk),
|
||||
.tx_rst(sfp_1_tx_rst),
|
||||
.logic_clk(clk),
|
||||
.logic_rst(rst),
|
||||
|
||||
.tx_axis_tdata(tx_axis_tdata),
|
||||
.tx_axis_tkeep(tx_axis_tkeep),
|
||||
.tx_axis_tvalid(tx_axis_tvalid),
|
||||
.tx_axis_tready(tx_axis_tready),
|
||||
.tx_axis_tlast(tx_axis_tlast),
|
||||
.tx_axis_tuser(tx_axis_tuser),
|
||||
|
||||
.rx_axis_tdata(rx_axis_tdata),
|
||||
.rx_axis_tkeep(rx_axis_tkeep),
|
||||
.rx_axis_tvalid(rx_axis_tvalid),
|
||||
.rx_axis_tready(rx_axis_tready),
|
||||
.rx_axis_tlast(rx_axis_tlast),
|
||||
.rx_axis_tuser(rx_axis_tuser),
|
||||
|
||||
.xgmii_rxd(sfp_1_rxd),
|
||||
.xgmii_rxc(sfp_1_rxc),
|
||||
.xgmii_txd(sfp_1_txd),
|
||||
.xgmii_txc(sfp_1_txc),
|
||||
|
||||
.tx_fifo_overflow(),
|
||||
.tx_fifo_bad_frame(),
|
||||
.tx_fifo_good_frame(),
|
||||
.rx_error_bad_frame(),
|
||||
.rx_error_bad_fcs(),
|
||||
.rx_fifo_overflow(),
|
||||
.rx_fifo_bad_frame(),
|
||||
.rx_fifo_good_frame(),
|
||||
|
||||
.ifg_delay(8'd12)
|
||||
);
|
||||
|
||||
eth_axis_rx_64
|
||||
eth_axis_rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_axis_tdata),
|
||||
.s_axis_tkeep(rx_axis_tkeep),
|
||||
.s_axis_tvalid(rx_axis_tvalid),
|
||||
.s_axis_tready(rx_axis_tready),
|
||||
.s_axis_tlast(rx_axis_tlast),
|
||||
.s_axis_tuser(rx_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.m_eth_hdr_valid(rx_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(rx_eth_hdr_ready),
|
||||
.m_eth_dest_mac(rx_eth_dest_mac),
|
||||
.m_eth_src_mac(rx_eth_src_mac),
|
||||
.m_eth_type(rx_eth_type),
|
||||
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
||||
// Status signals
|
||||
.busy(),
|
||||
.error_header_early_termination()
|
||||
);
|
||||
|
||||
eth_axis_tx_64
|
||||
eth_axis_tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame input
|
||||
.s_eth_hdr_valid(tx_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(tx_eth_hdr_ready),
|
||||
.s_eth_dest_mac(tx_eth_dest_mac),
|
||||
.s_eth_src_mac(tx_eth_src_mac),
|
||||
.s_eth_type(tx_eth_type),
|
||||
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
||||
// AXI output
|
||||
.m_axis_tdata(tx_axis_tdata),
|
||||
.m_axis_tkeep(tx_axis_tkeep),
|
||||
.m_axis_tvalid(tx_axis_tvalid),
|
||||
.m_axis_tready(tx_axis_tready),
|
||||
.m_axis_tlast(tx_axis_tlast),
|
||||
.m_axis_tuser(tx_axis_tuser),
|
||||
// Status signals
|
||||
.busy()
|
||||
);
|
||||
|
||||
udp_complete_64
|
||||
udp_complete_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame input
|
||||
.s_eth_hdr_valid(rx_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(rx_eth_hdr_ready),
|
||||
.s_eth_dest_mac(rx_eth_dest_mac),
|
||||
.s_eth_src_mac(rx_eth_src_mac),
|
||||
.s_eth_type(rx_eth_type),
|
||||
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
|
||||
// Ethernet frame output
|
||||
.m_eth_hdr_valid(tx_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(tx_eth_hdr_ready),
|
||||
.m_eth_dest_mac(tx_eth_dest_mac),
|
||||
.m_eth_src_mac(tx_eth_src_mac),
|
||||
.m_eth_type(tx_eth_type),
|
||||
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
|
||||
// IP frame input
|
||||
.s_ip_hdr_valid(tx_ip_hdr_valid),
|
||||
.s_ip_hdr_ready(tx_ip_hdr_ready),
|
||||
.s_ip_dscp(tx_ip_dscp),
|
||||
.s_ip_ecn(tx_ip_ecn),
|
||||
.s_ip_length(tx_ip_length),
|
||||
.s_ip_ttl(tx_ip_ttl),
|
||||
.s_ip_protocol(tx_ip_protocol),
|
||||
.s_ip_source_ip(tx_ip_source_ip),
|
||||
.s_ip_dest_ip(tx_ip_dest_ip),
|
||||
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
|
||||
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
|
||||
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
|
||||
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
|
||||
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
|
||||
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
|
||||
// IP frame output
|
||||
.m_ip_hdr_valid(rx_ip_hdr_valid),
|
||||
.m_ip_hdr_ready(rx_ip_hdr_ready),
|
||||
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
|
||||
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
|
||||
.m_ip_eth_type(rx_ip_eth_type),
|
||||
.m_ip_version(rx_ip_version),
|
||||
.m_ip_ihl(rx_ip_ihl),
|
||||
.m_ip_dscp(rx_ip_dscp),
|
||||
.m_ip_ecn(rx_ip_ecn),
|
||||
.m_ip_length(rx_ip_length),
|
||||
.m_ip_identification(rx_ip_identification),
|
||||
.m_ip_flags(rx_ip_flags),
|
||||
.m_ip_fragment_offset(rx_ip_fragment_offset),
|
||||
.m_ip_ttl(rx_ip_ttl),
|
||||
.m_ip_protocol(rx_ip_protocol),
|
||||
.m_ip_header_checksum(rx_ip_header_checksum),
|
||||
.m_ip_source_ip(rx_ip_source_ip),
|
||||
.m_ip_dest_ip(rx_ip_dest_ip),
|
||||
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
|
||||
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
|
||||
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
|
||||
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
|
||||
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
|
||||
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
|
||||
// UDP frame input
|
||||
.s_udp_hdr_valid(tx_udp_hdr_valid),
|
||||
.s_udp_hdr_ready(tx_udp_hdr_ready),
|
||||
.s_udp_ip_dscp(tx_udp_ip_dscp),
|
||||
.s_udp_ip_ecn(tx_udp_ip_ecn),
|
||||
.s_udp_ip_ttl(tx_udp_ip_ttl),
|
||||
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
|
||||
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
|
||||
.s_udp_source_port(tx_udp_source_port),
|
||||
.s_udp_dest_port(tx_udp_dest_port),
|
||||
.s_udp_length(tx_udp_length),
|
||||
.s_udp_checksum(tx_udp_checksum),
|
||||
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
|
||||
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
|
||||
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
|
||||
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
|
||||
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
|
||||
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
|
||||
// UDP frame output
|
||||
.m_udp_hdr_valid(rx_udp_hdr_valid),
|
||||
.m_udp_hdr_ready(rx_udp_hdr_ready),
|
||||
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
|
||||
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
|
||||
.m_udp_eth_type(rx_udp_eth_type),
|
||||
.m_udp_ip_version(rx_udp_ip_version),
|
||||
.m_udp_ip_ihl(rx_udp_ip_ihl),
|
||||
.m_udp_ip_dscp(rx_udp_ip_dscp),
|
||||
.m_udp_ip_ecn(rx_udp_ip_ecn),
|
||||
.m_udp_ip_length(rx_udp_ip_length),
|
||||
.m_udp_ip_identification(rx_udp_ip_identification),
|
||||
.m_udp_ip_flags(rx_udp_ip_flags),
|
||||
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
|
||||
.m_udp_ip_ttl(rx_udp_ip_ttl),
|
||||
.m_udp_ip_protocol(rx_udp_ip_protocol),
|
||||
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
|
||||
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
|
||||
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
|
||||
.m_udp_source_port(rx_udp_source_port),
|
||||
.m_udp_dest_port(rx_udp_dest_port),
|
||||
.m_udp_length(rx_udp_length),
|
||||
.m_udp_checksum(rx_udp_checksum),
|
||||
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
|
||||
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
|
||||
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
|
||||
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
|
||||
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
|
||||
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
|
||||
// Status signals
|
||||
.ip_rx_busy(),
|
||||
.ip_tx_busy(),
|
||||
.udp_rx_busy(),
|
||||
.udp_tx_busy(),
|
||||
.ip_rx_error_header_early_termination(),
|
||||
.ip_rx_error_payload_early_termination(),
|
||||
.ip_rx_error_invalid_header(),
|
||||
.ip_rx_error_invalid_checksum(),
|
||||
.ip_tx_error_payload_early_termination(),
|
||||
.ip_tx_error_arp_failed(),
|
||||
.udp_rx_error_header_early_termination(),
|
||||
.udp_rx_error_payload_early_termination(),
|
||||
.udp_tx_error_payload_early_termination(),
|
||||
// Configuration
|
||||
.local_mac(local_mac),
|
||||
.local_ip(local_ip),
|
||||
.gateway_ip(gateway_ip),
|
||||
.subnet_mask(subnet_mask),
|
||||
.clear_arp_cache(1'b0)
|
||||
);
|
||||
|
||||
axis_fifo #(
|
||||
.ADDR_WIDTH(10),
|
||||
.DATA_WIDTH(64),
|
||||
.KEEP_ENABLE(1),
|
||||
.KEEP_WIDTH(8),
|
||||
.ID_ENABLE(0),
|
||||
.DEST_ENABLE(0),
|
||||
.USER_ENABLE(1),
|
||||
.USER_WIDTH(1),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
udp_payload_fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
|
||||
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
|
||||
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
|
||||
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
|
||||
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
|
||||
.s_axis_tid(0),
|
||||
.s_axis_tdest(0),
|
||||
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
|
||||
|
||||
// AXI output
|
||||
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
|
||||
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
|
||||
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
|
||||
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
|
||||
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
|
||||
|
||||
// Status
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
endmodule
|
||||
52
example/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
52
example/ExaNIC_X10/fpga/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||
* using a pipeline of N registers.
|
||||
*/
|
||||
module sync_reset #(
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
output wire sync_reset_out
|
||||
);
|
||||
|
||||
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||
|
||||
assign sync_reset_out = sync_reg[N-1];
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst)
|
||||
sync_reg <= {N{1'b1}};
|
||||
else
|
||||
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
example/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
58
example/ExaNIC_X10/fpga/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
example/ExaNIC_X10/fpga/tb/arp_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/arp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/arp_ep.py
|
||||
1
example/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
example/ExaNIC_X10/fpga/tb/eth_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/eth_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/eth_ep.py
|
||||
1
example/ExaNIC_X10/fpga/tb/gmii_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/gmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/gmii_ep.py
|
||||
1
example/ExaNIC_X10/fpga/tb/ip_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/ip_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/ip_ep.py
|
||||
294
example/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
294
example/ExaNIC_X10/fpga/tb/test_fpga_core.py
Executable file
@ -0,0 +1,294 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2016-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import eth_ep
|
||||
import arp_ep
|
||||
import udp_ep
|
||||
import gmii_ep
|
||||
import xgmii_ep
|
||||
|
||||
module = 'fpga_core'
|
||||
testbench = 'test_%s' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/lfsr.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_rx.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_tx.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/eth_axis_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_complete_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_checksum_gen_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_ip_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/udp_ip_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_complete_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/ip_arb_mux.v")
|
||||
srcs.append("../lib/eth/rtl/arp_64.v")
|
||||
srcs.append("../lib/eth/rtl/arp_cache.v")
|
||||
srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/eth_arb_mux.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/axis_fifo.v")
|
||||
srcs.append("../lib/eth/lib/axis/rtl/axis_async_fifo.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
sfp_1_txd = Signal(intbv(0)[64:])
|
||||
sfp_1_txc = Signal(intbv(0)[8:])
|
||||
sfp_2_txd = Signal(intbv(0)[64:])
|
||||
sfp_2_txc = Signal(intbv(0)[8:])
|
||||
|
||||
# Outputs
|
||||
sfp_1_led = Signal(intbv(0)[2:])
|
||||
sfp_2_led = Signal(intbv(0)[2:])
|
||||
sma_led = Signal(intbv(0)[2:])
|
||||
sfp_1_tx_clk = Signal(bool(0))
|
||||
sfp_1_tx_rst = Signal(bool(0))
|
||||
sfp_1_rx_clk = Signal(bool(0))
|
||||
sfp_1_rx_rst = Signal(bool(0))
|
||||
sfp_1_rxd = Signal(intbv(0)[64:])
|
||||
sfp_1_rxc = Signal(intbv(0)[8:])
|
||||
sfp_2_tx_clk = Signal(bool(0))
|
||||
sfp_2_tx_rst = Signal(bool(0))
|
||||
sfp_2_rx_clk = Signal(bool(0))
|
||||
sfp_2_rx_rst = Signal(bool(0))
|
||||
sfp_2_rxd = Signal(intbv(0)[64:])
|
||||
sfp_2_rxc = Signal(intbv(0)[8:])
|
||||
|
||||
# sources and sinks
|
||||
sfp_1_source = xgmii_ep.XGMIISource()
|
||||
sfp_1_source_logic = sfp_1_source.create_logic(sfp_1_tx_clk, sfp_1_tx_rst, txd=sfp_1_rxd, txc=sfp_1_rxc, name='sfp_1_source')
|
||||
|
||||
sfp_1_sink = xgmii_ep.XGMIISink()
|
||||
sfp_1_sink_logic = sfp_1_sink.create_logic(sfp_1_rx_clk, sfp_1_rx_rst, rxd=sfp_1_txd, rxc=sfp_1_txc, name='sfp_1_sink')
|
||||
|
||||
sfp_2_source = xgmii_ep.XGMIISource()
|
||||
sfp_2_source_logic = sfp_2_source.create_logic(sfp_2_tx_clk, sfp_2_tx_rst, txd=sfp_2_rxd, txc=sfp_2_rxc, name='sfp_2_source')
|
||||
|
||||
sfp_2_sink = xgmii_ep.XGMIISink()
|
||||
sfp_2_sink_logic = sfp_2_sink.create_logic(sfp_2_rx_clk, sfp_2_rx_rst, rxd=sfp_2_txd, rxc=sfp_2_txc, name='sfp_2_sink')
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
sfp_1_led=sfp_1_led,
|
||||
sfp_2_led=sfp_2_led,
|
||||
sma_led=sma_led,
|
||||
|
||||
sfp_1_tx_clk=sfp_1_tx_clk,
|
||||
sfp_1_tx_rst=sfp_1_tx_rst,
|
||||
sfp_1_txd=sfp_1_txd,
|
||||
sfp_1_txc=sfp_1_txc,
|
||||
sfp_1_rx_clk=sfp_1_rx_clk,
|
||||
sfp_1_rx_rst=sfp_1_rx_rst,
|
||||
sfp_1_rxd=sfp_1_rxd,
|
||||
sfp_1_rxc=sfp_1_rxc,
|
||||
sfp_2_tx_clk=sfp_2_tx_clk,
|
||||
sfp_2_tx_rst=sfp_2_tx_rst,
|
||||
sfp_2_txd=sfp_2_txd,
|
||||
sfp_2_txc=sfp_2_txc,
|
||||
sfp_2_rx_clk=sfp_2_rx_clk,
|
||||
sfp_2_rx_rst=sfp_2_rx_rst,
|
||||
sfp_2_rxd=sfp_2_rxd,
|
||||
sfp_2_rxc=sfp_2_rxc
|
||||
)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@always_comb
|
||||
def clk_logic():
|
||||
sfp_1_tx_clk.next = clk
|
||||
sfp_1_tx_rst.next = rst
|
||||
sfp_1_rx_clk.next = clk
|
||||
sfp_1_rx_rst.next = rst
|
||||
sfp_2_tx_clk.next = clk
|
||||
sfp_2_tx_rst.next = rst
|
||||
sfp_2_rx_clk.next = clk
|
||||
sfp_2_rx_rst.next = rst
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: test UDP RX packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = udp_ep.UDPFrame()
|
||||
test_frame.eth_dest_mac = 0x020000000000
|
||||
test_frame.eth_src_mac = 0xDAD1D2D3D4D5
|
||||
test_frame.eth_type = 0x0800
|
||||
test_frame.ip_version = 4
|
||||
test_frame.ip_ihl = 5
|
||||
test_frame.ip_dscp = 0
|
||||
test_frame.ip_ecn = 0
|
||||
test_frame.ip_length = None
|
||||
test_frame.ip_identification = 0
|
||||
test_frame.ip_flags = 2
|
||||
test_frame.ip_fragment_offset = 0
|
||||
test_frame.ip_ttl = 64
|
||||
test_frame.ip_protocol = 0x11
|
||||
test_frame.ip_header_checksum = None
|
||||
test_frame.ip_source_ip = 0xc0a80181
|
||||
test_frame.ip_dest_ip = 0xc0a80180
|
||||
test_frame.udp_source_port = 5678
|
||||
test_frame.udp_dest_port = 1234
|
||||
test_frame.payload = bytearray(range(32))
|
||||
test_frame.build()
|
||||
|
||||
sfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+test_frame.build_eth().build_axis_fcs().data)
|
||||
|
||||
# wait for ARP request packet
|
||||
while sfp_1_sink.empty():
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = sfp_1_sink.recv()
|
||||
check_eth_frame = eth_ep.EthFrame()
|
||||
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
|
||||
check_frame = arp_ep.ARPFrame()
|
||||
check_frame.parse_eth(check_eth_frame)
|
||||
|
||||
print(check_frame)
|
||||
|
||||
assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF
|
||||
assert check_frame.eth_src_mac == 0x020000000000
|
||||
assert check_frame.eth_type == 0x0806
|
||||
assert check_frame.arp_htype == 0x0001
|
||||
assert check_frame.arp_ptype == 0x0800
|
||||
assert check_frame.arp_hlen == 6
|
||||
assert check_frame.arp_plen == 4
|
||||
assert check_frame.arp_oper == 1
|
||||
assert check_frame.arp_sha == 0x020000000000
|
||||
assert check_frame.arp_spa == 0xc0a80180
|
||||
assert check_frame.arp_tha == 0x000000000000
|
||||
assert check_frame.arp_tpa == 0xc0a80181
|
||||
|
||||
# generate response
|
||||
arp_frame = arp_ep.ARPFrame()
|
||||
arp_frame.eth_dest_mac = 0x020000000000
|
||||
arp_frame.eth_src_mac = 0xDAD1D2D3D4D5
|
||||
arp_frame.eth_type = 0x0806
|
||||
arp_frame.arp_htype = 0x0001
|
||||
arp_frame.arp_ptype = 0x0800
|
||||
arp_frame.arp_hlen = 6
|
||||
arp_frame.arp_plen = 4
|
||||
arp_frame.arp_oper = 2
|
||||
arp_frame.arp_sha = 0xDAD1D2D3D4D5
|
||||
arp_frame.arp_spa = 0xc0a80181
|
||||
arp_frame.arp_tha = 0x020000000000
|
||||
arp_frame.arp_tpa = 0xc0a80180
|
||||
|
||||
sfp_1_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5'+arp_frame.build_eth().build_axis_fcs().data)
|
||||
|
||||
while sfp_1_sink.empty():
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = sfp_1_sink.recv()
|
||||
check_eth_frame = eth_ep.EthFrame()
|
||||
check_eth_frame.parse_axis_fcs(rx_frame.data[8:])
|
||||
check_frame = udp_ep.UDPFrame()
|
||||
check_frame.parse_eth(check_eth_frame)
|
||||
|
||||
print(check_frame)
|
||||
|
||||
assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5
|
||||
assert check_frame.eth_src_mac == 0x020000000000
|
||||
assert check_frame.eth_type == 0x0800
|
||||
assert check_frame.ip_version == 4
|
||||
assert check_frame.ip_ihl == 5
|
||||
assert check_frame.ip_dscp == 0
|
||||
assert check_frame.ip_ecn == 0
|
||||
assert check_frame.ip_identification == 0
|
||||
assert check_frame.ip_flags == 2
|
||||
assert check_frame.ip_fragment_offset == 0
|
||||
assert check_frame.ip_ttl == 64
|
||||
assert check_frame.ip_protocol == 0x11
|
||||
assert check_frame.ip_source_ip == 0xc0a80180
|
||||
assert check_frame.ip_dest_ip == 0xc0a80181
|
||||
assert check_frame.udp_source_port == 1234
|
||||
assert check_frame.udp_dest_port == 5678
|
||||
assert check_frame.payload.data == bytearray(range(32))
|
||||
|
||||
assert sfp_1_source.empty()
|
||||
assert sfp_1_sink.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
122
example/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
122
example/ExaNIC_X10/fpga/tb/test_fpga_core.v
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2016-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg sfp_1_tx_clk = 0;
|
||||
reg sfp_1_tx_rst = 0;
|
||||
reg sfp_1_rx_clk = 0;
|
||||
reg sfp_1_rx_rst = 0;
|
||||
reg [63:0] sfp_1_rxd = 0;
|
||||
reg [7:0] sfp_1_rxc = 0;
|
||||
reg sfp_2_tx_clk = 0;
|
||||
reg sfp_2_tx_rst = 0;
|
||||
reg sfp_2_rx_clk = 0;
|
||||
reg sfp_2_rx_rst = 0;
|
||||
reg [63:0] sfp_2_rxd = 0;
|
||||
reg [7:0] sfp_2_rxc = 0;
|
||||
|
||||
// Outputs
|
||||
wire [1:0] sfp_1_led;
|
||||
wire [1:0] sfp_2_led;
|
||||
wire [1:0] sma_led;
|
||||
wire [63:0] sfp_1_txd;
|
||||
wire [7:0] sfp_1_txc;
|
||||
wire [63:0] sfp_2_txd;
|
||||
wire [7:0] sfp_2_txc;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk,
|
||||
rst,
|
||||
current_test,
|
||||
sfp_1_tx_clk,
|
||||
sfp_1_tx_rst,
|
||||
sfp_1_rx_clk,
|
||||
sfp_1_rx_rst,
|
||||
sfp_1_rxd,
|
||||
sfp_1_rxc,
|
||||
sfp_2_tx_clk,
|
||||
sfp_2_tx_rst,
|
||||
sfp_2_rx_clk,
|
||||
sfp_2_rx_rst,
|
||||
sfp_2_rxd,
|
||||
sfp_2_rxc
|
||||
);
|
||||
$to_myhdl(
|
||||
sfp_1_led,
|
||||
sfp_2_led,
|
||||
sma_led,
|
||||
sfp_1_txd,
|
||||
sfp_1_txc,
|
||||
sfp_2_txd,
|
||||
sfp_2_txc
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.sfp_1_led(sfp_1_led),
|
||||
.sfp_2_led(sfp_2_led),
|
||||
.sma_led(sma_led),
|
||||
.sfp_1_tx_clk(sfp_1_tx_clk),
|
||||
.sfp_1_tx_rst(sfp_1_tx_rst),
|
||||
.sfp_1_txd(sfp_1_txd),
|
||||
.sfp_1_txc(sfp_1_txc),
|
||||
.sfp_1_rx_clk(sfp_1_rx_clk),
|
||||
.sfp_1_rx_rst(sfp_1_rx_rst),
|
||||
.sfp_1_rxd(sfp_1_rxd),
|
||||
.sfp_1_rxc(sfp_1_rxc),
|
||||
.sfp_2_tx_clk(sfp_2_tx_clk),
|
||||
.sfp_2_tx_rst(sfp_2_tx_rst),
|
||||
.sfp_2_txd(sfp_2_txd),
|
||||
.sfp_2_txc(sfp_2_txc),
|
||||
.sfp_2_rx_clk(sfp_2_rx_clk),
|
||||
.sfp_2_rx_rst(sfp_2_rx_rst),
|
||||
.sfp_2_rxd(sfp_2_rxd),
|
||||
.sfp_2_rxc(sfp_2_rxc)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
example/ExaNIC_X10/fpga/tb/udp_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/udp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/udp_ep.py
|
||||
1
example/ExaNIC_X10/fpga/tb/xgmii_ep.py
Symbolic link
1
example/ExaNIC_X10/fpga/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
Loading…
x
Reference in New Issue
Block a user