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Update PTP subsystem to use separate clock for improved stability

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-05-06 17:46:16 -07:00
parent 6656a14528
commit 835f0d38f0
216 changed files with 2554 additions and 937 deletions
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12
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
View File

@ -50,12 +50,9 @@ module mqnic_app_block #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -295,10 +292,15 @@ module mqnic_app_block #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
input wire ptp_sync_ts_step,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,

11
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -137,8 +137,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -248,7 +251,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -341,7 +347,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -323,7 +323,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -338,6 +340,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -345,6 +349,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(1)
mac.tx.reset.setimmediatevalue(1)
self.dut.ptp_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst)
await Timer(100, 'ns')
@ -355,6 +361,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
async def _run_loopback(self):
@ -916,8 +924,11 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

12
fpga/app/template/rtl/mqnic_app_block.v
View File

@ -50,12 +50,9 @@ module mqnic_app_block #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -295,10 +292,15 @@ module mqnic_app_block #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
input wire ptp_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
input wire ptp_sync_pps,
input wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
input wire ptp_sync_ts_step,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,

11
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -136,8 +136,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -248,7 +251,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -342,7 +348,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -323,7 +323,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -338,6 +340,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -345,6 +349,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(1)
mac.tx.reset.setimmediatevalue(1)
self.dut.ptp_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst)
await Timer(100, 'ns')
@ -355,6 +361,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
async def _run_loopback(self):
@ -756,8 +764,11 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

56
fpga/common/rtl/mqnic_core.v
View File

@ -60,13 +60,11 @@ module mqnic_core #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -329,10 +327,15 @@ module mqnic_core #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -628,12 +631,11 @@ always @(posedge clk) begin
end
mqnic_ptp #(
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
.REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
@ -664,9 +666,15 @@ mqnic_ptp_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse)
@ -2638,8 +2646,8 @@ generate
/*
* PTP clock
*/
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step),
/*
* MSI interrupts
@ -2681,14 +2689,14 @@ generate
// PTP CDC logic
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.NS_WIDTH(6),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE)
)
tx_ptp_cdc_inst (
.input_clk(clk),
.input_rst(rst),
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(port_tx_clk),
.output_rst(port_tx_rst),
.sample_clk(ptp_sample_clk),
@ -2702,14 +2710,14 @@ generate
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.NS_WIDTH(6),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PIPELINE_OUTPUT(PTP_PORT_CDC_PIPELINE)
)
rx_ptp_cdc_inst (
.input_clk(clk),
.input_rst(rst),
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_clk : port_rx_clk),
.output_rst(PTP_SEPARATE_RX_CLOCK ? port_rx_ptp_rst : port_rx_rst),
.sample_clk(ptp_sample_clk),
@ -2756,12 +2764,9 @@ if (APP_ENABLE) begin : app
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -2999,10 +3004,15 @@ if (APP_ENABLE) begin : app
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

26
fpga/common/rtl/mqnic_core_axi.v
View File

@ -60,13 +60,11 @@ module mqnic_core_axi #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -319,10 +317,15 @@ module mqnic_core_axi #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -793,13 +796,11 @@ mqnic_core #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1060,10 +1061,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

26
fpga/common/rtl/mqnic_core_pcie.v
View File

@ -60,13 +60,11 @@ module mqnic_core_pcie #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -330,10 +328,15 @@ module mqnic_core_pcie #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -1344,13 +1347,11 @@ mqnic_core #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1611,10 +1612,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

26
fpga/common/rtl/mqnic_core_pcie_s10.v
View File

@ -60,13 +60,11 @@ module mqnic_core_pcie_s10 #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -287,10 +285,15 @@ module mqnic_core_pcie_s10 #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -608,13 +611,11 @@ mqnic_core_pcie #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -876,10 +877,15 @@ core_pcie_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

26
fpga/common/rtl/mqnic_core_pcie_us.v
View File

@ -60,13 +60,11 @@ module mqnic_core_pcie_us #
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -338,10 +336,15 @@ module mqnic_core_pcie_us #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
@ -698,13 +701,11 @@ mqnic_core_pcie #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -966,10 +967,15 @@ core_pcie_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

36
fpga/common/rtl/mqnic_ptp.v
View File

@ -42,12 +42,11 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_ptp #
(
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
parameter REG_ADDR_WIDTH = 7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0),
@ -78,9 +77,15 @@ module mqnic_ptp #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [95:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse
@ -149,12 +154,11 @@ always @* begin
end
mqnic_ptp_clock #(
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
@ -185,9 +189,15 @@ ptp_clock_inst (
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step)
);
generate
@ -227,8 +237,8 @@ if (PTP_PEROUT_ENABLE) begin
/*
* PTP clock
*/
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked[n]),
.ptp_perout_error(ptp_perout_error[n]),
.ptp_perout_pulse(ptp_perout_pulse[n])

136
fpga/common/rtl/mqnic_ptp_clock.v
View File

@ -42,12 +42,11 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_ptp_clock #
(
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
parameter REG_ADDR_WIDTH = 7,
@ -78,11 +77,27 @@ module mqnic_ptp_clock #
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [95:0] ptp_ts_96,
output wire ptp_ts_step
output wire ptp_ts_step,
output wire ptp_sync_pps,
output wire [95:0] ptp_sync_ts_96,
output wire ptp_sync_ts_step
);
parameter PTP_FNS_WIDTH = 32;
parameter PTP_CLK_PERIOD_NS = PTP_CLK_PERIOD_NS_NUM / PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_CLK_PERIOD_NS_REM = PTP_CLK_PERIOD_NS_NUM - PTP_CLK_PERIOD_NS*PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_CLK_PERIOD_FNS = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) / PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_CLK_PERIOD_FNS_REM = (PTP_CLK_PERIOD_NS_REM * {32'd1, {PTP_FNS_WIDTH{1'b0}}}) - PTP_CLK_PERIOD_FNS*PTP_CLK_PERIOD_NS_DENOM;
parameter PTP_PERIOD_NS_WIDTH = $clog2(PTP_CLK_PERIOD_NS+1) + 2;
parameter PTP_OFFSET_NS_WIDTH = 32;
localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
// check configuration
@ -116,8 +131,8 @@ reg reg_rd_ack_reg = 1'b0;
reg [95:0] get_ptp_ts_96_reg = 0;
reg [95:0] set_ptp_ts_96_reg = 0;
reg set_ptp_ts_96_valid_reg = 0;
reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = 0;
reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = 0;
reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = PTP_CLK_PERIOD_NS;
reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = PTP_CLK_PERIOD_FNS;
reg set_ptp_period_valid_reg = 0;
reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0;
reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0;
@ -136,10 +151,6 @@ always @(posedge clk) begin
reg_rd_data_reg <= 0;
reg_rd_ack_reg <= 1'b0;
set_ptp_ts_96_valid_reg <= 1'b0;
set_ptp_period_valid_reg <= 1'b0;
set_ptp_offset_valid_reg <= 1'b0;
if (reg_wr_en && !reg_wr_ack_reg) begin
// write operation
reg_wr_ack_reg <= 1'b1;
@ -151,20 +162,20 @@ always @(posedge clk) begin
RBB+7'h3C: begin
// PTP set sec h
set_ptp_ts_96_reg[95:80] <= reg_wr_data;
set_ptp_ts_96_valid_reg <= 1'b1;
set_ptp_ts_96_valid_reg <= !set_ptp_ts_96_valid_reg;
end
RBB+7'h40: set_ptp_period_fns_reg <= reg_wr_data; // PTP period fns
RBB+7'h44: begin
// PTP period ns
set_ptp_period_ns_reg <= reg_wr_data;
set_ptp_period_valid_reg <= 1'b1;
set_ptp_period_valid_reg <= !set_ptp_period_valid_reg;
end
RBB+7'h50: set_ptp_offset_fns_reg <= reg_wr_data; // PTP offset fns
RBB+7'h54: set_ptp_offset_ns_reg <= reg_wr_data; // PTP offset ns
RBB+7'h58: begin
// PTP offset count
set_ptp_offset_count_reg <= reg_wr_data;
set_ptp_offset_valid_reg <= 1'b1;
set_ptp_offset_valid_reg <= !set_ptp_offset_valid_reg;
end
default: reg_wr_ack_reg <= 1'b0;
endcase
@ -185,14 +196,14 @@ always @(posedge clk) begin
reg_rd_data_reg[23:16] <= 0;
reg_rd_data_reg[31:24] <= 0;
end
RBB+7'h10: reg_rd_data_reg <= ptp_ts_96[15:0]; // PTP cur fns
RBB+7'h14: reg_rd_data_reg <= ptp_ts_96[45:16]; // PTP cur ns
RBB+7'h18: reg_rd_data_reg <= ptp_ts_96[79:48]; // PTP cur sec l
RBB+7'h1C: reg_rd_data_reg <= ptp_ts_96[95:80]; // PTP cur sec h
RBB+7'h10: reg_rd_data_reg <= ptp_sync_ts_96[15:0]; // PTP cur fns
RBB+7'h14: reg_rd_data_reg <= ptp_sync_ts_96[45:16]; // PTP cur ns
RBB+7'h18: reg_rd_data_reg <= ptp_sync_ts_96[79:48]; // PTP cur sec l
RBB+7'h1C: reg_rd_data_reg <= ptp_sync_ts_96[95:80]; // PTP cur sec h
RBB+7'h20: begin
// PTP get fns
get_ptp_ts_96_reg <= ptp_ts_96;
reg_rd_data_reg <= ptp_ts_96[15:0];
get_ptp_ts_96_reg <= ptp_sync_ts_96;
reg_rd_data_reg <= ptp_sync_ts_96[15:0];
end
RBB+7'h24: reg_rd_data_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns
RBB+7'h28: reg_rd_data_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l
@ -203,8 +214,8 @@ always @(posedge clk) begin
RBB+7'h3C: reg_rd_data_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h
RBB+7'h40: reg_rd_data_reg <= set_ptp_period_fns_reg; // PTP period fns
RBB+7'h44: reg_rd_data_reg <= set_ptp_period_ns_reg; // PTP period ns
RBB+7'h48: reg_rd_data_reg <= PTP_PERIOD_FNS; // PTP nom period fns
RBB+7'h4C: reg_rd_data_reg <= PTP_PERIOD_NS; // PTP nom period ns
RBB+7'h48: reg_rd_data_reg <= PTP_CLK_PERIOD_FNS; // PTP nom period fns
RBB+7'h4C: reg_rd_data_reg <= PTP_CLK_PERIOD_NS; // PTP nom period ns
RBB+7'h50: reg_rd_data_reg <= set_ptp_offset_fns_reg; // PTP offset fns
RBB+7'h54: reg_rd_data_reg <= set_ptp_offset_ns_reg; // PTP offset ns
RBB+7'h58: reg_rd_data_reg <= set_ptp_offset_count_reg; // PTP offset count
@ -216,28 +227,69 @@ always @(posedge clk) begin
if (rst) begin
reg_wr_ack_reg <= 1'b0;
reg_rd_ack_reg <= 1'b0;
set_ptp_period_ns_reg <= PTP_CLK_PERIOD_NS;
set_ptp_period_fns_reg <= PTP_CLK_PERIOD_FNS;
end
end
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_ts_96_valid_sync_3_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_period_valid_sync_3_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_1_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_2_reg = 1'b0;
(* shreg_extract = "no" *)
reg set_ptp_offset_valid_sync_3_reg = 1'b0;
always @(posedge ptp_clk) begin
set_ptp_ts_96_valid_sync_1_reg <= set_ptp_ts_96_valid_reg;
set_ptp_ts_96_valid_sync_2_reg <= set_ptp_ts_96_valid_sync_1_reg;
set_ptp_ts_96_valid_sync_3_reg <= set_ptp_ts_96_valid_sync_2_reg;
set_ptp_period_valid_sync_1_reg <= set_ptp_period_valid_reg;
set_ptp_period_valid_sync_2_reg <= set_ptp_period_valid_sync_1_reg;
set_ptp_period_valid_sync_3_reg <= set_ptp_period_valid_sync_2_reg;
set_ptp_offset_valid_sync_1_reg <= set_ptp_offset_valid_reg;
set_ptp_offset_valid_sync_2_reg <= set_ptp_offset_valid_sync_1_reg;
set_ptp_offset_valid_sync_3_reg <= set_ptp_offset_valid_sync_2_reg;
end
// PTP clock
ptp_clock #(
.PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.FNS_WIDTH(PTP_FNS_WIDTH),
.PERIOD_NS(PTP_PERIOD_NS),
.PERIOD_FNS(PTP_PERIOD_FNS),
.PERIOD_NS(PTP_CLK_PERIOD_NS),
.PERIOD_FNS(PTP_CLK_PERIOD_FNS),
.DRIFT_ENABLE(0),
.DRIFT_NS(0),
.DRIFT_FNS(PTP_CLK_PERIOD_FNS_REM),
.DRIFT_RATE(PTP_CLK_PERIOD_NS_DENOM),
.PIPELINE_OUTPUT(PTP_CLOCK_PIPELINE)
)
ptp_clock_inst (
.clk(clk),
.rst(rst),
.clk(ptp_clk),
.rst(ptp_rst),
/*
* Timestamp inputs for synchronization
*/
.input_ts_96(set_ptp_ts_96_reg),
.input_ts_96_valid(set_ptp_ts_96_valid_reg),
.input_ts_96_valid(set_ptp_ts_96_valid_sync_2_reg ^ set_ptp_ts_96_valid_sync_3_reg),
.input_ts_64(0),
.input_ts_64_valid(1'b0),
@ -246,7 +298,7 @@ ptp_clock_inst (
*/
.input_period_ns(set_ptp_period_ns_reg),
.input_period_fns(set_ptp_period_fns_reg),
.input_period_valid(set_ptp_period_valid_reg),
.input_period_valid(set_ptp_period_valid_sync_2_reg ^ set_ptp_period_valid_sync_3_reg),
/*
* Offset adjustment
@ -254,8 +306,8 @@ ptp_clock_inst (
.input_adj_ns(set_ptp_offset_ns_reg),
.input_adj_fns(set_ptp_offset_fns_reg),
.input_adj_count(set_ptp_offset_count_reg),
.input_adj_valid(set_ptp_offset_valid_reg),
.input_adj_active(set_ptp_offset_active),
.input_adj_valid(set_ptp_offset_valid_sync_2_reg ^ set_ptp_offset_valid_sync_3_reg),
// .input_adj_active(set_ptp_offset_active),
/*
* Drift adjustment
@ -278,6 +330,28 @@ ptp_clock_inst (
.output_pps(ptp_pps)
);
// sync to core clock domain
ptp_clock_cdc #(
.TS_WIDTH(96),
.NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PIPELINE_OUTPUT(PTP_CLOCK_CDC_PIPELINE)
)
ptp_cdc_inst (
.input_clk(ptp_clk),
.input_rst(ptp_rst),
.output_clk(clk),
.output_rst(rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(ptp_sync_ts_96),
.output_ts_step(ptp_sync_ts_step),
.output_pps(ptp_sync_pps),
.locked()
);
endmodule
`resetall

60
fpga/common/syn/vivado/mqnic_ptp_clock.tcl Normal file
View File

@ -0,0 +1,60 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
# PTP clock timing constraints
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_ptp_clock || REF_NAME == mqnic_ptp_clock)}] {
puts "Inserting timing constraints for mqnic_ptp_clock instance $inst"
set src_clk [get_clocks -of_objects [get_pins "$inst/set_ptp_ts_96_valid_reg_reg/C"]]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_ts_96_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_inc_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_inc_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_ovf_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_ovf_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_s_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/ts_96_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_ts_96_valid_reg_reg"] -to [get_cells "$inst/set_ptp_ts_96_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_period_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_period_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_period_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/period_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_period_valid_reg_reg"] -to [get_cells "$inst/set_ptp_period_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/set_ptp_offset_valid_sync_\[123\]_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/set_ptp_offset_ns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_ns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_offset_fns_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_fns_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_offset_count_reg_reg[*]"] -to [get_cells "$inst/ptp_clock_inst/adj_count_reg_reg[*]"] -datapath_only [get_property -min PERIOD $src_clk]
set_max_delay -from [get_cells "$inst/set_ptp_offset_valid_reg_reg"] -to [get_cells "$inst/set_ptp_offset_valid_sync_1_reg_reg"] -datapath_only [get_property -min PERIOD $src_clk]
}

11
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -122,8 +122,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -234,7 +237,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -326,7 +332,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -139,7 +139,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -155,6 +157,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -163,6 +167,8 @@ class TB(object):
mac.rx.reset.value = 1
mac.tx.reset.value = 1
self.dut.ptp_rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -171,6 +177,8 @@ class TB(object):
mac.rx.reset.value = 0
mac.tx.reset.value = 0
self.dut.ptp_rst.value = 0
async def _run_loopback(self):
while True:
await RisingEdge(self.dut.clk)
@ -547,8 +555,11 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

11
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -132,8 +132,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -249,7 +252,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -348,7 +354,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -248,7 +248,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -263,6 +265,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -270,6 +274,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(1)
mac.tx.reset.setimmediatevalue(1)
self.dut.ptp_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst)
await Timer(100, 'ns')
@ -280,6 +286,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
async def _run_loopback(self):
@ -671,8 +679,11 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

11
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -134,8 +134,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -246,7 +249,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -340,7 +346,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -323,7 +323,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -338,6 +340,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -345,6 +349,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(1)
mac.tx.reset.setimmediatevalue(1)
self.dut.ptp_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst)
await Timer(100, 'ns')
@ -355,6 +361,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
async def _run_loopback(self):
@ -748,8 +756,11 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

11
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -136,8 +136,11 @@ export PARAM_PORTS_PER_IF ?= 1
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -248,7 +251,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -342,7 +348,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

15
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -323,7 +323,9 @@ class TB(object):
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
@ -338,6 +340,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@ -345,6 +349,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(1)
mac.tx.reset.setimmediatevalue(1)
self.dut.ptp_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst)
await Timer(100, 'ns')
@ -355,6 +361,8 @@ class TB(object):
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
self.dut.ptp_rst.setimmediatevalue(0)
await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
async def _run_loopback(self):
@ -803,8 +811,11 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['SCHED_PER_IF'] = ports_per_if
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -110,6 +110,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -112,6 +112,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

50
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -248,14 +249,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -964,6 +961,8 @@ wire qsfp_0_rx_ptp_rst_int;
wire [79:0] qsfp_0_rx_ptp_time_int;
wire qsfp_0_rx_status;
wire qsfp_0_ref_clk;
wire qsfp_0_txuserclk2;
wire qsfp_0_rxuserclk2;
@ -1042,7 +1041,7 @@ qsfp_0_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(), // output
.gt_ref_clk_out(qsfp_0_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1371,6 +1370,8 @@ wire qsfp_1_rx_ptp_rst_int;
wire [79:0] qsfp_1_rx_ptp_time_int;
wire qsfp_1_rx_status;
wire qsfp_1_ref_clk;
wire qsfp_1_txuserclk2;
wire qsfp_1_rxuserclk2;
@ -1449,7 +1450,7 @@ qsfp_1_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(), // output
.gt_ref_clk_out(qsfp_1_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1735,6 +1736,22 @@ qsfp_1_cmac_inst (
.drp_we(1'b0) // input
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp_0_ref_clk;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
assign front_led[0] = qsfp_0_rx_status;
assign front_led[1] = qsfp_1_rx_status;
@ -1756,13 +1773,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1882,6 +1897,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

39
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -185,6 +183,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -396,6 +401,9 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -654,9 +662,9 @@ end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -831,13 +839,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1108,10 +1114,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -138,8 +138,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -244,7 +247,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -332,7 +338,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

12
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp_0_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp_0_tx_clk, 3.102, units="ns").start())
@ -328,6 +332,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst.setimmediatevalue(0)
self.dut.qsfp_0_tx_rst.setimmediatevalue(0)
self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
@ -336,6 +341,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp_0_rx_rst.setimmediatevalue(1)
self.dut.qsfp_0_tx_rst.setimmediatevalue(1)
self.dut.qsfp_1_rx_rst.setimmediatevalue(1)
@ -347,6 +353,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst.setimmediatevalue(0)
self.dut.qsfp_0_tx_rst.setimmediatevalue(0)
self.dut.qsfp_1_rx_rst.setimmediatevalue(0)
@ -677,8 +684,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -128,6 +128,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -128,6 +128,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -129,6 +129,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

34
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -249,14 +250,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h2;
parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
@ -1332,6 +1329,14 @@ qsfp_1_phy_quad_inst (
.phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp_0_mgt_refclk_bufg;
assign ptp_rst = qsfp_0_rst;
assign ptp_sample_clk = clk_125mhz_int;
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1350,13 +1355,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -1475,6 +1478,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

43
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -191,6 +189,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -482,6 +487,9 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -836,9 +844,9 @@ qsfp_1_rb_drp_inst (
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -890,8 +898,8 @@ tdma_ber_inst (
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
);
assign user_led_g[0] = 1'b1;
@ -1073,13 +1081,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1350,10 +1356,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -146,8 +146,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
@ -251,7 +254,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@ -338,7 +344,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)

12
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start())
self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0)
@ -359,6 +363,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0)
self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0)
@ -379,6 +384,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp_0_rx_rst_0.setimmediatevalue(1)
self.dut.qsfp_0_tx_rst_0.setimmediatevalue(1)
self.dut.qsfp_0_rx_rst_1.setimmediatevalue(1)
@ -402,6 +408,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0)
self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0)
self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0)
@ -744,8 +751,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

1
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -115,6 +115,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/AU200/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

51
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -250,14 +251,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -1092,6 +1089,8 @@ wire qsfp0_rx_ptp_rst_int;
wire [79:0] qsfp0_rx_ptp_time_int;
wire qsfp0_rx_status;
wire qsfp0_ref_clk;
wire qsfp0_txuserclk2;
wire qsfp0_rxuserclk2;
@ -1099,6 +1098,8 @@ assign qsfp0_tx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_ptp_clk_int = qsfp0_rxuserclk2;
assign clk_161mhz_ref_int = qsfp0_ref_clk;
sync_reset #(
.N(4)
)
@ -1170,7 +1171,7 @@ qsfp0_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(clk_161mhz_ref_int), // output
.gt_ref_clk_out(qsfp0_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1503,6 +1504,7 @@ wire [79:0] qsfp1_rx_ptp_time_int;
wire qsfp1_rx_status;
wire qsfp1_ref_clk;
wire qsfp1_txuserclk2;
wire qsfp1_rxuserclk2;
@ -1581,7 +1583,7 @@ qsfp1_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(), // output
.gt_ref_clk_out(qsfp1_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1867,6 +1869,22 @@ qsfp1_cmac_inst (
.drp_we(1'b0) // input
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_ref_clk;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
wire [2:0] led_int;
assign led[0] = led_int[0]; // red
@ -1891,13 +1909,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -2017,6 +2033,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

39
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -185,6 +183,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -413,6 +418,9 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -665,9 +673,9 @@ end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -839,13 +847,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1116,10 +1122,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -138,8 +138,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -244,7 +247,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -332,7 +338,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

12
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp0_tx_clk, 3.102, units="ns").start())
@ -328,6 +332,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -336,6 +341,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst.setimmediatevalue(1)
self.dut.qsfp0_tx_rst.setimmediatevalue(1)
self.dut.qsfp1_rx_rst.setimmediatevalue(1)
@ -347,6 +353,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -677,8 +684,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -133,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU200/fpga_25g/fpga/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -133,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

34
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -251,14 +252,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1465,6 +1462,14 @@ qsfp1_phy_quad_inst (
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_mgt_refclk_1_bufg;
assign ptp_rst = qsfp0_rst;
assign ptp_sample_clk = clk_125mhz_int;
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1483,13 +1488,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -1608,6 +1611,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

43
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -191,6 +189,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -499,6 +504,9 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -847,9 +855,9 @@ qsfp1_rb_drp_inst (
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -902,8 +910,8 @@ tdma_ber_inst (
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
);
assign led[0] = pps_led_reg;
@ -1082,13 +1090,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1359,10 +1365,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -146,8 +146,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
@ -251,7 +254,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@ -338,7 +344,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)

12
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
@ -359,6 +363,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -379,6 +384,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
@ -402,6 +408,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -744,8 +751,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

1
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -115,6 +115,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

1
fpga/mqnic/AU250/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

51
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -250,14 +251,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -1092,6 +1089,8 @@ wire qsfp0_rx_ptp_rst_int;
wire [79:0] qsfp0_rx_ptp_time_int;
wire qsfp0_rx_status;
wire qsfp0_ref_clk;
wire qsfp0_txuserclk2;
wire qsfp0_rxuserclk2;
@ -1099,6 +1098,8 @@ assign qsfp0_tx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_ptp_clk_int = qsfp0_rxuserclk2;
assign clk_161mhz_ref_int = qsfp0_ref_clk;
sync_reset #(
.N(4)
)
@ -1170,7 +1171,7 @@ qsfp0_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(clk_161mhz_ref_int), // output
.gt_ref_clk_out(qsfp0_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1503,6 +1504,7 @@ wire [79:0] qsfp1_rx_ptp_time_int;
wire qsfp1_rx_status;
wire qsfp1_ref_clk;
wire qsfp1_txuserclk2;
wire qsfp1_rxuserclk2;
@ -1581,7 +1583,7 @@ qsfp1_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(), // output
.gt_ref_clk_out(qsfp1_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1867,6 +1869,22 @@ qsfp1_cmac_inst (
.drp_we(1'b0) // input
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_ref_clk;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
wire [2:0] led_int;
assign led[0] = led_int[0]; // red
@ -1891,13 +1909,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -2017,6 +2033,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

39
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
@ -185,6 +183,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -413,6 +418,9 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -665,9 +673,9 @@ end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -839,13 +847,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1116,10 +1122,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -138,8 +138,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -244,7 +247,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -332,7 +338,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

12
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp0_tx_clk, 3.102, units="ns").start())
@ -328,6 +332,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -336,6 +341,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst.setimmediatevalue(1)
self.dut.qsfp0_tx_rst.setimmediatevalue(1)
self.dut.qsfp1_rx_rst.setimmediatevalue(1)
@ -347,6 +353,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -677,8 +684,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -133,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU250/fpga_25g/fpga/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -133,6 +133,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

34
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -251,14 +252,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1465,6 +1462,14 @@ qsfp1_phy_quad_inst (
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_mgt_refclk_1_bufg;
assign ptp_rst = qsfp0_rst;
assign ptp_sample_clk = clk_125mhz_int;
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1483,13 +1488,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -1608,6 +1611,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

43
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -191,6 +189,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -499,6 +504,9 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -847,9 +855,9 @@ qsfp1_rb_drp_inst (
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -902,8 +910,8 @@ tdma_ber_inst (
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
);
assign led[0] = pps_led_reg;
@ -1082,13 +1090,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1359,10 +1365,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -146,8 +146,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
@ -251,7 +254,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@ -338,7 +344,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)

12
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
@ -359,6 +363,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -379,6 +384,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
@ -402,6 +408,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -744,8 +751,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

1
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -113,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

1
fpga/mqnic/AU280/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

51
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -233,13 +234,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -994,6 +992,8 @@ wire qsfp0_rx_ptp_rst_int;
wire [79:0] qsfp0_rx_ptp_time_int;
wire qsfp0_rx_status;
wire qsfp0_ref_clk;
wire qsfp0_txuserclk2;
wire qsfp0_rxuserclk2;
@ -1001,6 +1001,8 @@ assign qsfp0_tx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_clk_int = qsfp0_txuserclk2;
assign qsfp0_rx_ptp_clk_int = qsfp0_rxuserclk2;
assign clk_161mhz_ref_int = qsfp0_ref_clk;
sync_reset #(
.N(4)
)
@ -1072,7 +1074,7 @@ qsfp0_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(clk_161mhz_ref_int), // output
.gt_ref_clk_out(qsfp0_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1404,6 +1406,8 @@ wire qsfp1_rx_ptp_rst_int;
wire [79:0] qsfp1_rx_ptp_time_int;
wire qsfp1_rx_status;
wire qsfp1_ref_clk;
wire qsfp1_txuserclk2;
wire qsfp1_rxuserclk2;
@ -1482,7 +1486,7 @@ qsfp1_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(), // output
.gt_ref_clk_out(qsfp1_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1768,6 +1772,22 @@ qsfp1_cmac_inst (
.drp_we(1'b0) // input
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_ref_clk;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1786,13 +1806,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1912,6 +1930,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* PCIe
*/

35
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
@ -185,6 +183,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* PCIe
*/
@ -385,6 +390,9 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -715,13 +723,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -992,10 +998,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -138,8 +138,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 1
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -244,7 +247,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -332,7 +338,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

12
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp0_tx_clk, 3.102, units="ns").start())
@ -317,6 +321,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -325,6 +330,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst.setimmediatevalue(1)
self.dut.qsfp0_tx_rst.setimmediatevalue(1)
self.dut.qsfp1_rx_rst.setimmediatevalue(1)
@ -336,6 +342,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst.setimmediatevalue(0)
self.dut.qsfp0_tx_rst.setimmediatevalue(0)
self.dut.qsfp1_rx_rst.setimmediatevalue(0)
@ -666,8 +673,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -131,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU280/fpga_25g/fpga/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -131,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

34
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -234,14 +235,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1368,6 +1365,14 @@ qsfp1_phy_quad_inst (
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp0_mgt_refclk_1_bufg;
assign ptp_rst = qsfp0_rst;
assign ptp_sample_clk = clk_125mhz_int;
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1386,13 +1391,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -1515,6 +1518,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* PCIe
*/

39
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -191,6 +189,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* PCIe
*/
@ -471,6 +476,9 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -781,8 +789,8 @@ tdma_ber_inst (
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
);
wire [PORT_COUNT-1:0] eth_tx_clk;
@ -958,13 +966,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1235,10 +1241,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -146,8 +146,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 1
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
@ -251,7 +254,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@ -338,7 +344,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)

12
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
@ -348,6 +352,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -368,6 +373,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(1)
@ -391,6 +397,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp0_rx_rst_2.setimmediatevalue(0)
@ -733,8 +740,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

1
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -113,6 +113,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

1
fpga/mqnic/AU50/fpga_100g/fpga/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

47
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -211,14 +212,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter PTP_SEPARATE_RX_CLOCK = 1;
// Interface configuration
@ -971,6 +968,7 @@ wire [79:0] qsfp_rx_ptp_time_int;
wire qsfp_rx_status;
wire qsfp_ref_clk;
wire qsfp_txuserclk2;
wire qsfp_rxuserclk2;
@ -978,6 +976,8 @@ assign qsfp_tx_clk_int = qsfp_txuserclk2;
assign qsfp_rx_clk_int = qsfp_txuserclk2;
assign qsfp_rx_ptp_clk_int = qsfp_rxuserclk2;
assign clk_161mhz_ref_int = qsfp_ref_clk;
sync_reset #(
.N(4)
)
@ -1049,7 +1049,7 @@ qsfp_cmac_inst (
.gt_loopback_in(12'd0), // input [11:0]
.gt_rxrecclkout(), // output [3:0]
.gt_powergoodout(), // output [3:0]
.gt_ref_clk_out(clk_161mhz_ref_int), // output
.gt_ref_clk_out(qsfp_ref_clk), // output
.gtwiz_reset_tx_datapath(1'b0), // input
.gtwiz_reset_rx_datapath(1'b0), // input
.sys_reset(rst_125mhz_int), // input
@ -1335,6 +1335,22 @@ qsfp_cmac_inst (
.drp_we(1'b0) // input
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp_ref_clk;
assign ptp_sample_clk = clk_125mhz_int;
sync_reset #(
.N(4)
)
sync_reset_ptp_rst_inst (
.clk(ptp_clk),
.rst(rst_125mhz_int),
.out(ptp_rst)
);
assign qsfp_led_stat_g = qsfp_rx_status;
fpga_core #(
@ -1355,13 +1371,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1481,6 +1495,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

39
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_SEPARATE_RX_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
@ -185,6 +183,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -362,6 +367,9 @@ end
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -534,9 +542,9 @@ end
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -705,13 +713,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -982,10 +988,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -138,8 +138,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 1
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
@ -244,7 +247,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
@ -332,7 +338,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)

12
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp_rx_clk, 3.102, units="ns").start())
cocotb.start_soon(Clock(dut.qsfp_tx_clk, 3.102, units="ns").start())
@ -298,12 +302,14 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_rx_rst.setimmediatevalue(0)
self.dut.qsfp_tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp_rx_rst.setimmediatevalue(1)
self.dut.qsfp_tx_rst.setimmediatevalue(1)
@ -313,6 +319,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_rx_rst.setimmediatevalue(0)
self.dut.qsfp_tx_rst.setimmediatevalue(0)
@ -626,8 +633,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0

1
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -131,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU50/fpga_25g/fpga/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -131,6 +131,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl
View File

@ -97,6 +97,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "1"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "0"
dict set params PTP_PEROUT_COUNT "1"

34
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -60,6 +60,7 @@ module fpga #
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -215,14 +216,10 @@ module fpga #
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024;
parameter PTP_CLK_PERIOD_NS_DENOM = 165;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter PTP_USE_SAMPLE_CLOCK = 1;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -1138,6 +1135,14 @@ qsfp_phy_quad_inst (
.phy_4_rx_prbs31_enable(qsfp_rx_prbs31_enable_4_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_clk = qsfp_mgt_refclk_0_bufg;
assign ptp_rst = qsfp_rst;
assign ptp_sample_clk = clk_125mhz_int;
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
@ -1156,13 +1161,11 @@ fpga_core #(
.PORT_MASK(PORT_MASK),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
@ -1281,6 +1284,13 @@ core_inst (
.clk_250mhz(pcie_user_clk),
.rst_250mhz(pcie_user_reset),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/

43
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -59,14 +59,12 @@ module fpga_core #
parameter PORT_MASK = 0,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 1024,
parameter PTP_CLK_PERIOD_NS_DENOM = 165,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 1,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 1,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
@ -191,6 +189,13 @@ module fpga_core #
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
@ -419,6 +424,9 @@ wire axil_csr_rready;
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
@ -639,9 +647,9 @@ qsfp_rb_drp_inst (
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge ptp_clk) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
pps_led_counter_reg <= 80566406;
end else if (pps_led_counter_reg > 0) begin
pps_led_counter_reg <= pps_led_counter_reg - 1;
end
@ -694,8 +702,8 @@ tdma_ber_inst (
.s_axil_rresp(axil_csr_rresp),
.s_axil_rvalid(axil_csr_rvalid),
.s_axil_rready(axil_csr_rready),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step)
.ptp_ts_96(ptp_sync_ts_96),
.ptp_ts_step(ptp_sync_ts_step)
);
assign qsfp_led_act = pps_led_reg;
@ -875,13 +883,11 @@ mqnic_core_pcie_us #(
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
@ -1152,10 +1158,15 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),

11
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -146,8 +146,11 @@ export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK ?= 0
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM = 1024
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 165
export PARAM_PTP_CLOCK_PIPELINE ?= 1
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
export PARAM_PTP_PORT_CDC_PIPELINE ?= 1
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
@ -251,7 +254,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
@ -338,7 +344,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
COMPILE_ARGS += -GPORT_MASK=$(PARAM_PORT_MASK)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)

12
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -268,6 +268,10 @@ class TB(object):
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp_rx_clk_1, 2.56, units="ns").start())
self.qsfp_1_source = XgmiiSource(dut.qsfp_rxd_1, dut.qsfp_rxc_1, dut.qsfp_rx_clk_1, dut.qsfp_rx_rst_1)
@ -313,6 +317,7 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp_rx_rst_2.setimmediatevalue(0)
@ -325,6 +330,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp_rx_rst_1.setimmediatevalue(1)
self.dut.qsfp_tx_rst_1.setimmediatevalue(1)
self.dut.qsfp_rx_rst_2.setimmediatevalue(1)
@ -340,6 +346,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp_rx_rst_1.setimmediatevalue(0)
self.dut.qsfp_tx_rst_1.setimmediatevalue(0)
self.dut.qsfp_rx_rst_2.setimmediatevalue(0)
@ -653,8 +660,11 @@ def test_fpga_core(request):
parameters['PORT_MASK'] = 0
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
parameters['PTP_CLOCK_PIPELINE'] = 1
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 1
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
View File

@ -126,6 +126,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
View File

@ -126,6 +126,7 @@ XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl

1
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl
View File

@ -88,6 +88,7 @@ dict set params PORT_MASK "0"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"

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