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Fix VCU118 CMAC reference clocks

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This commit is contained in:
Alex Forencich 2020-07-14 10:47:18 -07:00
parent 20eac98bde
commit 837a390567
2 changed files with 2 additions and 2 deletions
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2
fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus_0.tcl
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@ -4,7 +4,7 @@ create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usp
set_property -dict [list \ set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \ CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \ CONFIG.NUM_LANES {4x25} \
CONFIG.GT_REF_CLK_FREQ {161.1328125} \ CONFIG.GT_REF_CLK_FREQ {156.25} \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {0} \

2
fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus_1.tcl
View File

@ -4,7 +4,7 @@ create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usp
set_property -dict [list \ set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \ CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \ CONFIG.NUM_LANES {4x25} \
CONFIG.GT_REF_CLK_FREQ {161.1328125} \ CONFIG.GT_REF_CLK_FREQ {156.25} \
CONFIG.USER_INTERFACE {AXIS} \ CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \ CONFIG.GT_DRP_CLK {125} \
CONFIG.TX_FLOW_CONTROL {0} \ CONFIG.TX_FLOW_CONTROL {0} \