diff --git a/lib/axis/README.md b/lib/axis/README.md index 8ea4b149d..397ca5053 100644 --- a/lib/axis/README.md +++ b/lib/axis/README.md @@ -205,7 +205,7 @@ Parametrizable priority encoder. DATA_WIDTH : width of tdata signal KEEP_ENABLE : enable tkeep signal (default DATA_WIDTH>8) - KEEP_WIDTH : width of tkeep signal (default DATA_WIDTH/8) + KEEP_WIDTH : width of tkeep signal (default (DATA_WIDTH+7)/8) LAST_ENABLE : enable tlast signal ID_ENABLE : enable tid signal ID_WIDTH : width of tid signal diff --git a/lib/axis/rtl/axis_adapter.v b/lib/axis/rtl/axis_adapter.v index cb3325106..51aa226ac 100644 --- a/lib/axis/rtl/axis_adapter.v +++ b/lib/axis/rtl/axis_adapter.v @@ -39,14 +39,14 @@ module axis_adapter # // If disabled, tkeep assumed to be 1'b1 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), // tkeep signal width (words per cycle) on input interface - parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8), // Width of output AXI stream interface in bits parameter M_DATA_WIDTH = 8, // Propagate tkeep signal on output interface // If disabled, tkeep assumed to be 1'b1 parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), // tkeep signal width (words per cycle) on output interface - parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_arb_mux.v b/lib/axis/rtl/axis_arb_mux.v index 83bdd4f6b..43a588f41 100644 --- a/lib/axis/rtl/axis_arb_mux.v +++ b/lib/axis/rtl/axis_arb_mux.v @@ -40,7 +40,7 @@ module axis_arb_mux # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_arb_mux_wrap.py b/lib/axis/rtl/axis_arb_mux_wrap.py index 091d36612..076d8a1a9 100755 --- a/lib/axis/rtl/axis_arb_mux_wrap.py +++ b/lib/axis/rtl/axis_arb_mux_wrap.py @@ -75,7 +75,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_async_fifo.v b/lib/axis/rtl/axis_async_fifo.v index 2d89f2da4..4f1e3601e 100644 --- a/lib/axis/rtl/axis_async_fifo.v +++ b/lib/axis/rtl/axis_async_fifo.v @@ -43,7 +43,7 @@ module axis_async_fifo # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_async_fifo_adapter.v b/lib/axis/rtl/axis_async_fifo_adapter.v index 76a293a69..848fcf501 100644 --- a/lib/axis/rtl/axis_async_fifo_adapter.v +++ b/lib/axis/rtl/axis_async_fifo_adapter.v @@ -43,14 +43,14 @@ module axis_async_fifo_adapter # // If disabled, tkeep assumed to be 1'b1 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), // tkeep signal width (words per cycle) on input interface - parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8), // Width of output AXI stream interface in bits parameter M_DATA_WIDTH = 8, // Propagate tkeep signal on output interface // If disabled, tkeep assumed to be 1'b1 parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), // tkeep signal width (words per cycle) on output interface - parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_broadcast.v b/lib/axis/rtl/axis_broadcast.v index 16137ea73..34fafd266 100644 --- a/lib/axis/rtl/axis_broadcast.v +++ b/lib/axis/rtl/axis_broadcast.v @@ -40,7 +40,7 @@ module axis_broadcast # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_broadcast_wrap.py b/lib/axis/rtl/axis_broadcast_wrap.py index e755a20ea..acd31571c 100755 --- a/lib/axis/rtl/axis_broadcast_wrap.py +++ b/lib/axis/rtl/axis_broadcast_wrap.py @@ -75,7 +75,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_crosspoint.v b/lib/axis/rtl/axis_crosspoint.v index c6574d269..7fde4ab4e 100644 --- a/lib/axis/rtl/axis_crosspoint.v +++ b/lib/axis/rtl/axis_crosspoint.v @@ -42,7 +42,7 @@ module axis_crosspoint # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_crosspoint_wrap.py b/lib/axis/rtl/axis_crosspoint_wrap.py index f7396532b..0646ec8a8 100755 --- a/lib/axis/rtl/axis_crosspoint_wrap.py +++ b/lib/axis/rtl/axis_crosspoint_wrap.py @@ -81,7 +81,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_demux.v b/lib/axis/rtl/axis_demux.v index 796799e55..7edd757f5 100644 --- a/lib/axis/rtl/axis_demux.v +++ b/lib/axis/rtl/axis_demux.v @@ -40,7 +40,7 @@ module axis_demux # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_demux_wrap.py b/lib/axis/rtl/axis_demux_wrap.py index 344c8bcb0..bc7311765 100755 --- a/lib/axis/rtl/axis_demux_wrap.py +++ b/lib/axis/rtl/axis_demux_wrap.py @@ -75,7 +75,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_fifo.v b/lib/axis/rtl/axis_fifo.v index bf3be6e19..c93147461 100644 --- a/lib/axis/rtl/axis_fifo.v +++ b/lib/axis/rtl/axis_fifo.v @@ -43,7 +43,7 @@ module axis_fifo # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_fifo_adapter.v b/lib/axis/rtl/axis_fifo_adapter.v index 7b43b0070..095d6ce74 100644 --- a/lib/axis/rtl/axis_fifo_adapter.v +++ b/lib/axis/rtl/axis_fifo_adapter.v @@ -43,14 +43,14 @@ module axis_fifo_adapter # // If disabled, tkeep assumed to be 1'b1 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), // tkeep signal width (words per cycle) on input interface - parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8), // Width of output AXI stream interface in bits parameter M_DATA_WIDTH = 8, // Propagate tkeep signal on output interface // If disabled, tkeep assumed to be 1'b1 parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), // tkeep signal width (words per cycle) on output interface - parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_frame_len.v b/lib/axis/rtl/axis_frame_len.v index a1f75e5d7..49ce097a1 100644 --- a/lib/axis/rtl/axis_frame_len.v +++ b/lib/axis/rtl/axis_frame_len.v @@ -39,7 +39,7 @@ module axis_frame_len # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Width of length counter parameter LEN_WIDTH = 16 ) diff --git a/lib/axis/rtl/axis_frame_length_adjust.v b/lib/axis/rtl/axis_frame_length_adjust.v index 42550ad00..92fb2ec11 100644 --- a/lib/axis/rtl/axis_frame_length_adjust.v +++ b/lib/axis/rtl/axis_frame_length_adjust.v @@ -39,7 +39,7 @@ module axis_frame_length_adjust # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_frame_length_adjust_fifo.v b/lib/axis/rtl/axis_frame_length_adjust_fifo.v index a580cee9d..f2bc4a065 100644 --- a/lib/axis/rtl/axis_frame_length_adjust_fifo.v +++ b/lib/axis/rtl/axis_frame_length_adjust_fifo.v @@ -39,7 +39,7 @@ module axis_frame_length_adjust_fifo # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_mux.v b/lib/axis/rtl/axis_mux.v index ba97d9390..ab021d3ef 100644 --- a/lib/axis/rtl/axis_mux.v +++ b/lib/axis/rtl/axis_mux.v @@ -40,7 +40,7 @@ module axis_mux # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_mux_wrap.py b/lib/axis/rtl/axis_mux_wrap.py index bc1b8325b..00698cd0d 100755 --- a/lib/axis/rtl/axis_mux_wrap.py +++ b/lib/axis/rtl/axis_mux_wrap.py @@ -75,7 +75,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/rtl/axis_pipeline_fifo.v b/lib/axis/rtl/axis_pipeline_fifo.v index 0da814573..4c194bf7e 100644 --- a/lib/axis/rtl/axis_pipeline_fifo.v +++ b/lib/axis/rtl/axis_pipeline_fifo.v @@ -38,7 +38,7 @@ module axis_pipeline_fifo # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_pipeline_register.v b/lib/axis/rtl/axis_pipeline_register.v index 1e22ffcc9..9715dca4b 100644 --- a/lib/axis/rtl/axis_pipeline_register.v +++ b/lib/axis/rtl/axis_pipeline_register.v @@ -38,7 +38,7 @@ module axis_pipeline_register # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_ram_switch.v b/lib/axis/rtl/axis_ram_switch.v index ed831fe28..ac31dcca2 100644 --- a/lib/axis/rtl/axis_ram_switch.v +++ b/lib/axis/rtl/axis_ram_switch.v @@ -52,13 +52,13 @@ module axis_ram_switch # // Propagate tkeep signal parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8), // Width of output AXI stream interfaces in bits parameter M_DATA_WIDTH = 8, // Propagate tkeep signal parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_ram_switch_wrap.py b/lib/axis/rtl/axis_ram_switch_wrap.py index 45adfed5b..1dbd223a8 100755 --- a/lib/axis/rtl/axis_ram_switch_wrap.py +++ b/lib/axis/rtl/axis_ram_switch_wrap.py @@ -91,13 +91,13 @@ module {{name}} # // Propagate tkeep signal parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + parameter S_KEEP_WIDTH = ((S_DATA_WIDTH+7)/8), // Width of output AXI stream interfaces in bits parameter M_DATA_WIDTH = 8, // Propagate tkeep signal parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + parameter M_KEEP_WIDTH = ((M_DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_rate_limit.v b/lib/axis/rtl/axis_rate_limit.v index 3f91b4cbc..24ec9546a 100644 --- a/lib/axis/rtl/axis_rate_limit.v +++ b/lib/axis/rtl/axis_rate_limit.v @@ -39,7 +39,7 @@ module axis_rate_limit # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_register.v b/lib/axis/rtl/axis_register.v index fbd245c1f..7e8f10931 100644 --- a/lib/axis/rtl/axis_register.v +++ b/lib/axis/rtl/axis_register.v @@ -38,7 +38,7 @@ module axis_register # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_srl_fifo.v b/lib/axis/rtl/axis_srl_fifo.v index e0cc4164a..7eabf8f45 100644 --- a/lib/axis/rtl/axis_srl_fifo.v +++ b/lib/axis/rtl/axis_srl_fifo.v @@ -38,7 +38,7 @@ module axis_srl_fifo # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_srl_register.v b/lib/axis/rtl/axis_srl_register.v index 4bfaeaafc..f0e9efee2 100644 --- a/lib/axis/rtl/axis_srl_register.v +++ b/lib/axis/rtl/axis_srl_register.v @@ -38,7 +38,7 @@ module axis_srl_register # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tlast signal parameter LAST_ENABLE = 1, // Propagate tid signal diff --git a/lib/axis/rtl/axis_stat_counter.v b/lib/axis/rtl/axis_stat_counter.v index c59c441be..cc0476083 100644 --- a/lib/axis/rtl/axis_stat_counter.v +++ b/lib/axis/rtl/axis_stat_counter.v @@ -39,7 +39,7 @@ module axis_stat_counter # // If disabled, tkeep assumed to be 1'b1 parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Prepend data with tag parameter TAG_ENABLE = 1, // Tag field width diff --git a/lib/axis/rtl/axis_switch.v b/lib/axis/rtl/axis_switch.v index c949b700b..d791294bb 100644 --- a/lib/axis/rtl/axis_switch.v +++ b/lib/axis/rtl/axis_switch.v @@ -42,7 +42,7 @@ module axis_switch # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_switch_wrap.py b/lib/axis/rtl/axis_switch_wrap.py index 0af37e02a..e3e13dc39 100755 --- a/lib/axis/rtl/axis_switch_wrap.py +++ b/lib/axis/rtl/axis_switch_wrap.py @@ -81,7 +81,7 @@ module {{name}} # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // input tid signal width diff --git a/lib/axis/rtl/axis_tap.v b/lib/axis/rtl/axis_tap.v index a9c7e19e1..13966adcb 100644 --- a/lib/axis/rtl/axis_tap.v +++ b/lib/axis/rtl/axis_tap.v @@ -38,7 +38,7 @@ module axis_tap # // Propagate tkeep signal parameter KEEP_ENABLE = (DATA_WIDTH>8), // tkeep signal width (words per cycle) - parameter KEEP_WIDTH = (DATA_WIDTH/8), + parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8), // Propagate tid signal parameter ID_ENABLE = 0, // tid signal width diff --git a/lib/axis/tb/axis_adapter/Makefile b/lib/axis/tb/axis_adapter/Makefile index af559301a..621657d76 100644 --- a/lib/axis/tb/axis_adapter/Makefile +++ b/lib/axis/tb/axis_adapter/Makefile @@ -34,10 +34,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_S_DATA_WIDTH ?= 8 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 ) +export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) export PARAM_M_DATA_WIDTH ?= 8 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 ) +export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_adapter/test_axis_adapter.py b/lib/axis/tb/axis_adapter/test_axis_adapter.py index addc72745..5997d61ef 100644 --- a/lib/axis/tb/axis_adapter/test_axis_adapter.py +++ b/lib/axis/tb/axis_adapter/test_axis_adapter.py @@ -227,10 +227,10 @@ def test_axis_register(request, s_data_width, m_data_width): parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) - parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8 + parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) - parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8 + parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_arb_mux/Makefile b/lib/axis/tb/axis_arb_mux/Makefile index 962af950f..936f22b1c 100644 --- a/lib/axis/tb/axis_arb_mux/Makefile +++ b/lib/axis/tb/axis_arb_mux/Makefile @@ -40,7 +40,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_S_ID_WIDTH ?= 8 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(PORTS)-1).bit_length())") diff --git a/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py b/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py index ec23a41c7..187964b32 100644 --- a/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py +++ b/lib/axis/tb/axis_arb_mux/test_axis_arb_mux.py @@ -344,7 +344,7 @@ def test_axis_arb_mux(request, ports, data_width, round_robin): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['S_ID_WIDTH'] = 8 parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (ports-1).bit_length() diff --git a/lib/axis/tb/axis_async_fifo/Makefile b/lib/axis/tb/axis_async_fifo/Makefile index 75efe9944..f301f8b45 100644 --- a/lib/axis/tb/axis_async_fifo/Makefile +++ b/lib/axis/tb/axis_async_fifo/Makefile @@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v export PARAM_DEPTH ?= 1024 export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py b/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py index 223a7e36c..fb3026d8b 100644 --- a/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py +++ b/lib/axis/tb/axis_async_fifo/test_axis_async_fifo.py @@ -539,7 +539,7 @@ def test_axis_async_fifo(request, data_width, frame_fifo, drop_oversize_frame, d parameters['DEPTH'] = 1024 parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_async_fifo_adapter/Makefile b/lib/axis/tb/axis_async_fifo_adapter/Makefile index 1471541eb..c193ebb0d 100644 --- a/lib/axis/tb/axis_async_fifo_adapter/Makefile +++ b/lib/axis/tb/axis_async_fifo_adapter/Makefile @@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v export PARAM_DEPTH ?= 1024 export PARAM_S_DATA_WIDTH ?= 8 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 ) +export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) export PARAM_M_DATA_WIDTH ?= 8 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 ) +export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py b/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py index 6ff2ac88d..bae15ef00 100644 --- a/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py +++ b/lib/axis/tb/axis_async_fifo_adapter/test_axis_async_fifo_adapter.py @@ -536,10 +536,10 @@ def test_axis_async_fifo_adapter(request, s_data_width, m_data_width, frame_fifo parameters['DEPTH'] = 1024 parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) - parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8 + parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) - parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8 + parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_broadcast/Makefile b/lib/axis/tb/axis_broadcast/Makefile index 8bd2282a3..7b66215cd 100644 --- a/lib/axis/tb/axis_broadcast/Makefile +++ b/lib/axis/tb/axis_broadcast/Makefile @@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_broadcast/test_axis_broadcast.py b/lib/axis/tb/axis_broadcast/test_axis_broadcast.py index 8bc7ac9a9..caca51885 100644 --- a/lib/axis/tb/axis_broadcast/test_axis_broadcast.py +++ b/lib/axis/tb/axis_broadcast/test_axis_broadcast.py @@ -170,7 +170,7 @@ def test_axis_broadcast(request, ports, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_demux/Makefile b/lib/axis/tb/axis_demux/Makefile index 6fd45472c..8822019d2 100644 --- a/lib/axis/tb/axis_demux/Makefile +++ b/lib/axis/tb/axis_demux/Makefile @@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 diff --git a/lib/axis/tb/axis_demux/test_axis_demux.py b/lib/axis/tb/axis_demux/test_axis_demux.py index 832b02118..bce6b471c 100644 --- a/lib/axis/tb/axis_demux/test_axis_demux.py +++ b/lib/axis/tb/axis_demux/test_axis_demux.py @@ -186,7 +186,7 @@ def test_axis_demux(request, ports, data_width, tdest_route): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_fifo/Makefile b/lib/axis/tb/axis_fifo/Makefile index 9073da6cc..fabad14d2 100644 --- a/lib/axis/tb/axis_fifo/Makefile +++ b/lib/axis/tb/axis_fifo/Makefile @@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v export PARAM_DEPTH ?= 1024 export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_fifo/test_axis_fifo.py b/lib/axis/tb/axis_fifo/test_axis_fifo.py index 61b5351de..db13ca87b 100644 --- a/lib/axis/tb/axis_fifo/test_axis_fifo.py +++ b/lib/axis/tb/axis_fifo/test_axis_fifo.py @@ -329,7 +329,7 @@ def test_axis_fifo(request, data_width, frame_fifo, drop_oversize_frame, drop_ba parameters['DEPTH'] = 1024 parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_fifo_adapter/Makefile b/lib/axis/tb/axis_fifo_adapter/Makefile index 786c51c53..86e3f2f3c 100644 --- a/lib/axis/tb/axis_fifo_adapter/Makefile +++ b/lib/axis/tb/axis_fifo_adapter/Makefile @@ -37,10 +37,10 @@ VERILOG_SOURCES += ../../rtl/axis_adapter.v export PARAM_DEPTH ?= 1024 export PARAM_S_DATA_WIDTH ?= 8 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 ) +export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) export PARAM_M_DATA_WIDTH ?= 8 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 ) +export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py b/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py index 6ff21ca98..bc3fc76ec 100644 --- a/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py +++ b/lib/axis/tb/axis_fifo_adapter/test_axis_fifo_adapter.py @@ -332,10 +332,10 @@ def test_axis_fifo_adapter(request, s_data_width, m_data_width, frame_fifo, drop parameters['DEPTH'] = 1024 parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) - parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8 + parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) - parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8 + parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_frame_length_adjust/Makefile b/lib/axis/tb/axis_frame_length_adjust/Makefile index 0cec922d8..abe6052c3 100644 --- a/lib/axis/tb/axis_frame_length_adjust/Makefile +++ b/lib/axis/tb/axis_frame_length_adjust/Makefile @@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 diff --git a/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py b/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py index 5817f5c0d..260c9fe52 100644 --- a/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py +++ b/lib/axis/tb/axis_frame_length_adjust/test_axis_frame_length_adjust.py @@ -214,7 +214,7 @@ def test_axis_frame_length_adjust(request, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile b/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile index ed886c2a2..59b5d822c 100644 --- a/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile +++ b/lib/axis/tb/axis_frame_length_adjust_fifo/Makefile @@ -36,7 +36,7 @@ VERILOG_SOURCES += ../../rtl/axis_fifo.v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 diff --git a/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py b/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py index b3403cd00..0ad01cf86 100644 --- a/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py +++ b/lib/axis/tb/axis_frame_length_adjust_fifo/test_axis_frame_length_adjust_fifo.py @@ -306,7 +306,7 @@ def test_axis_frame_length_adjust_fifo(request, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_mux/Makefile b/lib/axis/tb/axis_mux/Makefile index 5323a4d3f..247a0784c 100644 --- a/lib/axis/tb/axis_mux/Makefile +++ b/lib/axis/tb/axis_mux/Makefile @@ -38,7 +38,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 diff --git a/lib/axis/tb/axis_mux/test_axis_mux.py b/lib/axis/tb/axis_mux/test_axis_mux.py index 217b03ce6..d722acf11 100644 --- a/lib/axis/tb/axis_mux/test_axis_mux.py +++ b/lib/axis/tb/axis_mux/test_axis_mux.py @@ -206,7 +206,7 @@ def test_axis_mux(request, ports, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 parameters['DEST_ENABLE'] = 1 diff --git a/lib/axis/tb/axis_pipeline_fifo/Makefile b/lib/axis/tb/axis_pipeline_fifo/Makefile index cfb36c0b3..a356a55e1 100644 --- a/lib/axis/tb/axis_pipeline_fifo/Makefile +++ b/lib/axis/tb/axis_pipeline_fifo/Makefile @@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py b/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py index 830b03376..575598579 100644 --- a/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py +++ b/lib/axis/tb/axis_pipeline_fifo/test_axis_pipeline_fifo.py @@ -317,7 +317,7 @@ def test_axis_pipeline_fifo(request, length, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_pipeline_register/Makefile b/lib/axis/tb/axis_pipeline_register/Makefile index b635f7289..13e6e6cf5 100644 --- a/lib/axis/tb/axis_pipeline_register/Makefile +++ b/lib/axis/tb/axis_pipeline_register/Makefile @@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/axis_register.v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py b/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py index a971e8e19..2ea13bf52 100644 --- a/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py +++ b/lib/axis/tb/axis_pipeline_register/test_axis_pipeline_register.py @@ -229,7 +229,7 @@ def test_axis_pipeline_register(request, length, data_width, reg_type): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_ram_switch/Makefile b/lib/axis/tb/axis_ram_switch/Makefile index adfea859f..6b07dabe7 100644 --- a/lib/axis/tb/axis_ram_switch/Makefile +++ b/lib/axis/tb/axis_ram_switch/Makefile @@ -45,10 +45,10 @@ export PARAM_CMD_FIFO_DEPTH ?= 32 export PARAM_SPEEDUP ?= 0 export PARAM_S_DATA_WIDTH ?= 8 export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 ) -export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 ) +export PARAM_S_KEEP_WIDTH ?= $(shell expr \( $(PARAM_S_DATA_WIDTH) + 7 \) / 8 ) export PARAM_M_DATA_WIDTH ?= 8 export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 ) -export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 ) +export PARAM_M_KEEP_WIDTH ?= $(shell expr \( $(PARAM_M_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_S_ID_WIDTH ?= 16 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") diff --git a/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py b/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py index 422fcd843..6bc3fd1ee 100644 --- a/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py +++ b/lib/axis/tb/axis_ram_switch/test_axis_ram_switch.py @@ -356,10 +356,10 @@ def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width): parameters['SPEEDUP'] = 0 parameters['S_DATA_WIDTH'] = s_data_width parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8) - parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8 + parameters['S_KEEP_WIDTH'] = (parameters['S_DATA_WIDTH'] + 7) // 8 parameters['M_DATA_WIDTH'] = m_data_width parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8) - parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8 + parameters['M_KEEP_WIDTH'] = (parameters['M_DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['S_ID_WIDTH'] = 16 parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length() diff --git a/lib/axis/tb/axis_rate_limit/Makefile b/lib/axis/tb/axis_rate_limit/Makefile index 4da3e0bb0..002d611ce 100644 --- a/lib/axis/tb/axis_rate_limit/Makefile +++ b/lib/axis/tb/axis_rate_limit/Makefile @@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py b/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py index 170419df2..f54828e7c 100644 --- a/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py +++ b/lib/axis/tb/axis_rate_limit/test_axis_rate_limit.py @@ -187,7 +187,7 @@ def test_axis_rate_limit(request, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_register/Makefile b/lib/axis/tb/axis_register/Makefile index 20747961b..0a2e2e9de 100644 --- a/lib/axis/tb/axis_register/Makefile +++ b/lib/axis/tb/axis_register/Makefile @@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_register/test_axis_register.py b/lib/axis/tb/axis_register/test_axis_register.py index bd9e3e794..55e4c7864 100644 --- a/lib/axis/tb/axis_register/test_axis_register.py +++ b/lib/axis/tb/axis_register/test_axis_register.py @@ -227,7 +227,7 @@ def test_axis_register(request, data_width, reg_type): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_srl_fifo/Makefile b/lib/axis/tb/axis_srl_fifo/Makefile index 35b77686b..43b43716c 100644 --- a/lib/axis/tb/axis_srl_fifo/Makefile +++ b/lib/axis/tb/axis_srl_fifo/Makefile @@ -35,7 +35,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v export PARAM_DEPTH ?= 1024 export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 export PARAM_DEST_ENABLE ?= 1 diff --git a/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py b/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py index e18fd8a88..0e7281a81 100644 --- a/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py +++ b/lib/axis/tb/axis_srl_fifo/test_axis_srl_fifo.py @@ -317,7 +317,7 @@ def test_axis_srl_fifo(request, data_width): parameters['DEPTH'] = 1024 parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_srl_register/Makefile b/lib/axis/tb/axis_srl_register/Makefile index d1842025d..d7c66b764 100644 --- a/lib/axis/tb/axis_srl_register/Makefile +++ b/lib/axis/tb/axis_srl_register/Makefile @@ -34,7 +34,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_LAST_ENABLE ?= 1 export PARAM_ID_ENABLE ?= 1 export PARAM_ID_WIDTH ?= 8 diff --git a/lib/axis/tb/axis_srl_register/test_axis_srl_register.py b/lib/axis/tb/axis_srl_register/test_axis_srl_register.py index 4dd1c0c37..7be3ad873 100644 --- a/lib/axis/tb/axis_srl_register/test_axis_srl_register.py +++ b/lib/axis/tb/axis_srl_register/test_axis_srl_register.py @@ -226,7 +226,7 @@ def test_axis_srl_register(request, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['LAST_ENABLE'] = 1 parameters['ID_ENABLE'] = 1 parameters['ID_WIDTH'] = 8 diff --git a/lib/axis/tb/axis_switch/Makefile b/lib/axis/tb/axis_switch/Makefile index 9cf555993..a59fb3dbe 100644 --- a/lib/axis/tb/axis_switch/Makefile +++ b/lib/axis/tb/axis_switch/Makefile @@ -42,7 +42,7 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v # module parameters export PARAM_DATA_WIDTH ?= 8 export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 ) -export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 ) +export PARAM_KEEP_WIDTH ?= $(shell expr \( $(PARAM_DATA_WIDTH) + 7 \) / 8 ) export PARAM_ID_ENABLE ?= 1 export PARAM_S_ID_WIDTH ?= 16 export PARAM_M_ID_WIDTH ?= $(shell python -c "print($(PARAM_S_ID_WIDTH) + ($(S_COUNT)-1).bit_length())") diff --git a/lib/axis/tb/axis_switch/test_axis_switch.py b/lib/axis/tb/axis_switch/test_axis_switch.py index 9e250e333..c2da5a08e 100644 --- a/lib/axis/tb/axis_switch/test_axis_switch.py +++ b/lib/axis/tb/axis_switch/test_axis_switch.py @@ -351,7 +351,7 @@ def test_axis_switch(request, s_count, m_count, data_width): parameters['DATA_WIDTH'] = data_width parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8) - parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8 + parameters['KEEP_WIDTH'] = (parameters['DATA_WIDTH'] + 7) // 8 parameters['ID_ENABLE'] = 1 parameters['S_ID_WIDTH'] = 16 parameters['M_ID_WIDTH'] = parameters['S_ID_WIDTH'] + (s_count-1).bit_length() diff --git a/lib/axis/tox.ini b/lib/axis/tox.ini index 2fc6307f2..0fba1b4bd 100644 --- a/lib/axis/tox.ini +++ b/lib/axis/tox.ini @@ -1,21 +1,23 @@ # tox configuration [tox] -envlist = py39 +envlist = py3 skipsdist = True +minversion = 3.2.0 +requires = virtualenv >= 16.1 [gh-actions] python = - 3.9: py39 + 3.9: py3 [testenv] deps = - pytest - pytest-xdist - pytest-split - cocotb - cocotb-test - cocotbext-axi - jinja2 + pytest == 6.2.5 + pytest-xdist == 2.4.0 + pytest-split == 0.4.0 + cocotb == 1.6.1 + cocotb-test == 0.2.1 + cocotbext-axi == 0.1.16 + jinja2 == 3.0.3 commands = pytest -n auto {posargs}