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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich 2022-07-18 22:27:08 -07:00
parent debf36a01e
commit 84c6eb95a6
4 changed files with 11 additions and 1 deletions
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1
README.md
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@ -29,6 +29,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Cisco Nexus K3P-Q (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)

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docs/source/devicelist.rst
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@ -24,6 +24,7 @@ This section details PCIe form-factor targets, which interface with a separate h
Silicom fb2CG\@KU15P XCKU15P-2FFVE1760E 0x1c2ca00e
Digilent NetFPGA SUME XC7V690T-3FFG1761 0x10ee7028
BittWare XUP-P3R XCVU9P-2FLGB2104E 0x12ba9823
BittWare 250-SoC XCZU19EG-2FFVD1760E 0x198a250e
Intel DK-DEV-1SMX-H-A 1SM21BHU2F53E1VG 0x11720001
Intel DK-DEV-1SMC-H-A 1SM21CHU1F53E1VG 0x11720001
Xilinx Alveo U50 XCU50-2FSVH2104E 0x10ee9032
@ -48,6 +49,7 @@ This section details PCIe form-factor targets, which interface with a separate h
Nexus K3P-Q Gen 3 x8 2x QSFP28 8 GB DDR4 (1G x72) \-
fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \-
NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \-
250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (512M x72) \-
XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \-
DK-DEV-1SMX-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB
DK-DEV-1SMC-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB
@ -73,6 +75,7 @@ This section details PCIe form-factor targets, which interface with a separate h
Nexus K3P-Q Y Y Y
fb2CG\@KU15P Y Y Y
NetFPGA SUME Y N :sup:`7` N :sup:`8`
250-SoC Y N N :sup:`9`
XUP-P3R Y Y Y
DK-DEV-1SMX-H-A N N N
DK-DEV-1SMC-H-A N N N
@ -83,7 +86,7 @@ This section details PCIe form-factor targets, which interface with a separate h
VCU108 Y Y :sup:`5` Y
VCU118 Y Y :sup:`5` Y
VCU1525 Y Y :sup:`5` Y
ZCU106 Y Y :sup:`5` Y
ZCU106 Y Y :sup:`5` N :sup:`9`
======================= ============ ============ ==========
- :sup:`1` I2C access to optical modules
@ -94,6 +97,7 @@ This section details PCIe form-factor targets, which interface with a separate h
- :sup:`6` MAC available from BMC, but accessing BMC is not yet implemented
- :sup:`7` No on-board EEPROM
- :sup:`8` Flash sits behind CPLD, not currently exposed via PCIe
- :sup:`9` Flash sits behind Zynq SoC, not currently exposed via PCIe
.. table:: Summary of the board-specific design variants and some important configuration parameters.
@ -118,6 +122,9 @@ This section details PCIe form-factor targets, which interface with a separate h
fb2CG\@KU15P mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
fb2CG\@KU15P mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
NetFPGA SUME mqnic/fpga/fpga 1x1 256/512 10G RR
250-SoC mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
250-SoC mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
250-SoC mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G RR
XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G RR
XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR

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docs/source/index.rst
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@ -21,6 +21,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Cisco Nexus K3P-Q (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG\@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)

1
docs/source/modules/mqnic_core.rst
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@ -696,6 +696,7 @@ Ports
ptp_rst in 1 PTP reset
ptp_sample_clk in 1 PTP sample clock
ptp_pps out 1 PTP pulse-per-second (synchronous to ptp_clk)
ptp_pps_str out 1 PTP pulse-per-second (stretched) (synchronous to ptp_clk)
ptp_ts_96 out PTP_TS_WIDTH current PTP time (synchronous to ptp_clk)
ptp_ts_step out 1 PTP clock step (synchronous to ptp_clk)
ptp_sync_pps out 1 PTP pulse-per-second (synchronous to clk)