From 84c6eb95a6285caac878267dfa0f87da16faf2f6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 18 Jul 2022 22:27:08 -0700 Subject: [PATCH] Update docs Signed-off-by: Alex Forencich --- README.md | 1 + docs/source/devicelist.rst | 9 ++++++++- docs/source/index.rst | 1 + docs/source/modules/mqnic_core.rst | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 824830312..5ac1caf81 100644 --- a/README.md +++ b/README.md @@ -29,6 +29,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Cisco Nexus K3P-Q (Xilinx Kintex UltraScale+ XCKU3P) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * NetFPGA SUME (Xilinx Virtex 7 XC7V690T) +* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG) * BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P) * Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) diff --git a/docs/source/devicelist.rst b/docs/source/devicelist.rst index 46a0452b5..543bb39ec 100644 --- a/docs/source/devicelist.rst +++ b/docs/source/devicelist.rst @@ -24,6 +24,7 @@ This section details PCIe form-factor targets, which interface with a separate h Silicom fb2CG\@KU15P XCKU15P-2FFVE1760E 0x1c2ca00e Digilent NetFPGA SUME XC7V690T-3FFG1761 0x10ee7028 BittWare XUP-P3R XCVU9P-2FLGB2104E 0x12ba9823 + BittWare 250-SoC XCZU19EG-2FFVD1760E 0x198a250e Intel DK-DEV-1SMX-H-A 1SM21BHU2F53E1VG 0x11720001 Intel DK-DEV-1SMC-H-A 1SM21CHU1F53E1VG 0x11720001 Xilinx Alveo U50 XCU50-2FSVH2104E 0x10ee9032 @@ -48,6 +49,7 @@ This section details PCIe form-factor targets, which interface with a separate h Nexus K3P-Q Gen 3 x8 2x QSFP28 8 GB DDR4 (1G x72) \- fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \- NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \- + 250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (512M x72) \- XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \- DK-DEV-1SMX-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB DK-DEV-1SMC-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB @@ -73,6 +75,7 @@ This section details PCIe form-factor targets, which interface with a separate h Nexus K3P-Q Y Y Y fb2CG\@KU15P Y Y Y NetFPGA SUME Y N :sup:`7` N :sup:`8` + 250-SoC Y N N :sup:`9` XUP-P3R Y Y Y DK-DEV-1SMX-H-A N N N DK-DEV-1SMC-H-A N N N @@ -83,7 +86,7 @@ This section details PCIe form-factor targets, which interface with a separate h VCU108 Y Y :sup:`5` Y VCU118 Y Y :sup:`5` Y VCU1525 Y Y :sup:`5` Y - ZCU106 Y Y :sup:`5` Y + ZCU106 Y Y :sup:`5` N :sup:`9` ======================= ============ ============ ========== - :sup:`1` I2C access to optical modules @@ -94,6 +97,7 @@ This section details PCIe form-factor targets, which interface with a separate h - :sup:`6` MAC available from BMC, but accessing BMC is not yet implemented - :sup:`7` No on-board EEPROM - :sup:`8` Flash sits behind CPLD, not currently exposed via PCIe +- :sup:`9` Flash sits behind Zynq SoC, not currently exposed via PCIe .. table:: Summary of the board-specific design variants and some important configuration parameters. @@ -118,6 +122,9 @@ This section details PCIe form-factor targets, which interface with a separate h fb2CG\@KU15P mqnic/fpga_100g/fpga 2x1 256/8K 100G RR fb2CG\@KU15P mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA NetFPGA SUME mqnic/fpga/fpga 1x1 256/512 10G RR + 250-SoC mqnic/fpga_25g/fpga 2x1 256/8K 25G RR + 250-SoC mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR + 250-SoC mqnic/fpga_100g/fpga 2x1 256/8K 100G RR XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G RR XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G RR XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR diff --git a/docs/source/index.rst b/docs/source/index.rst index 9da78829a..d0360ccb3 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -21,6 +21,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s * Cisco Nexus K3P-Q (Xilinx Kintex UltraScale+ XCKU3P) * Silicom fb2CG\@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * NetFPGA SUME (Xilinx Virtex 7 XC7V690T) +* BittWare 250-SoC (Xilinx Zynq UltraScale+ XCZU19EG) * BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P) * Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) diff --git a/docs/source/modules/mqnic_core.rst b/docs/source/modules/mqnic_core.rst index 0d5358a34..16963297b 100644 --- a/docs/source/modules/mqnic_core.rst +++ b/docs/source/modules/mqnic_core.rst @@ -696,6 +696,7 @@ Ports ptp_rst in 1 PTP reset ptp_sample_clk in 1 PTP sample clock ptp_pps out 1 PTP pulse-per-second (synchronous to ptp_clk) + ptp_pps_str out 1 PTP pulse-per-second (stretched) (synchronous to ptp_clk) ptp_ts_96 out PTP_TS_WIDTH current PTP time (synchronous to ptp_clk) ptp_ts_step out 1 PTP clock step (synchronous to ptp_clk) ptp_sync_pps out 1 PTP pulse-per-second (synchronous to clk)