diff --git a/tb/pcie_msix/Makefile b/tb/pcie_msix/Makefile
index d94fab9c5..f3b4d1d86 100644
--- a/tb/pcie_msix/Makefile
+++ b/tb/pcie_msix/Makefile
@@ -36,10 +36,7 @@ export PARAM_IRQ_INDEX_WIDTH := 11
 export PARAM_AXIL_DATA_WIDTH := 32
 export PARAM_AXIL_ADDR_WIDTH := $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 )
 export PARAM_AXIL_STRB_WIDTH := $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
-export PARAM_TLP_DATA_WIDTH := 64
-export PARAM_TLP_STRB_WIDTH := $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
 export PARAM_TLP_HDR_WIDTH := 128
-export PARAM_TLP_SEG_COUNT := 1
 export PARAM_TLP_FORCE_64_BIT_ADDR := 0
 
 ifeq ($(SIM), icarus)
diff --git a/tb/pcie_msix/test_pcie_msix.py b/tb/pcie_msix/test_pcie_msix.py
index c1c054e28..2115dec60 100644
--- a/tb/pcie_msix/test_pcie_msix.py
+++ b/tb/pcie_msix/test_pcie_msix.py
@@ -319,8 +319,7 @@ rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
 
 
 @pytest.mark.parametrize("axil_data_width", [32, 64])
-@pytest.mark.parametrize("pcie_data_width", [64, 128])
-def test_pcie_msix(request, pcie_data_width, axil_data_width):
+def test_pcie_msix(request, axil_data_width):
     dut = "pcie_msix"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -335,10 +334,7 @@ def test_pcie_msix(request, pcie_data_width, axil_data_width):
     parameters['AXIL_DATA_WIDTH'] = axil_data_width
     parameters['AXIL_ADDR_WIDTH'] = parameters['IRQ_INDEX_WIDTH']+5
     parameters['AXIL_STRB_WIDTH'] = (axil_data_width // 8)
-    parameters['TLP_DATA_WIDTH'] = pcie_data_width
-    parameters['TLP_STRB_WIDTH'] = pcie_data_width // 32
     parameters['TLP_HDR_WIDTH'] = 128
-    parameters['TLP_SEG_COUNT'] = 1
     parameters['TLP_FORCE_64_BIT_ADDR'] = 0
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}