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https://github.com/corundum/corundum.git
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Add a simple block transfer measurement
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
9b74e02408
commit
87e155949c
@ -51,6 +51,150 @@ static const struct pci_device_id pci_ids[] = {
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static void dma_block_read(struct example_dev *edev,
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dma_addr_t dma_addr, size_t dma_offset,
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size_t dma_offset_mask, size_t dma_stride,
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size_t ram_addr, size_t ram_offset,
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size_t ram_offset_mask, size_t ram_stride,
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size_t block_len, size_t block_count)
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{
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unsigned long t;
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// DMA base address
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iowrite32(dma_addr & 0xffffffff, edev->bar[0] + 0x001080);
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iowrite32((dma_addr >> 32) & 0xffffffff, edev->bar[0] + 0x001084);
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// DMA offset address
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iowrite32(dma_offset & 0xffffffff, edev->bar[0] + 0x001088);
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iowrite32((dma_offset >> 32) & 0xffffffff, edev->bar[0] + 0x00108c);
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// DMA offset mask
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iowrite32(dma_offset_mask & 0xffffffff, edev->bar[0] + 0x001090);
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iowrite32((dma_offset_mask >> 32) & 0xffffffff, edev->bar[0] + 0x001094);
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// DMA stride
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iowrite32(dma_stride & 0xffffffff, edev->bar[0] + 0x001098);
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iowrite32((dma_stride >> 32) & 0xffffffff, edev->bar[0] + 0x00109c);
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// RAM base address
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iowrite32(ram_addr & 0xffffffff, edev->bar[0] + 0x0010c0);
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iowrite32((ram_addr >> 32) & 0xffffffff, edev->bar[0] + 0x0010c4);
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// RAM offset address
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iowrite32(ram_offset & 0xffffffff, edev->bar[0] + 0x0010c8);
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iowrite32((ram_offset >> 32) & 0xffffffff, edev->bar[0] + 0x0010cc);
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// RAM offset mask
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iowrite32(ram_offset_mask & 0xffffffff, edev->bar[0] + 0x0010d0);
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iowrite32((ram_offset_mask >> 32) & 0xffffffff, edev->bar[0] + 0x0010d4);
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// RAM stride
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iowrite32(ram_stride & 0xffffffff, edev->bar[0] + 0x0010d8);
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iowrite32((ram_stride >> 32) & 0xffffffff, edev->bar[0] + 0x0010dc);
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// clear cycle count
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iowrite32(0, edev->bar[0] + 0x001008);
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iowrite32(0, edev->bar[0] + 0x00100c);
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// block length
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iowrite32(block_len, edev->bar[0] + 0x001010);
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// block count
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iowrite32(block_count, edev->bar[0] + 0x001018);
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// start
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iowrite32(1, edev->bar[0] + 0x001000);
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// wait for transfer to complete
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t = jiffies + msecs_to_jiffies(20000);
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while (time_before(jiffies, t)) {
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if ((ioread32(edev->bar[0] + 0x001000) & 1) == 0)
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break;
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}
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if ((ioread32(edev->bar[0] + 0x001000) & 1) != 0)
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dev_warn(edev->dev, "%s: operation timed out", __func__);
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}
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static void dma_block_write(struct example_dev *edev,
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dma_addr_t dma_addr, size_t dma_offset,
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size_t dma_offset_mask, size_t dma_stride,
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size_t ram_addr, size_t ram_offset,
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size_t ram_offset_mask, size_t ram_stride,
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size_t block_len, size_t block_count)
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{
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unsigned long t;
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// DMA base address
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iowrite32(dma_addr & 0xffffffff, edev->bar[0] + 0x001180);
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iowrite32((dma_addr >> 32) & 0xffffffff, edev->bar[0] + 0x001184);
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// DMA offset address
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iowrite32(dma_offset & 0xffffffff, edev->bar[0] + 0x001188);
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iowrite32((dma_offset >> 32) & 0xffffffff, edev->bar[0] + 0x00118c);
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// DMA offset mask
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iowrite32(dma_offset_mask & 0xffffffff, edev->bar[0] + 0x001190);
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iowrite32((dma_offset_mask >> 32) & 0xffffffff, edev->bar[0] + 0x001194);
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// DMA stride
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iowrite32(dma_stride & 0xffffffff, edev->bar[0] + 0x001198);
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iowrite32((dma_stride >> 32) & 0xffffffff, edev->bar[0] + 0x00119c);
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// RAM base address
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iowrite32(ram_addr & 0xffffffff, edev->bar[0] + 0x0011c0);
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iowrite32((ram_addr >> 32) & 0xffffffff, edev->bar[0] + 0x0011c4);
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// RAM offset address
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iowrite32(ram_offset & 0xffffffff, edev->bar[0] + 0x0011c8);
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iowrite32((ram_offset >> 32) & 0xffffffff, edev->bar[0] + 0x0011cc);
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// RAM offset mask
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iowrite32(ram_offset_mask & 0xffffffff, edev->bar[0] + 0x0011d0);
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iowrite32((ram_offset_mask >> 32) & 0xffffffff, edev->bar[0] + 0x0011d4);
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// RAM stride
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iowrite32(ram_stride & 0xffffffff, edev->bar[0] + 0x0011d8);
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iowrite32((ram_stride >> 32) & 0xffffffff, edev->bar[0] + 0x0011dc);
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// clear cycle count
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iowrite32(0, edev->bar[0] + 0x001108);
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iowrite32(0, edev->bar[0] + 0x00110c);
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// block length
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iowrite32(block_len, edev->bar[0] + 0x001110);
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// block count
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iowrite32(block_count, edev->bar[0] + 0x001118);
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// start
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iowrite32(1, edev->bar[0] + 0x001100);
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// wait for transfer to complete
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t = jiffies + msecs_to_jiffies(20000);
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while (time_before(jiffies, t)) {
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if ((ioread32(edev->bar[0] + 0x001100) & 1) == 0)
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break;
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}
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if ((ioread32(edev->bar[0] + 0x001100) & 1) != 0)
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dev_warn(edev->dev, "%s: operation timed out", __func__);
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}
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static void dma_block_read_bench(struct example_dev *edev,
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dma_addr_t dma_addr, u64 size, u64 stride, u64 count)
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{
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u64 cycles;
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udelay(5);
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dma_block_read(edev, dma_addr, 0, 0x3fff, stride,
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0, 0, 0x3fff, stride, size, count);
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cycles = ioread32(edev->bar[0] + 0x001008);
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udelay(5);
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dev_info(edev->dev, "read %lld blocks of %lld bytes (stride %lld) in %lld ns: %lld Mbps",
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count, size, stride, cycles * 4, size * count * 8 * 1000 / (cycles * 4));
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}
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static void dma_block_write_bench(struct example_dev *edev,
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dma_addr_t dma_addr, u64 size, u64 stride, u64 count)
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{
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u64 cycles;
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udelay(5);
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dma_block_write(edev, dma_addr, 0, 0x3fff, stride,
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0, 0, 0x3fff, stride, size, count);
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cycles = ioread32(edev->bar[0] + 0x001108);
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udelay(5);
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dev_info(edev->dev, "wrote %lld blocks of %lld bytes (stride %lld) in %lld ns: %lld Mbps",
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count, size, stride, cycles * 4, size * count * 8 * 1000 / (cycles * 4));
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}
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static irqreturn_t edev_intr(int irq, void *data)
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{
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struct example_dev *edev = data;
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@ -70,6 +214,7 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct device *dev = &pdev->dev;
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int k;
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int mismatch = 0;
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dev_info(dev, DRIVER_NAME " probe");
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dev_info(dev, " Vendor: 0x%04x", pdev->vendor);
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@ -117,6 +262,7 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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return -ENOMEM;
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edev->pdev = pdev;
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edev->dev = dev;
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pci_set_drvdata(pdev, edev);
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// Allocate DMA buffer
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@ -234,6 +380,13 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
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edev->dma_region + 0x0200, 256, true);
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if (memcmp(edev->dma_region + 0x0000, edev->dma_region + 0x0200, 256) == 0) {
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dev_info(dev, "test data matches");
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} else {
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dev_warn(dev, "test data mismatch");
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mismatch = 1;
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}
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dev_info(dev, "start immediate write to host");
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iowrite32((edev->dma_region_addr + 0x0200) & 0xffffffff, edev->bar[0] + 0x000200);
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iowrite32(((edev->dma_region_addr + 0x0200) >> 32) & 0xffffffff, edev->bar[0] + 0x000204);
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@ -251,6 +404,34 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
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edev->dma_region + 0x0200, 4, true);
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if (!mismatch) {
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u64 size;
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u64 stride;
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dev_info(dev, "disable interrupts");
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iowrite32(0x0, edev->bar[0] + 0x000008);
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dev_info(dev, "perform block reads (dma_alloc_coherent)");
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for (size = 1; size <= 8192; size *= 2) {
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for (stride = size; stride <= max(size, 256llu); stride *= 2) {
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dma_block_read_bench(edev,
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edev->dma_region_addr + 0x0000,
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size, stride, 10000);
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}
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}
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dev_info(dev, "perform block writes (dma_alloc_coherent)");
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for (size = 1; size <= 8192; size *= 2) {
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for (stride = size; stride <= max(size, 256llu); stride *= 2) {
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dma_block_write_bench(edev,
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edev->dma_region_addr + 0x0000,
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size, stride, 10000);
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}
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}
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}
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// probe complete
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return 0;
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@ -31,6 +31,7 @@
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struct example_dev {
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struct pci_dev *pdev;
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struct device *dev;
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// BAR pointers
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void __iomem *bar[6];
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