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Rework header ready set

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This commit is contained in:
Alex Forencich 2014-11-17 19:27:45 -08:00
parent 59952bd8cf
commit 885d847514
4 changed files with 40 additions and 40 deletions
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12
rtl/eth_mux.py
View File

@ -235,6 +235,13 @@ always @* begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
case (select_next)
{%- for p in ports %}
{{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1;
{%- endfor %}
endcase
output_eth_hdr_valid_next = 1;
output_eth_dest_mac_next = selected_input_eth_dest_mac;
output_eth_src_mac_next = selected_input_eth_src_mac;
@ -244,10 +251,7 @@ always @* begin
// generate ready signal on selected port
case (select_next)
{%- for p in ports %}
{{w}}'d{{p}}: begin
input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
{{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
{%- endfor %}
endcase

28
rtl/eth_mux_4.v
View File

@ -244,6 +244,14 @@ always @* begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
case (select_next)
2'd0: input_0_eth_hdr_ready_next = 1;
2'd1: input_1_eth_hdr_ready_next = 1;
2'd2: input_2_eth_hdr_ready_next = 1;
2'd3: input_3_eth_hdr_ready_next = 1;
endcase
output_eth_hdr_valid_next = 1;
output_eth_dest_mac_next = selected_input_eth_dest_mac;
output_eth_src_mac_next = selected_input_eth_src_mac;
@ -252,22 +260,10 @@ always @* begin
// generate ready signal on selected port
case (select_next)
2'd0: begin
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd1: begin
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd2: begin
input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd3: begin
input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
endcase
// pass through selected packet data

12
rtl/eth_mux_64.py
View File

@ -240,6 +240,13 @@ always @* begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
case (select_next)
{%- for p in ports %}
{{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1;
{%- endfor %}
endcase
output_eth_hdr_valid_next = 1;
output_eth_dest_mac_next = selected_input_eth_dest_mac;
output_eth_src_mac_next = selected_input_eth_src_mac;
@ -249,10 +256,7 @@ always @* begin
// generate ready signal on selected port
case (select_next)
{%- for p in ports %}
{{w}}'d{{p}}: begin
input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
{{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
{%- endfor %}
endcase

28
rtl/eth_mux_64_4.v
View File

@ -255,6 +255,14 @@ always @* begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
case (select_next)
2'd0: input_0_eth_hdr_ready_next = 1;
2'd1: input_1_eth_hdr_ready_next = 1;
2'd2: input_2_eth_hdr_ready_next = 1;
2'd3: input_3_eth_hdr_ready_next = 1;
endcase
output_eth_hdr_valid_next = 1;
output_eth_dest_mac_next = selected_input_eth_dest_mac;
output_eth_src_mac_next = selected_input_eth_src_mac;
@ -263,22 +271,10 @@ always @* begin
// generate ready signal on selected port
case (select_next)
2'd0: begin
input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd1: begin
input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd2: begin
input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd3: begin
input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg);
input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
end
2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next;
endcase
// pass through selected packet data