From 885d847514f4a8b8138d934e41ed4450628a433a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 17 Nov 2014 19:27:45 -0800 Subject: [PATCH] Rework header ready set --- rtl/eth_mux.py | 12 ++++++++---- rtl/eth_mux_4.v | 28 ++++++++++++---------------- rtl/eth_mux_64.py | 12 ++++++++---- rtl/eth_mux_64_4.v | 28 ++++++++++++---------------- 4 files changed, 40 insertions(+), 40 deletions(-) diff --git a/rtl/eth_mux.py b/rtl/eth_mux.py index d0d5cd22c..088e821d5 100755 --- a/rtl/eth_mux.py +++ b/rtl/eth_mux.py @@ -235,6 +235,13 @@ always @* begin // start of frame, grab select value frame_next = 1; select_next = select; + + case (select_next) +{%- for p in ports %} + {{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1; +{%- endfor %} + endcase + output_eth_hdr_valid_next = 1; output_eth_dest_mac_next = selected_input_eth_dest_mac; output_eth_src_mac_next = selected_input_eth_src_mac; @@ -244,10 +251,7 @@ always @* begin // generate ready signal on selected port case (select_next) {%- for p in ports %} - {{w}}'d{{p}}: begin - input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end + {{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; {%- endfor %} endcase diff --git a/rtl/eth_mux_4.v b/rtl/eth_mux_4.v index b7071462b..7d5633bf3 100644 --- a/rtl/eth_mux_4.v +++ b/rtl/eth_mux_4.v @@ -244,6 +244,14 @@ always @* begin // start of frame, grab select value frame_next = 1; select_next = select; + + case (select_next) + 2'd0: input_0_eth_hdr_ready_next = 1; + 2'd1: input_1_eth_hdr_ready_next = 1; + 2'd2: input_2_eth_hdr_ready_next = 1; + 2'd3: input_3_eth_hdr_ready_next = 1; + endcase + output_eth_hdr_valid_next = 1; output_eth_dest_mac_next = selected_input_eth_dest_mac; output_eth_src_mac_next = selected_input_eth_src_mac; @@ -252,22 +260,10 @@ always @* begin // generate ready signal on selected port case (select_next) - 2'd0: begin - input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd1: begin - input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd2: begin - input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd3: begin - input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end + 2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; endcase // pass through selected packet data diff --git a/rtl/eth_mux_64.py b/rtl/eth_mux_64.py index 4a3250d6a..8e7fadda4 100755 --- a/rtl/eth_mux_64.py +++ b/rtl/eth_mux_64.py @@ -240,6 +240,13 @@ always @* begin // start of frame, grab select value frame_next = 1; select_next = select; + + case (select_next) +{%- for p in ports %} + {{w}}'d{{p}}: input_{{p}}_eth_hdr_ready_next = 1; +{%- endfor %} + endcase + output_eth_hdr_valid_next = 1; output_eth_dest_mac_next = selected_input_eth_dest_mac; output_eth_src_mac_next = selected_input_eth_src_mac; @@ -249,10 +256,7 @@ always @* begin // generate ready signal on selected port case (select_next) {%- for p in ports %} - {{w}}'d{{p}}: begin - input_{{p}}_eth_hdr_ready_next = input_{{p}}_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end + {{w}}'d{{p}}: input_{{p}}_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; {%- endfor %} endcase diff --git a/rtl/eth_mux_64_4.v b/rtl/eth_mux_64_4.v index cd80138e3..085eb5db3 100644 --- a/rtl/eth_mux_64_4.v +++ b/rtl/eth_mux_64_4.v @@ -255,6 +255,14 @@ always @* begin // start of frame, grab select value frame_next = 1; select_next = select; + + case (select_next) + 2'd0: input_0_eth_hdr_ready_next = 1; + 2'd1: input_1_eth_hdr_ready_next = 1; + 2'd2: input_2_eth_hdr_ready_next = 1; + 2'd3: input_3_eth_hdr_ready_next = 1; + endcase + output_eth_hdr_valid_next = 1; output_eth_dest_mac_next = selected_input_eth_dest_mac; output_eth_src_mac_next = selected_input_eth_src_mac; @@ -263,22 +271,10 @@ always @* begin // generate ready signal on selected port case (select_next) - 2'd0: begin - input_0_eth_hdr_ready_next = input_0_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd1: begin - input_1_eth_hdr_ready_next = input_1_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd2: begin - input_2_eth_hdr_ready_next = input_2_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end - 2'd3: begin - input_3_eth_hdr_ready_next = input_3_eth_hdr_ready_next | (frame_next & ~frame_reg); - input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; - end + 2'd0: input_0_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd1: input_1_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd2: input_2_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; + 2'd3: input_3_eth_payload_tready_next = output_eth_payload_tready_int_early & frame_next; endcase // pass through selected packet data