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Add test for PCIe spread spectrum clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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@ -421,6 +421,40 @@ async def run_test(dut):
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assert abs(mean(rel_diffs)) < 5
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assert abs(mean(tod_diffs)) < 5
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await RisingEdge(dut.clk)
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tb.log.info("Coherent tracking (250 MHz +0/-0.5%)")
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tb.set_ptp_clock_period(6.4)
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tb.set_clock_period(4.0)
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await RisingEdge(dut.clk)
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period = 4.000
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step = 0.0002
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period_min = 4.0
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period_max = 4.0*(1+0.005)
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for i in range(5000):
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period += step
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if period <= period_min:
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step = abs(step)
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if period >= period_max:
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step = -abs(step)
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tb.set_clock_period(period)
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for i in range(20):
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await RisingEdge(dut.clk)
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assert tb.dut.locked.value.integer
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rel_diffs, tod_diffs = await tb.measure_ts_diff()
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tb.log.info(f"Difference (rel): {mean(rel_diffs)} ns (stdev: {stdev(rel_diffs)})")
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tb.log.info(f"Difference (ToD): {mean(tod_diffs)} ns (stdev: {stdev(tod_diffs)})")
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assert abs(mean(rel_diffs)) < 5
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assert abs(mean(tod_diffs)) < 5
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await RisingEdge(dut.clk)
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tb.log.info("Significantly slower (100 MHz)")
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