From 8a261b1307f2cb31739fed81c4d1ef64f5b8a134 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 10 Jun 2023 20:21:56 -0700 Subject: [PATCH] fpga/mqnic/ADM_PCIE_9V3: Add virtual I2C switch to control modsel pins Signed-off-by: Alex Forencich --- .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 1 + .../fpga_100g/fpga_app_dma_bench/Makefile | 1 + .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile | 1 + .../ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 63 ++++++++++++------- .../fpga_100g/tb/fpga_core/Makefile | 1 + .../fpga_100g/tb/fpga_core/test_fpga_core.py | 1 + .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile | 1 + .../ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 63 ++++++++++++------- .../fpga_25g/tb/fpga_core/Makefile | 1 + .../fpga_25g/tb/fpga_core/test_fpga_core.py | 1 + 12 files changed, 94 insertions(+), 42 deletions(-) diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index cfad96dae..0288763a7 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -57,6 +57,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/ptp_clock.v SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v SYN_FILES += lib/eth/rtl/ptp_perout.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile index 73ed342ff..ab393049c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile @@ -57,6 +57,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index da8487941..72ee0c76c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -59,6 +59,7 @@ SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/ptp_clock.v SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v SYN_FILES += lib/eth/rtl/ptp_perout.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index acb25b00c..f222ca42e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -517,8 +517,12 @@ reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; -reg qsfp_0_sel_reg = 1'b0; -reg qsfp_1_sel_reg = 1'b0; +wire qsfp_i2c_select_scl_o; +wire qsfp_i2c_select_sda_o; +wire [7:0] qsfp_i2c_select; + +wire qsfp_i2c_scl_i_int = qsfp_i2c_scl_i & qsfp_i2c_scl_o; +wire qsfp_i2c_sda_i_int = qsfp_i2c_sda_i & qsfp_i2c_sda_o; reg qsfp_reset_reg = 1'b0; @@ -544,20 +548,20 @@ assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1 assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait; assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack; -assign qsfp_0_sel_l = !qsfp_0_sel_reg; -assign qsfp_1_sel_l = !qsfp_1_sel_reg; +assign qsfp_0_sel_l = !qsfp_i2c_select[0]; +assign qsfp_1_sel_l = !qsfp_i2c_select[1]; assign qsfp_reset_l = !qsfp_reset_reg; -assign qsfp_i2c_scl_o = qsfp_i2c_scl_o_reg; -assign qsfp_i2c_scl_t = qsfp_i2c_scl_o_reg; -assign qsfp_i2c_sda_o = qsfp_i2c_sda_o_reg; -assign qsfp_i2c_sda_t = qsfp_i2c_sda_o_reg; +assign qsfp_i2c_scl_o = qsfp_i2c_scl_o_reg & qsfp_i2c_select_scl_o; +assign qsfp_i2c_scl_t = qsfp_i2c_scl_o; +assign qsfp_i2c_sda_o = qsfp_i2c_sda_o_reg & qsfp_i2c_select_sda_o; +assign qsfp_i2c_sda_t = qsfp_i2c_sda_o; assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg; +assign eeprom_i2c_scl_t = eeprom_i2c_scl_o; assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg; -assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg; +assign eeprom_i2c_sda_t = eeprom_i2c_sda_o; assign eeprom_wp = 1'b0; assign fpga_boot = fpga_boot_reg; @@ -570,6 +574,32 @@ assign qspi_1_cs = qspi_1_cs_reg; assign qspi_1_dq_o = qspi_1_dq_o_reg; assign qspi_1_dq_oe = qspi_1_dq_oe_reg; +i2c_single_reg #( + .FILTER_LEN(4), + .DEV_ADDR(7'h74) +) +qsfp_i2c_select_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * I2C interface + */ + .scl_i(qsfp_i2c_scl_i_int), + .scl_o(qsfp_i2c_select_scl_o), + .scl_t(), + .sda_i(qsfp_i2c_sda_i_int), + .sda_o(qsfp_i2c_select_sda_o), + .sda_t(), + + /* + * Data register + */ + .data_in(8'd0), + .data_latch(1'b0), + .data_out(qsfp_i2c_select) +); + always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; @@ -593,10 +623,6 @@ always @(posedge clk_250mhz) begin if (ctrl_reg_wr_strb[1]) begin qsfp_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; end - if (ctrl_reg_wr_strb[2]) begin - qsfp_0_sel_reg <= ctrl_reg_wr_data[16]; - qsfp_1_sel_reg <= ctrl_reg_wr_data[17]; - end end // I2C 1 RBB+8'h1C: begin @@ -663,12 +689,10 @@ always @(posedge clk_250mhz) begin RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header RBB+8'h0C: begin // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp_i2c_scl_i; + ctrl_reg_rd_data_reg[0] <= qsfp_i2c_scl_i_int; ctrl_reg_rd_data_reg[1] <= qsfp_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp_i2c_sda_i; + ctrl_reg_rd_data_reg[8] <= qsfp_i2c_sda_i_int; ctrl_reg_rd_data_reg[9] <= qsfp_i2c_sda_o_reg; - ctrl_reg_rd_data_reg[16] <= qsfp_0_sel_reg; - ctrl_reg_rd_data_reg[17] <= qsfp_1_sel_reg; end // I2C 1 RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type @@ -727,9 +751,6 @@ always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0; - qsfp_0_sel_reg <= 1'b0; - qsfp_1_sel_reg <= 1'b0; - qsfp_reset_reg <= 1'b0; qsfp_i2c_scl_o_reg <= 1'b1; diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 6974d970c..0bcd42f96 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -83,6 +83,7 @@ VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 6ddca1add..60c085549 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -675,6 +675,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "stats_dma_latency.v"), os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "common", "i2c_single_reg.v"), os.path.join(eth_rtl_dir, "ptp_clock.v"), os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), os.path.join(eth_rtl_dir, "ptp_perout.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index 820cca85a..e84aeb243 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -58,6 +58,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index 820cca85a..e84aeb243 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -58,6 +58,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 1206fdcb0..0972b2e6a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -60,6 +60,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += rtl/common/i2c_single_reg.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v SYN_FILES += lib/eth/rtl/eth_phy_10g.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 56c183a81..54b37ed1a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -585,8 +585,12 @@ reg ctrl_reg_wr_ack_reg = 1'b0; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg ctrl_reg_rd_ack_reg = 1'b0; -reg qsfp_0_sel_reg = 1'b0; -reg qsfp_1_sel_reg = 1'b0; +wire qsfp_i2c_select_scl_o; +wire qsfp_i2c_select_sda_o; +wire [7:0] qsfp_i2c_select; + +wire qsfp_i2c_scl_i_int = qsfp_i2c_scl_i & qsfp_i2c_scl_o; +wire qsfp_i2c_sda_i_int = qsfp_i2c_sda_i & qsfp_i2c_sda_o; reg qsfp_reset_reg = 1'b0; @@ -612,20 +616,20 @@ assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1 assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait; assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack; -assign qsfp_0_sel_l = !qsfp_0_sel_reg; -assign qsfp_1_sel_l = !qsfp_1_sel_reg; +assign qsfp_0_sel_l = !qsfp_i2c_select[0]; +assign qsfp_1_sel_l = !qsfp_i2c_select[1]; assign qsfp_reset_l = !qsfp_reset_reg; -assign qsfp_i2c_scl_o = qsfp_i2c_scl_o_reg; -assign qsfp_i2c_scl_t = qsfp_i2c_scl_o_reg; -assign qsfp_i2c_sda_o = qsfp_i2c_sda_o_reg; -assign qsfp_i2c_sda_t = qsfp_i2c_sda_o_reg; +assign qsfp_i2c_scl_o = qsfp_i2c_scl_o_reg & qsfp_i2c_select_scl_o; +assign qsfp_i2c_scl_t = qsfp_i2c_scl_o; +assign qsfp_i2c_sda_o = qsfp_i2c_sda_o_reg & qsfp_i2c_select_sda_o; +assign qsfp_i2c_sda_t = qsfp_i2c_sda_o; assign eeprom_i2c_scl_o = eeprom_i2c_scl_o_reg; -assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg; +assign eeprom_i2c_scl_t = eeprom_i2c_scl_o; assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg; -assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg; +assign eeprom_i2c_sda_t = eeprom_i2c_sda_o; assign eeprom_wp = 1'b0; assign fpga_boot = fpga_boot_reg; @@ -638,6 +642,32 @@ assign qspi_1_cs = qspi_1_cs_reg; assign qspi_1_dq_o = qspi_1_dq_o_reg; assign qspi_1_dq_oe = qspi_1_dq_oe_reg; +i2c_single_reg #( + .FILTER_LEN(4), + .DEV_ADDR(7'h74) +) +qsfp_i2c_select_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * I2C interface + */ + .scl_i(qsfp_i2c_scl_i_int), + .scl_o(qsfp_i2c_select_scl_o), + .scl_t(), + .sda_i(qsfp_i2c_sda_i_int), + .sda_o(qsfp_i2c_select_sda_o), + .sda_t(), + + /* + * Data register + */ + .data_in(8'd0), + .data_latch(1'b0), + .data_out(qsfp_i2c_select) +); + always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; @@ -661,10 +691,6 @@ always @(posedge clk_250mhz) begin if (ctrl_reg_wr_strb[1]) begin qsfp_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; end - if (ctrl_reg_wr_strb[2]) begin - qsfp_0_sel_reg <= ctrl_reg_wr_data[16]; - qsfp_1_sel_reg <= ctrl_reg_wr_data[17]; - end end // I2C 1 RBB+8'h1C: begin @@ -731,12 +757,10 @@ always @(posedge clk_250mhz) begin RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header RBB+8'h0C: begin // I2C ctrl: control - ctrl_reg_rd_data_reg[0] <= qsfp_i2c_scl_i; + ctrl_reg_rd_data_reg[0] <= qsfp_i2c_scl_i_int; ctrl_reg_rd_data_reg[1] <= qsfp_i2c_scl_o_reg; - ctrl_reg_rd_data_reg[8] <= qsfp_i2c_sda_i; + ctrl_reg_rd_data_reg[8] <= qsfp_i2c_sda_i_int; ctrl_reg_rd_data_reg[9] <= qsfp_i2c_sda_o_reg; - ctrl_reg_rd_data_reg[16] <= qsfp_0_sel_reg; - ctrl_reg_rd_data_reg[17] <= qsfp_1_sel_reg; end // I2C 1 RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type @@ -795,9 +819,6 @@ always @(posedge clk_250mhz) begin ctrl_reg_wr_ack_reg <= 1'b0; ctrl_reg_rd_ack_reg <= 1'b0; - qsfp_0_sel_reg <= 1'b0; - qsfp_1_sel_reg <= 1'b0; - qsfp_reset_reg <= 1'b0; qsfp_i2c_scl_o_reg <= 1'b1; diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 714a31fb8..7535eade6 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -86,6 +86,7 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v VERILOG_SOURCES += ../../rtl/common/tdma_ber.v VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v +VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index cb5bc6439..3a0c34225 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -726,6 +726,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "tdma_scheduler.v"), os.path.join(rtl_dir, "common", "tdma_ber.v"), os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), + os.path.join(rtl_dir, "common", "i2c_single_reg.v"), os.path.join(eth_rtl_dir, "eth_mac_10g.v"), os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),