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Add MTU registers

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This commit is contained in:
Alex Forencich 2020-05-01 18:55:01 -07:00
parent ca0cbf4d93
commit 8b535e54ac
3 changed files with 15 additions and 0 deletions
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9
fpga/common/rtl/port.v
View File

@ -569,6 +569,9 @@ reg sched_enable_reg = 1'b0;
reg [RX_QUEUE_INDEX_WIDTH-1:0] rss_mask_reg = 0;
reg [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu_reg = MAX_TX_SIZE;
reg [DMA_CLIENT_LEN_WIDTH-1:0] rx_mtu_reg = MAX_RX_SIZE;
reg tdma_enable_reg = 1'b0;
wire tdma_locked;
wire tdma_error;
@ -623,6 +626,8 @@ always @(posedge clk) begin
end
end
16'h0080: rss_mask_reg <= axil_ctrl_wdata; // RSS mask
16'h0100: tx_mtu_reg <= axil_ctrl_wdata; // TX MTU
16'h0200: rx_mtu_reg <= axil_ctrl_wdata; // RX MTU
16'h1000: begin
// TDMA control
if (axil_ctrl_wstrb[0]) begin
@ -686,6 +691,8 @@ always @(posedge clk) begin
axil_ctrl_rdata_reg[0] <= sched_enable_reg;
end
16'h0080: axil_ctrl_rdata_reg <= rss_mask_reg; // RSS mask
16'h0100: axil_ctrl_rdata_reg <= tx_mtu_reg; // TX MTU
16'h0200: axil_ctrl_rdata_reg <= rx_mtu_reg; // RX MTU
16'h1000: begin
// TDMA control
axil_ctrl_rdata_reg[0] <= tdma_enable_reg;
@ -720,6 +727,8 @@ always @(posedge clk) begin
sched_enable_reg <= 1'b0;
rss_mask_reg <= 0;
tx_mtu_reg <= MAX_TX_SIZE;
rx_mtu_reg <= MAX_RX_SIZE;
tdma_enable_reg <= 1'b0;
end
end

3
fpga/common/tb/mqnic.py
View File

@ -136,6 +136,9 @@ MQNIC_PORT_REG_SCHED_STRIDE = 0x0018
MQNIC_PORT_REG_SCHED_TYPE = 0x001C
MQNIC_PORT_REG_SCHED_ENABLE = 0x0040
MQNIC_PORT_REG_TX_MTU = 0x0100
MQNIC_PORT_REG_RX_MTU = 0x0200
MQNIC_PORT_REG_TDMA_CTRL = 0x1000
MQNIC_PORT_REG_TDMA_STATUS = 0x1004
MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT = 0x1008

3
modules/mqnic/mqnic_hw.h
View File

@ -152,6 +152,9 @@ either expressed or implied, of The Regents of the University of California.
#define MQNIC_PORT_REG_RSS_MASK 0x0080
#define MQNIC_PORT_REG_TX_MTU 0x0100
#define MQNIC_PORT_REG_RX_MTU 0x0200
#define MQNIC_PORT_REG_TDMA_CTRL 0x1000
#define MQNIC_PORT_REG_TDMA_STATUS 0x1004
#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x1008