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Add IPROG for ExaNIC X10

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This commit is contained in:
Alex Forencich 2020-10-03 15:36:40 -07:00
parent be67f173b6
commit 8dfdf3a717
12 changed files with 274 additions and 0 deletions
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4
fpga/mqnic/ExaNIC_X10/fpga/boot.xdc Normal file
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@ -0,0 +1,4 @@
# Timing constraints for FPGA boot logic
set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]

1
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
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@ -70,6 +70,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl

116
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v
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@ -292,6 +292,121 @@ flash_sync_signal_inst (
.out(flash_dq_i_int)
);
// FPGA boot
wire fpga_boot;
reg fpga_boot_sync_reg_0 = 1'b0;
reg fpga_boot_sync_reg_1 = 1'b0;
reg fpga_boot_sync_reg_2 = 1'b0;
wire icap_avail;
reg [2:0] icap_state = 0;
reg icap_csib_reg = 1'b1;
reg icap_rdwrb_reg = 1'b0;
reg [31:0] icap_di_reg = 32'hffffffff;
wire [31:0] icap_di_rev;
assign icap_di_rev[ 7] = icap_di_reg[ 0];
assign icap_di_rev[ 6] = icap_di_reg[ 1];
assign icap_di_rev[ 5] = icap_di_reg[ 2];
assign icap_di_rev[ 4] = icap_di_reg[ 3];
assign icap_di_rev[ 3] = icap_di_reg[ 4];
assign icap_di_rev[ 2] = icap_di_reg[ 5];
assign icap_di_rev[ 1] = icap_di_reg[ 6];
assign icap_di_rev[ 0] = icap_di_reg[ 7];
assign icap_di_rev[15] = icap_di_reg[ 8];
assign icap_di_rev[14] = icap_di_reg[ 9];
assign icap_di_rev[13] = icap_di_reg[10];
assign icap_di_rev[12] = icap_di_reg[11];
assign icap_di_rev[11] = icap_di_reg[12];
assign icap_di_rev[10] = icap_di_reg[13];
assign icap_di_rev[ 9] = icap_di_reg[14];
assign icap_di_rev[ 8] = icap_di_reg[15];
assign icap_di_rev[23] = icap_di_reg[16];
assign icap_di_rev[22] = icap_di_reg[17];
assign icap_di_rev[21] = icap_di_reg[18];
assign icap_di_rev[20] = icap_di_reg[19];
assign icap_di_rev[19] = icap_di_reg[20];
assign icap_di_rev[18] = icap_di_reg[21];
assign icap_di_rev[17] = icap_di_reg[22];
assign icap_di_rev[16] = icap_di_reg[23];
assign icap_di_rev[31] = icap_di_reg[24];
assign icap_di_rev[30] = icap_di_reg[25];
assign icap_di_rev[29] = icap_di_reg[26];
assign icap_di_rev[28] = icap_di_reg[27];
assign icap_di_rev[27] = icap_di_reg[28];
assign icap_di_rev[26] = icap_di_reg[29];
assign icap_di_rev[25] = icap_di_reg[30];
assign icap_di_rev[24] = icap_di_reg[31];
always @(posedge clk_125mhz_int) begin
case (icap_state)
0: begin
icap_state <= 0;
icap_csib_reg <= 1'b1;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hffffffff; // dummy word
if (fpga_boot_sync_reg_2 && icap_avail) begin
icap_state <= 1;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hffffffff; // dummy word
end
end
1: begin
icap_state <= 2;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hAA995566; // sync word
end
2: begin
icap_state <= 3;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h20000000; // type 1 noop
end
3: begin
icap_state <= 4;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h30008001; // write 1 word to CMD
end
4: begin
icap_state <= 5;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h0000000F; // IPROG
end
5: begin
icap_state <= 0;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h20000000; // type 1 noop
end
endcase
fpga_boot_sync_reg_0 <= fpga_boot;
fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
end
ICAPE3
icape3_inst (
.AVAIL(icap_avail),
.CLK(clk_125mhz_int),
.CSIB(icap_csib_reg),
.I(icap_di_rev),
.O(),
.PRDONE(),
.PRERROR(),
.RDWRB(icap_rdwrb_reg)
);
// PCIe
wire pcie_sys_clk;
wire pcie_sys_clk_gt;
@ -990,6 +1105,7 @@ core_inst (
/*
* BPI flash
*/
.fpga_boot(fpga_boot),
.flash_dq_i(flash_dq_i_int),
.flash_dq_o(flash_dq_o_int),
.flash_dq_oe(flash_dq_oe_int),

11
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
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@ -196,6 +196,7 @@ module fpga_core #
/*
* BPI Flash
*/
output wire fpga_boot,
input wire [15:0] flash_dq_i,
output wire [15:0] flash_dq_o,
output wire flash_dq_oe,
@ -433,6 +434,8 @@ reg sfp_i2c_sda_o_reg = 1'b1;
reg eeprom_i2c_scl_o_reg = 1'b1;
reg eeprom_i2c_sda_o_reg = 1'b1;
reg fpga_boot_reg = 1'b0;
reg [15:0] flash_dq_o_reg = 16'd0;
reg flash_dq_oe_reg = 1'b0;
reg [22:0] flash_addr_reg = 23'd0;
@ -491,6 +494,8 @@ assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg;
assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg;
assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg;
assign fpga_boot = fpga_boot_reg;
assign flash_dq_o = flash_dq_o_reg;
assign flash_dq_oe = flash_dq_oe_reg;
assign flash_addr = flash_addr_reg;
@ -527,6 +532,10 @@ always @(posedge clk_250mhz) begin
axil_csr_bvalid_reg <= 1'b1;
case ({axil_csr_awaddr[15:2], 2'b00})
16'h0040: begin
// FPGA ID
fpga_boot_reg <= axil_csr_wdata == 32'hFEE1DEAD;
end
// GPIO
16'h0110: begin
// GPIO I2C 0
@ -770,6 +779,8 @@ always @(posedge clk_250mhz) begin
eeprom_i2c_scl_o_reg <= 1'b1;
eeprom_i2c_sda_o_reg <= 1'b1;
fpga_boot_reg <= 1'b0;
flash_dq_o_reg <= 16'd0;
flash_dq_oe_reg <= 1'b0;
flash_addr_reg <= 23'd0;

2
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -251,6 +251,7 @@ def bench():
eeprom_i2c_scl_t = Signal(bool(1))
eeprom_i2c_sda_o = Signal(bool(1))
eeprom_i2c_sda_t = Signal(bool(1))
fpga_boot = Signal(bool(0))
flash_dq_o = Signal(intbv(0)[16:])
flash_dq_oe = Signal(bool(0))
flash_addr = Signal(intbv(0)[23:])
@ -594,6 +595,7 @@ def bench():
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
fpga_boot=fpga_boot,
flash_dq_i=flash_dq_i,
flash_dq_o=flash_dq_o,
flash_dq_oe=flash_dq_oe,

3
fpga/mqnic/ExaNIC_X10/fpga/tb/test_fpga_core.v
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@ -165,6 +165,7 @@ wire eeprom_i2c_scl_o;
wire eeprom_i2c_scl_t;
wire eeprom_i2c_sda_o;
wire eeprom_i2c_sda_t;
wire fpga_boot;
wire [15:0] flash_dq_o;
wire flash_dq_oe;
wire [22:0] flash_addr;
@ -289,6 +290,7 @@ initial begin
eeprom_i2c_scl_t,
eeprom_i2c_sda_o,
eeprom_i2c_sda_t,
fpga_boot,
flash_dq_o,
flash_dq_oe,
flash_addr,
@ -423,6 +425,7 @@ UUT (
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
.fpga_boot(fpga_boot),
.flash_dq_i(flash_dq_i),
.flash_dq_o(flash_dq_o),
.flash_dq_oe(flash_dq_oe),

4
fpga/mqnic_tdma/ExaNIC_X10/fpga/boot.xdc Normal file
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@ -0,0 +1,4 @@
# Timing constraints for FPGA boot logic
set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]

1
fpga/mqnic_tdma/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -71,6 +71,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/sync_reset.tcl
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl

116
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v
View File

@ -292,6 +292,121 @@ flash_sync_signal_inst (
.out(flash_dq_i_int)
);
// FPGA boot
wire fpga_boot;
reg fpga_boot_sync_reg_0 = 1'b0;
reg fpga_boot_sync_reg_1 = 1'b0;
reg fpga_boot_sync_reg_2 = 1'b0;
wire icap_avail;
reg [2:0] icap_state = 0;
reg icap_csib_reg = 1'b1;
reg icap_rdwrb_reg = 1'b0;
reg [31:0] icap_di_reg = 32'hffffffff;
wire [31:0] icap_di_rev;
assign icap_di_rev[ 7] = icap_di_reg[ 0];
assign icap_di_rev[ 6] = icap_di_reg[ 1];
assign icap_di_rev[ 5] = icap_di_reg[ 2];
assign icap_di_rev[ 4] = icap_di_reg[ 3];
assign icap_di_rev[ 3] = icap_di_reg[ 4];
assign icap_di_rev[ 2] = icap_di_reg[ 5];
assign icap_di_rev[ 1] = icap_di_reg[ 6];
assign icap_di_rev[ 0] = icap_di_reg[ 7];
assign icap_di_rev[15] = icap_di_reg[ 8];
assign icap_di_rev[14] = icap_di_reg[ 9];
assign icap_di_rev[13] = icap_di_reg[10];
assign icap_di_rev[12] = icap_di_reg[11];
assign icap_di_rev[11] = icap_di_reg[12];
assign icap_di_rev[10] = icap_di_reg[13];
assign icap_di_rev[ 9] = icap_di_reg[14];
assign icap_di_rev[ 8] = icap_di_reg[15];
assign icap_di_rev[23] = icap_di_reg[16];
assign icap_di_rev[22] = icap_di_reg[17];
assign icap_di_rev[21] = icap_di_reg[18];
assign icap_di_rev[20] = icap_di_reg[19];
assign icap_di_rev[19] = icap_di_reg[20];
assign icap_di_rev[18] = icap_di_reg[21];
assign icap_di_rev[17] = icap_di_reg[22];
assign icap_di_rev[16] = icap_di_reg[23];
assign icap_di_rev[31] = icap_di_reg[24];
assign icap_di_rev[30] = icap_di_reg[25];
assign icap_di_rev[29] = icap_di_reg[26];
assign icap_di_rev[28] = icap_di_reg[27];
assign icap_di_rev[27] = icap_di_reg[28];
assign icap_di_rev[26] = icap_di_reg[29];
assign icap_di_rev[25] = icap_di_reg[30];
assign icap_di_rev[24] = icap_di_reg[31];
always @(posedge clk_125mhz_int) begin
case (icap_state)
0: begin
icap_state <= 0;
icap_csib_reg <= 1'b1;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hffffffff; // dummy word
if (fpga_boot_sync_reg_2 && icap_avail) begin
icap_state <= 1;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hffffffff; // dummy word
end
end
1: begin
icap_state <= 2;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'hAA995566; // sync word
end
2: begin
icap_state <= 3;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h20000000; // type 1 noop
end
3: begin
icap_state <= 4;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h30008001; // write 1 word to CMD
end
4: begin
icap_state <= 5;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h0000000F; // IPROG
end
5: begin
icap_state <= 0;
icap_csib_reg <= 1'b0;
icap_rdwrb_reg <= 1'b0;
icap_di_reg <= 32'h20000000; // type 1 noop
end
endcase
fpga_boot_sync_reg_0 <= fpga_boot;
fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
end
ICAPE3
icape3_inst (
.AVAIL(icap_avail),
.CLK(clk_125mhz_int),
.CSIB(icap_csib_reg),
.I(icap_di_rev),
.O(),
.PRDONE(),
.PRERROR(),
.RDWRB(icap_rdwrb_reg)
);
// PCIe
wire pcie_sys_clk;
wire pcie_sys_clk_gt;
@ -990,6 +1105,7 @@ core_inst (
/*
* BPI flash
*/
.fpga_boot(fpga_boot),
.flash_dq_i(flash_dq_i_int),
.flash_dq_o(flash_dq_o_int),
.flash_dq_oe(flash_dq_oe_int),

11
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -196,6 +196,7 @@ module fpga_core #
/*
* BPI Flash
*/
output wire fpga_boot,
input wire [15:0] flash_dq_i,
output wire [15:0] flash_dq_o,
output wire flash_dq_oe,
@ -433,6 +434,8 @@ reg sfp_i2c_sda_o_reg = 1'b1;
reg eeprom_i2c_scl_o_reg = 1'b1;
reg eeprom_i2c_sda_o_reg = 1'b1;
reg fpga_boot_reg = 1'b0;
reg [15:0] flash_dq_o_reg = 16'd0;
reg flash_dq_oe_reg = 1'b0;
reg [22:0] flash_addr_reg = 23'd0;
@ -491,6 +494,8 @@ assign eeprom_i2c_scl_t = eeprom_i2c_scl_o_reg;
assign eeprom_i2c_sda_o = eeprom_i2c_sda_o_reg;
assign eeprom_i2c_sda_t = eeprom_i2c_sda_o_reg;
assign fpga_boot = fpga_boot_reg;
assign flash_dq_o = flash_dq_o_reg;
assign flash_dq_oe = flash_dq_oe_reg;
assign flash_addr = flash_addr_reg;
@ -527,6 +532,10 @@ always @(posedge clk_250mhz) begin
axil_csr_bvalid_reg <= 1'b1;
case ({axil_csr_awaddr[15:2], 2'b00})
16'h0040: begin
// FPGA ID
fpga_boot_reg <= axil_csr_wdata == 32'hFEE1DEAD;
end
// GPIO
16'h0110: begin
// GPIO I2C 0
@ -770,6 +779,8 @@ always @(posedge clk_250mhz) begin
eeprom_i2c_scl_o_reg <= 1'b1;
eeprom_i2c_sda_o_reg <= 1'b1;
fpga_boot_reg <= 1'b0;
flash_dq_o_reg <= 16'd0;
flash_dq_oe_reg <= 1'b0;
flash_addr_reg <= 23'd0;

2
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.py
View File

@ -252,6 +252,7 @@ def bench():
eeprom_i2c_scl_t = Signal(bool(1))
eeprom_i2c_sda_o = Signal(bool(1))
eeprom_i2c_sda_t = Signal(bool(1))
fpga_boot = Signal(bool(0))
flash_dq_o = Signal(intbv(0)[16:])
flash_dq_oe = Signal(bool(0))
flash_addr = Signal(intbv(0)[23:])
@ -595,6 +596,7 @@ def bench():
eeprom_i2c_sda_i=eeprom_i2c_sda_i,
eeprom_i2c_sda_o=eeprom_i2c_sda_o,
eeprom_i2c_sda_t=eeprom_i2c_sda_t,
fpga_boot=fpga_boot,
flash_dq_i=flash_dq_i,
flash_dq_o=flash_dq_o,
flash_dq_oe=flash_dq_oe,

3
fpga/mqnic_tdma/ExaNIC_X10/fpga/tb/test_fpga_core.v
View File

@ -165,6 +165,7 @@ wire eeprom_i2c_scl_o;
wire eeprom_i2c_scl_t;
wire eeprom_i2c_sda_o;
wire eeprom_i2c_sda_t;
wire fpga_boot;
wire [15:0] flash_dq_o;
wire flash_dq_oe;
wire [22:0] flash_addr;
@ -289,6 +290,7 @@ initial begin
eeprom_i2c_scl_t,
eeprom_i2c_sda_o,
eeprom_i2c_sda_t,
fpga_boot,
flash_dq_o,
flash_dq_oe,
flash_addr,
@ -423,6 +425,7 @@ UUT (
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
.fpga_boot(fpga_boot),
.flash_dq_i(flash_dq_i),
.flash_dq_o(flash_dq_o),
.flash_dq_oe(flash_dq_oe),