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Add ethernet frame to AXI stream modules

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Alex Forencich 2014-09-14 01:06:48 -07:00
parent e1955a29da
commit 8e4d162667
13 changed files with 4470 additions and 0 deletions
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377
rtl/eth_axis_rx.v Normal file
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out)
*/
module eth_axis_rx
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* Ethernet frame output
*/
output wire output_eth_hdr_valid,
input wire output_eth_hdr_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [7:0] output_eth_payload_tdata,
output wire output_eth_payload_tvalid,
input wire output_eth_payload_tready,
output wire output_eth_payload_tlast,
output wire output_eth_payload_tuser,
/*
* Status signals
*/
output wire busy,
output wire frame_error
);
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame on an 8 bit wide AXI interface,
separates the dest MAC, source MAC, and eth type into separate parallel
outputs, and forwards the payload data out through a separate AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD_IDLE = 3'd2,
STATE_READ_PAYLOAD_TRANSFER = 3'd3,
STATE_READ_PAYLOAD_TRANSFER_WAIT = 3'd4,
STATE_READ_PAYLOAD_TRANSFER_LAST = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_dest_mac_0;
reg store_eth_dest_mac_1;
reg store_eth_dest_mac_2;
reg store_eth_dest_mac_3;
reg store_eth_dest_mac_4;
reg store_eth_dest_mac_5;
reg store_eth_src_mac_0;
reg store_eth_src_mac_1;
reg store_eth_src_mac_2;
reg store_eth_src_mac_3;
reg store_eth_src_mac_4;
reg store_eth_src_mac_5;
reg store_eth_type_0;
reg store_eth_type_1;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_axis_tready_reg = 0;
reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [7:0] output_eth_payload_tdata_reg = 0;
reg output_eth_payload_tvalid_reg = 0;
reg output_eth_payload_tlast_reg = 0;
reg output_eth_payload_tuser_reg = 0;
reg busy_reg = 0, busy_next;
reg frame_error_reg = 0, frame_error_next;
reg [7:0] temp_eth_payload_tdata_reg = 0;
reg temp_eth_payload_tlast_reg = 0;
reg temp_eth_payload_tuser_reg = 0;
assign input_axis_tready = input_axis_tready_reg;
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
assign busy = busy_reg;
assign frame_error = frame_error_reg;
always @* begin
state_next = 2'bz;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
store_eth_dest_mac_0 = 0;
store_eth_dest_mac_1 = 0;
store_eth_dest_mac_2 = 0;
store_eth_dest_mac_3 = 0;
store_eth_dest_mac_4 = 0;
store_eth_dest_mac_5 = 0;
store_eth_src_mac_0 = 0;
store_eth_src_mac_1 = 0;
store_eth_src_mac_2 = 0;
store_eth_src_mac_3 = 0;
store_eth_src_mac_4 = 0;
store_eth_src_mac_5 = 0;
store_eth_type_0 = 0;
store_eth_type_1 = 0;
frame_ptr_next = frame_ptr_reg;
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
frame_error_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_axis_tready & input_axis_tvalid) begin
frame_ptr_next = 1;
store_eth_dest_mac_5 = 1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
if (input_axis_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_READ_HEADER;
case (frame_ptr_reg)
8'h00: store_eth_dest_mac_5 = 1;
8'h01: store_eth_dest_mac_4 = 1;
8'h02: store_eth_dest_mac_3 = 1;
8'h03: store_eth_dest_mac_2 = 1;
8'h04: store_eth_dest_mac_1 = 1;
8'h05: store_eth_dest_mac_0 = 1;
8'h06: store_eth_src_mac_5 = 1;
8'h07: store_eth_src_mac_4 = 1;
8'h08: store_eth_src_mac_3 = 1;
8'h09: store_eth_src_mac_2 = 1;
8'h0A: store_eth_src_mac_1 = 1;
8'h0B: store_eth_src_mac_0 = 1;
8'h0C: store_eth_type_1 = 1;
8'h0D: begin
store_eth_type_0 = 1;
output_eth_hdr_valid_next = 1;
state_next = STATE_READ_PAYLOAD_IDLE;
end
endcase
if (input_axis_tlast) begin
state_next = STATE_IDLE;
frame_error_next = 1;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_axis_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
if (input_axis_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_READ_PAYLOAD_IDLE;
end
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_axis_tvalid & output_eth_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
if (input_axis_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else if (~input_axis_tvalid & output_eth_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_READ_PAYLOAD_IDLE;
end else if (input_axis_tvalid & ~output_eth_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_eth_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_eth_payload_tlast_reg) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_eth_payload_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_axis_tready_reg <= 0;
output_eth_hdr_valid_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
output_eth_payload_tdata_reg <= 0;
output_eth_payload_tvalid_reg <= 0;
output_eth_payload_tlast_reg <= 0;
output_eth_payload_tuser_reg <= 0;
temp_eth_payload_tdata_reg <= 0;
temp_eth_payload_tlast_reg <= 0;
temp_eth_payload_tuser_reg <= 0;
busy_reg <= 0;
frame_error_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
frame_error_reg <= frame_error_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_axis_tready_reg <= ~output_eth_hdr_valid;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_axis_tready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_axis_tready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
endcase
// datapath
if (store_eth_dest_mac_0) output_eth_dest_mac_reg[ 7: 0] <= input_axis_tdata;
if (store_eth_dest_mac_1) output_eth_dest_mac_reg[15: 8] <= input_axis_tdata;
if (store_eth_dest_mac_2) output_eth_dest_mac_reg[23:16] <= input_axis_tdata;
if (store_eth_dest_mac_3) output_eth_dest_mac_reg[31:24] <= input_axis_tdata;
if (store_eth_dest_mac_4) output_eth_dest_mac_reg[39:32] <= input_axis_tdata;
if (store_eth_dest_mac_5) output_eth_dest_mac_reg[47:40] <= input_axis_tdata;
if (store_eth_src_mac_0) output_eth_src_mac_reg[ 7: 0] <= input_axis_tdata;
if (store_eth_src_mac_1) output_eth_src_mac_reg[15: 8] <= input_axis_tdata;
if (store_eth_src_mac_2) output_eth_src_mac_reg[23:16] <= input_axis_tdata;
if (store_eth_src_mac_3) output_eth_src_mac_reg[31:24] <= input_axis_tdata;
if (store_eth_src_mac_4) output_eth_src_mac_reg[39:32] <= input_axis_tdata;
if (store_eth_src_mac_5) output_eth_src_mac_reg[47:40] <= input_axis_tdata;
if (store_eth_type_0) output_eth_type_reg[ 7: 0] <= input_axis_tdata;
if (store_eth_type_1) output_eth_type_reg[15: 8] <= input_axis_tdata;
if (transfer_in_out) begin
output_eth_payload_tdata_reg <= input_axis_tdata;
output_eth_payload_tlast_reg <= input_axis_tlast;
output_eth_payload_tuser_reg <= input_axis_tuser;
end else if (transfer_in_temp) begin
temp_eth_payload_tdata_reg <= input_axis_tdata;
temp_eth_payload_tlast_reg <= input_axis_tlast;
temp_eth_payload_tuser_reg <= input_axis_tuser;
end else if (transfer_temp_out) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
end
end
endmodule

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame receiver (AXI in, Ethernet frame out, 64 bit datapath)
*/
module eth_axis_rx_64
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [63:0] input_axis_tdata,
input wire [7:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* Ethernet frame output
*/
output wire output_eth_hdr_valid,
input wire output_eth_hdr_ready,
output wire [47:0] output_eth_dest_mac,
output wire [47:0] output_eth_src_mac,
output wire [15:0] output_eth_type,
output wire [63:0] output_eth_payload_tdata,
output wire [7:0] output_eth_payload_tkeep,
output wire output_eth_payload_tvalid,
input wire output_eth_payload_tready,
output wire output_eth_payload_tlast,
output wire output_eth_payload_tuser,
/*
* Status signals
*/
output wire busy,
output wire frame_error
);
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame on an 8 bit wide AXI interface,
separates the dest MAC, source MAC, and eth type into separate parallel
outputs, and forwards the payload data out through a separate AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD_IDLE = 3'd2,
STATE_READ_PAYLOAD_TRANSFER = 3'd3,
STATE_READ_PAYLOAD_TRANSFER_WAIT = 3'd4,
STATE_READ_PAYLOAD_TRANSFER_LAST = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_hdr_word_0;
reg store_hdr_word_1;
reg transfer_in_save;
reg transfer_save_out;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg input_axis_tready_reg = 0;
reg output_eth_hdr_valid_reg = 0, output_eth_hdr_valid_next;
reg [47:0] output_eth_dest_mac_reg = 0;
reg [47:0] output_eth_src_mac_reg = 0;
reg [15:0] output_eth_type_reg = 0;
reg [63:0] output_eth_payload_tdata_reg = 0;
reg [7:0] output_eth_payload_tkeep_reg = 0;
reg output_eth_payload_tvalid_reg = 0;
reg output_eth_payload_tlast_reg = 0;
reg output_eth_payload_tuser_reg = 0;
reg busy_reg = 0, busy_next;
reg frame_error_reg = 0, frame_error_next;
reg [63:0] temp_eth_payload_tdata_reg = 0;
reg [7:0] temp_eth_payload_tkeep_reg = 0;
reg temp_eth_payload_tlast_reg = 0;
reg temp_eth_payload_tuser_reg = 0;
reg [63:0] save_axis_tdata_reg = 0;
reg [7:0] save_axis_tkeep_reg = 0;
reg save_axis_tlast_reg = 0;
reg save_axis_tuser_reg = 0;
assign input_axis_tready = input_axis_tready_reg;
assign output_eth_hdr_valid = output_eth_hdr_valid_reg;
assign output_eth_dest_mac = output_eth_dest_mac_reg;
assign output_eth_src_mac = output_eth_src_mac_reg;
assign output_eth_type = output_eth_type_reg;
assign output_eth_payload_tdata = output_eth_payload_tdata_reg;
assign output_eth_payload_tkeep = output_eth_payload_tkeep_reg;
assign output_eth_payload_tvalid = output_eth_payload_tvalid_reg;
assign output_eth_payload_tlast = output_eth_payload_tlast_reg;
assign output_eth_payload_tuser = output_eth_payload_tuser_reg;
assign busy = busy_reg;
assign frame_error = frame_error_reg;
always @* begin
state_next = 2'bz;
transfer_in_save = 0;
transfer_save_out = 0;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
store_hdr_word_0 = 0;
store_hdr_word_1 = 0;
frame_ptr_next = frame_ptr_reg;
output_eth_hdr_valid_next = output_eth_hdr_valid_reg & ~output_eth_hdr_ready;
frame_error_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_axis_tready & input_axis_tvalid) begin
frame_ptr_next = 8;
store_hdr_word_0 = 1;
transfer_in_save = 1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header state
if (input_axis_tvalid) begin
// word transfer in - store it
frame_ptr_next = frame_ptr_reg+8;
transfer_in_save = 1;
state_next = STATE_READ_HEADER;
case (frame_ptr_reg)
8'h00: store_hdr_word_0 = 1;
8'h08: begin
store_hdr_word_1 = 1;
output_eth_hdr_valid_next = 1;
state_next = STATE_READ_PAYLOAD_IDLE;
end
endcase
if (input_axis_tlast) begin
state_next = STATE_IDLE;
frame_error_next = 1;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_axis_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
transfer_in_save = 1;
if (input_axis_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_READ_PAYLOAD_IDLE;
end
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_axis_tvalid & output_eth_payload_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
transfer_in_save = 1;
if (input_axis_tlast) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else if (~input_axis_tvalid & output_eth_payload_tready) begin
// word transfer out - go back to idle
state_next = STATE_READ_PAYLOAD_IDLE;
end else if (input_axis_tvalid & ~output_eth_payload_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
transfer_in_save = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_eth_payload_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_eth_payload_tlast_reg | (save_axis_tlast_reg & save_axis_tkeep_reg[7:6] != 0)) begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_eth_payload_tready) begin
// word transfer out
if (save_axis_tkeep_reg[7:6]) begin
// part of word in save register
transfer_save_out = 1;
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end else begin
// nothing in save register; done
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_PAYLOAD_TRANSFER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_axis_tready_reg <= 0;
output_eth_hdr_valid_reg <= 0;
output_eth_dest_mac_reg <= 0;
output_eth_src_mac_reg <= 0;
output_eth_type_reg <= 0;
output_eth_payload_tdata_reg <= 0;
output_eth_payload_tvalid_reg <= 0;
output_eth_payload_tlast_reg <= 0;
output_eth_payload_tuser_reg <= 0;
temp_eth_payload_tdata_reg <= 0;
temp_eth_payload_tlast_reg <= 0;
temp_eth_payload_tuser_reg <= 0;
busy_reg <= 0;
frame_error_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_eth_hdr_valid_reg <= output_eth_hdr_valid_next;
frame_error_reg <= frame_error_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_axis_tready_reg <= ~output_eth_hdr_valid;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_HEADER: begin
// read header; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 0;
end
STATE_READ_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_axis_tready_reg <= 1;
output_eth_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_axis_tready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
STATE_READ_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_axis_tready_reg <= 0;
output_eth_payload_tvalid_reg <= 1;
end
endcase
// datapath
if (store_hdr_word_0) begin
output_eth_dest_mac_reg[47:40] <= input_axis_tdata[ 7: 0];
output_eth_dest_mac_reg[39:32] <= input_axis_tdata[15: 8];
output_eth_dest_mac_reg[31:24] <= input_axis_tdata[23:16];
output_eth_dest_mac_reg[23:16] <= input_axis_tdata[31:24];
output_eth_dest_mac_reg[15: 8] <= input_axis_tdata[39:32];
output_eth_dest_mac_reg[ 7: 0] <= input_axis_tdata[47:40];
output_eth_src_mac_reg[47:40] <= input_axis_tdata[55:48];
output_eth_src_mac_reg[39:32] <= input_axis_tdata[63:56];
end
if (store_hdr_word_1) begin
output_eth_src_mac_reg[31:24] <= input_axis_tdata[ 7: 0];
output_eth_src_mac_reg[23:16] <= input_axis_tdata[15: 8];
output_eth_src_mac_reg[15: 8] <= input_axis_tdata[23:16];
output_eth_src_mac_reg[ 7: 0] <= input_axis_tdata[31:24];
output_eth_type_reg[15:8] <= input_axis_tdata[39:32];
output_eth_type_reg[ 7:0] <= input_axis_tdata[47:40];
end
if (transfer_in_save) begin
save_axis_tdata_reg <= input_axis_tdata;
save_axis_tkeep_reg <= input_axis_tkeep;
save_axis_tlast_reg <= input_axis_tlast;
save_axis_tuser_reg <= input_axis_tuser;
end else if (transfer_save_out) begin
output_eth_payload_tdata_reg <= {48'd0, save_axis_tdata_reg[63:48]};
output_eth_payload_tkeep_reg <= {6'd0, save_axis_tkeep_reg[7:6]};
output_eth_payload_tlast_reg <= save_axis_tlast_reg;
output_eth_payload_tuser_reg <= save_axis_tuser_reg;
save_axis_tkeep_reg <= 0;
end
if (transfer_in_out) begin
output_eth_payload_tdata_reg <= {input_axis_tdata[47:0], save_axis_tdata_reg[63:48]};
output_eth_payload_tkeep_reg <= {input_axis_tkeep[5:0], save_axis_tkeep_reg[7:6]};
output_eth_payload_tlast_reg <= input_axis_tlast & (input_axis_tkeep[7:6] == 0);
output_eth_payload_tuser_reg <= input_axis_tuser & (input_axis_tkeep[7:6] == 0);
end else if (transfer_in_temp) begin
temp_eth_payload_tdata_reg <= {input_axis_tdata[47:0], save_axis_tdata_reg[63:48]};
temp_eth_payload_tkeep_reg <= {input_axis_tkeep[5:0], save_axis_tkeep_reg[7:6]};
temp_eth_payload_tlast_reg <= input_axis_tlast & (input_axis_tkeep[7:6] == 0);
temp_eth_payload_tuser_reg <= input_axis_tuser & (input_axis_tkeep[7:6] == 0);
end else if (transfer_temp_out) begin
output_eth_payload_tdata_reg <= temp_eth_payload_tdata_reg;
output_eth_payload_tkeep_reg <= temp_eth_payload_tkeep_reg;
output_eth_payload_tlast_reg <= temp_eth_payload_tlast_reg;
output_eth_payload_tuser_reg <= temp_eth_payload_tuser_reg;
end
end
end
endmodule

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out)
*/
module eth_axis_tx
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [7:0] input_eth_payload_tdata,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status signals
*/
output wire busy
);
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame with parallel field input
and an AXI interface for the payload data and produces an AXI
output stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD_IDLE = 3'd2,
STATE_WRITE_PAYLOAD_TRANSFER = 3'd3,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd4,
STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg [7:0] write_hdr_data;
reg write_hdr_out;
reg transfer_in_save;
reg transfer_save_out;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [47:0] eth_dest_mac_reg = 0;
reg [47:0] eth_src_mac_reg = 0;
reg [15:0] eth_type_reg = 0;
reg input_eth_hdr_ready_reg = 0;
reg input_eth_payload_tready_reg = 0;
reg [7:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg busy_reg = 0;
reg [7:0] temp_axis_tdata_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
store_eth_hdr = 0;
write_hdr_data = 0;
write_hdr_out = 0;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
frame_ptr_next = frame_ptr_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_eth_payload_tvalid) begin
store_eth_hdr = 1;
write_hdr_out = 1;
write_hdr_data = input_eth_dest_mac[47:40];
frame_ptr_next = 1;
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// read header state
if (output_axis_tready) begin
// word transfer out
frame_ptr_next = frame_ptr_reg+1;
state_next = STATE_WRITE_HEADER;
write_hdr_out = 1;
case (frame_ptr_reg)
8'h01: write_hdr_data = eth_dest_mac_reg[39:32];
8'h02: write_hdr_data = eth_dest_mac_reg[31:24];
8'h03: write_hdr_data = eth_dest_mac_reg[23:16];
8'h04: write_hdr_data = eth_dest_mac_reg[15: 8];
8'h05: write_hdr_data = eth_dest_mac_reg[ 7: 0];
8'h06: write_hdr_data = eth_src_mac_reg[47:40];
8'h07: write_hdr_data = eth_src_mac_reg[39:32];
8'h08: write_hdr_data = eth_src_mac_reg[31:24];
8'h09: write_hdr_data = eth_src_mac_reg[23:16];
8'h0A: write_hdr_data = eth_src_mac_reg[15: 8];
8'h0B: write_hdr_data = eth_src_mac_reg[ 7: 0];
8'h0C: write_hdr_data = eth_type_reg[15: 8];
8'h0D: begin
write_hdr_data = eth_type_reg[ 7: 0];
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_eth_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_out = 1;
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_IDLE;
end
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_eth_payload_tvalid & output_axis_tready) begin
// word transfer through - update output register
transfer_in_out = 1;
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else if (~input_eth_payload_tvalid & output_axis_tready) begin
// word transfer out - go back to idle
state_next = STATE_WRITE_PAYLOAD_IDLE;
end else if (input_eth_payload_tvalid & ~output_axis_tready) begin
// word transfer in - store in temp
transfer_in_temp = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_axis_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_axis_tlast_reg) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_axis_tready) begin
// word transfer out - done
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
eth_dest_mac_reg <= 0;
eth_src_mac_reg <= 0;
eth_type_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_eth_hdr_ready_reg <= 1;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 0;
end
STATE_WRITE_HEADER: begin
// read header; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
endcase
if (store_eth_hdr) begin
eth_dest_mac_reg <= input_eth_dest_mac;
eth_src_mac_reg <= input_eth_src_mac;
eth_type_reg <= input_eth_type;
end
if (write_hdr_out) begin
output_axis_tdata_reg <= write_hdr_data;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
end else if (transfer_in_out) begin
output_axis_tdata_reg <= input_eth_payload_tdata;
output_axis_tlast_reg <= input_eth_payload_tlast;
output_axis_tuser_reg <= input_eth_payload_tuser;
end else if (transfer_in_temp) begin
temp_axis_tdata_reg <= input_eth_payload_tdata;
temp_axis_tlast_reg <= input_eth_payload_tlast;
temp_axis_tuser_reg <= input_eth_payload_tuser;
end else if (transfer_temp_out) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
end
end
endmodule

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream ethernet frame transmitter (Ethernet frame in, AXI out, 64 bit datapath)
*/
module eth_axis_tx_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire input_eth_hdr_valid,
output wire input_eth_hdr_ready,
input wire [47:0] input_eth_dest_mac,
input wire [47:0] input_eth_src_mac,
input wire [15:0] input_eth_type,
input wire [63:0] input_eth_payload_tdata,
input wire [7:0] input_eth_payload_tkeep,
input wire input_eth_payload_tvalid,
output wire input_eth_payload_tready,
input wire input_eth_payload_tlast,
input wire input_eth_payload_tuser,
/*
* AXI output
*/
output wire [63:0] output_axis_tdata,
output wire [7:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status signals
*/
output wire busy
);
/*
Ethernet frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype 2 octets
This module receives an Ethernet frame with parallel field input
and an AXI interface for the payload data and produces an AXI
output stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_HEADER_LAST = 3'd2,
STATE_WRITE_HEADER_LAST_WAIT = 3'd3,
STATE_WRITE_PAYLOAD_IDLE = 3'd4,
STATE_WRITE_PAYLOAD_TRANSFER = 3'd5,
STATE_WRITE_PAYLOAD_TRANSFER_WAIT = 3'd6,
STATE_WRITE_PAYLOAD_TRANSFER_LAST = 3'd7;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg [63:0] write_hdr_data;
reg [7:0] write_hdr_keep;
reg write_hdr_out;
reg write_hdr_temp;
reg transfer_in_save;
reg transfer_save_out;
reg transfer_in_out;
reg transfer_in_temp;
reg transfer_temp_out;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [47:0] eth_dest_mac_reg = 0;
reg [47:0] eth_src_mac_reg = 0;
reg [15:0] eth_type_reg = 0;
reg input_eth_hdr_ready_reg = 0;
reg input_eth_payload_tready_reg = 0;
reg [63:0] output_axis_tdata_reg = 0;
reg [7:0] output_axis_tkeep_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg busy_reg = 0;
reg [63:0] temp_axis_tdata_reg = 0;
reg [7:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
reg [63:0] save_eth_payload_tdata_reg = 0;
reg [7:0] save_eth_payload_tkeep_reg = 0;
reg save_eth_payload_tlast_reg = 0;
reg save_eth_payload_tuser_reg = 0;
assign input_eth_hdr_ready = input_eth_hdr_ready_reg;
assign input_eth_payload_tready = input_eth_payload_tready_reg;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign busy = busy_reg;
always @* begin
state_next = 2'bz;
store_eth_hdr = 0;
write_hdr_data = 0;
write_hdr_keep = 0;
write_hdr_out = 0;
write_hdr_temp = 0;
transfer_in_save = 0;
transfer_save_out = 0;
transfer_in_out = 0;
transfer_in_temp = 0;
transfer_temp_out = 0;
frame_ptr_next = frame_ptr_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 0;
if (input_eth_payload_tvalid) begin
store_eth_hdr = 1;
write_hdr_out = 1;
write_hdr_data[ 7: 0] = input_eth_dest_mac[47:40];
write_hdr_data[15: 8] = input_eth_dest_mac[39:32];
write_hdr_data[23:16] = input_eth_dest_mac[31:24];
write_hdr_data[31:24] = input_eth_dest_mac[23:16];
write_hdr_data[39:32] = input_eth_dest_mac[15: 8];
write_hdr_data[47:40] = input_eth_dest_mac[ 7: 0];
write_hdr_data[55:48] = input_eth_src_mac[47:40];
write_hdr_data[63:56] = input_eth_src_mac[39:32];
write_hdr_keep = 8'hff;
frame_ptr_next = 8;
state_next = STATE_WRITE_HEADER_LAST;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER_LAST: begin
// last header word requires first payload word; process accordingly
if (input_eth_payload_tvalid & output_axis_tready) begin
// word transfer through - update output register
transfer_in_save = 1;
write_hdr_out = 1;
write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
write_hdr_data[39:32] = eth_type_reg[15: 8];
write_hdr_data[47:40] = eth_type_reg[ 7: 0];
write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else if (~input_eth_payload_tvalid & output_axis_tready) begin
// word transfer out - go back to idle
state_next = STATE_WRITE_HEADER_LAST_WAIT;
end else if (input_eth_payload_tvalid & ~output_axis_tready) begin
// word transfer in - store in temp
transfer_in_save = 1;
write_hdr_temp = 1;
write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
write_hdr_data[39:32] = eth_type_reg[15: 8];
write_hdr_data[47:40] = eth_type_reg[ 7: 0];
write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
STATE_WRITE_HEADER_LAST_WAIT: begin
// last header word requires first payload word; no data in registers
if (input_eth_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_save = 1;
write_hdr_out = 1;
write_hdr_data[ 7: 0] = eth_src_mac_reg[31:24];
write_hdr_data[15: 8] = eth_src_mac_reg[23:16];
write_hdr_data[23:16] = eth_src_mac_reg[15: 8];
write_hdr_data[31:24] = eth_src_mac_reg[ 7: 0];
write_hdr_data[39:32] = eth_type_reg[15: 8];
write_hdr_data[47:40] = eth_type_reg[ 7: 0];
write_hdr_data[55:48] = input_eth_payload_tdata[ 7: 0];
write_hdr_data[63:56] = input_eth_payload_tdata[15: 8];
write_hdr_keep = {input_eth_payload_tkeep[1:0], 6'h3F};
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_WRITE_HEADER_LAST_WAIT;
end
end
STATE_WRITE_PAYLOAD_IDLE: begin
// idle; no data in registers
if (input_eth_payload_tvalid) begin
// word transfer in - store it in output register
transfer_in_save = 1;
transfer_in_out = 1;
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_IDLE;
end
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// read payload; data in output register
if (input_eth_payload_tvalid & output_axis_tready) begin
// word transfer through - update output register
transfer_in_save = 1;
transfer_in_out = 1;
if (input_eth_payload_tlast) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else if (~input_eth_payload_tvalid & output_axis_tready) begin
// word transfer out - go back to idle
state_next = STATE_WRITE_PAYLOAD_IDLE;
end else if (input_eth_payload_tvalid & ~output_axis_tready) begin
// word transfer in - store in temp
transfer_in_save = 1;
transfer_in_temp = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in both output and temp registers
if (output_axis_tready) begin
// transfer out - move temp to output
transfer_temp_out = 1;
if (temp_axis_tlast_reg | (save_eth_payload_tlast_reg & save_eth_payload_tkeep_reg[7:6] != 0)) begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_WAIT;
end
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
if (output_axis_tready) begin
// word transfer out - done
if (save_eth_payload_tkeep_reg[7:2]) begin
// part of word in save register
transfer_save_out = 1;
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end else begin
// nothing in save register; done
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_TRANSFER_LAST;
end
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
eth_dest_mac_reg <= 0;
eth_src_mac_reg <= 0;
eth_type_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
busy_reg <= 0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
// generate valid outputs
case (state_next)
STATE_IDLE: begin
// idle; accept new data
input_eth_hdr_ready_reg <= 1;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 0;
end
STATE_WRITE_HEADER: begin
// read header; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_HEADER_LAST: begin
// write last header word; need first data word
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_HEADER_LAST_WAIT: begin
// last header word requires first payload word; no data in registers
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_IDLE: begin
// read payload; no data in registers; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 0;
end
STATE_WRITE_PAYLOAD_TRANSFER: begin
// read payload; data in output register; accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 1;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_WAIT: begin
// read payload; data in output and temp registers; do not accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
STATE_WRITE_PAYLOAD_TRANSFER_LAST: begin
// read last payload word; data in output register; do not accept new data
input_eth_hdr_ready_reg <= 0;
input_eth_payload_tready_reg <= 0;
output_axis_tvalid_reg <= 1;
end
endcase
if (store_eth_hdr) begin
eth_dest_mac_reg <= input_eth_dest_mac;
eth_src_mac_reg <= input_eth_src_mac;
eth_type_reg <= input_eth_type;
end
if (transfer_in_save) begin
save_eth_payload_tdata_reg <= input_eth_payload_tdata;
save_eth_payload_tkeep_reg <= input_eth_payload_tkeep;
save_eth_payload_tlast_reg <= input_eth_payload_tlast;
save_eth_payload_tuser_reg <= input_eth_payload_tuser;
end else if (transfer_save_out) begin
output_axis_tdata_reg <= {16'd0, save_eth_payload_tdata_reg[63:16]};
output_axis_tkeep_reg <= {2'd0, save_eth_payload_tkeep_reg[7:2]};
output_axis_tlast_reg <= save_eth_payload_tlast_reg;
output_axis_tuser_reg <= save_eth_payload_tuser_reg;
save_eth_payload_tkeep_reg <= 0;
end
if (write_hdr_out) begin
output_axis_tdata_reg <= write_hdr_data;
output_axis_tkeep_reg <= write_hdr_keep;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
end else if (write_hdr_temp) begin
temp_axis_tdata_reg <= write_hdr_data;
temp_axis_tkeep_reg <= write_hdr_keep;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else if (transfer_in_out) begin
output_axis_tdata_reg <= {input_eth_payload_tdata[15:0], save_eth_payload_tdata_reg[63:16]};
output_axis_tkeep_reg <= {input_eth_payload_tkeep[1:0], save_eth_payload_tkeep_reg[7:2]};
output_axis_tlast_reg <= input_eth_payload_tlast & (input_eth_payload_tkeep[7:2] == 0);
output_axis_tuser_reg <= input_eth_payload_tuser & (input_eth_payload_tkeep[7:2] == 0);
end else if (transfer_in_temp) begin
temp_axis_tdata_reg <= {input_eth_payload_tdata[15:0], save_eth_payload_tdata_reg[63:16]};
temp_axis_tkeep_reg <= {input_eth_payload_tkeep[1:0], save_eth_payload_tkeep_reg[7:2]};
temp_axis_tlast_reg <= input_eth_payload_tlast & (input_eth_payload_tkeep[7:2] == 0);
temp_axis_tuser_reg <= input_eth_payload_tuser & (input_eth_payload_tkeep[7:2] == 0);
end else if (transfer_temp_out) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
end
end
endmodule

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"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import axis_ep
from Queue import Queue
import struct
class EthFrame(object):
def __init__(self, payload=b'', eth_dest_mac=0, eth_src_mac=0, eth_type=0):
self._payload = axis_ep.AXIStreamFrame()
self.eth_dest_mac = eth_dest_mac
self.eth_src_mac = eth_src_mac
self.eth_type = eth_type
if type(payload) is dict:
self.payload = axis_ep.AXIStreamFrame(payload['eth_payload'])
self.eth_dest_mac = payload['eth_dest_mac']
self.eth_src_mac = payload['eth_src_mac']
self.eth_type = payload['eth_type']
if type(payload) is bytes:
payload = bytearray(payload)
if type(payload) is bytearray or type(payload) is axis_ep.AXIStreamFrame:
self.payload = axis_ep.AXIStreamFrame(payload)
if type(payload) is EthFrame:
self.payload = axis_ep.AXIStreamFrame(payload.payload)
self.eth_dest_mac = payload.eth_dest_mac
self.eth_src_mac = payload.eth_src_mac
self.eth_type = payload.eth_type
@property
def payload(self):
return self._payload
@payload.setter
def payload(self, value):
self._payload = axis_ep.AXIStreamFrame(value)
def build_axis(self):
data = b''
data += struct.pack('>Q', self.eth_dest_mac)[2:]
data += struct.pack('>Q', self.eth_src_mac)[2:]
data += struct.pack('>H', self.eth_type)
data += self.payload.data
return axis_ep.AXIStreamFrame(data)
def parse_axis(self, data):
data = axis_ep.AXIStreamFrame(data).data
self.eth_dest_mac = struct.unpack('>Q', '\x00\x00'+data[0:6])[0]
self.eth_src_mac = struct.unpack('>Q', '\x00\x00'+data[6:12])[0]
self.eth_type = struct.unpack('>H', data[12:14])[0]
data = data[14:]
self.payload = axis_ep.AXIStreamFrame(data)
def __eq__(self, other):
if type(other) is EthFrame:
return (self.eth_src_mac == other.eth_src_mac and
self.eth_dest_mac == other.eth_dest_mac and
self.eth_type == other.eth_type and
self.payload == other.payload)
def __repr__(self):
return 'EthFrame(payload=%s, eth_dest_mac=0x%012x, eth_src_mac=0x%012x, eth_type=0x%04x)' % (repr(self.payload), self.eth_dest_mac, self.eth_src_mac, self.eth_type)
def EthFrameSource(clk, rst,
eth_hdr_valid=None,
eth_hdr_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
eth_payload_tdata=None,
eth_payload_tkeep=Signal(bool(True)),
eth_payload_tvalid=Signal(bool(False)),
eth_payload_tready=Signal(bool(True)),
eth_payload_tlast=Signal(bool(False)),
eth_payload_tuser=Signal(bool(False)),
fifo=None,
pause=0,
name=None):
eth_hdr_ready_int = Signal(bool(False))
eth_hdr_valid_int = Signal(bool(False))
eth_payload_pause = Signal(bool(False))
eth_payload_fifo = Queue()
eth_payload_source = axis_ep.AXIStreamSource(clk,
rst,
tdata=eth_payload_tdata,
tkeep=eth_payload_tkeep,
tvalid=eth_payload_tvalid,
tready=eth_payload_tready,
tlast=eth_payload_tlast,
tuser=eth_payload_tuser,
fifo=eth_payload_fifo,
pause=eth_payload_pause)
@always_comb
def pause_logic():
eth_hdr_ready_int.next = eth_hdr_ready and not pause
eth_hdr_valid.next = eth_hdr_valid_int and not pause
eth_payload_pause.next = pause # or eth_hdr_valid_int
@instance
def logic():
frame = dict()
while True:
yield clk.posedge, rst.posedge
if rst:
eth_hdr_valid_int.next = False
else:
if eth_hdr_ready_int:
eth_hdr_valid_int.next = False
if (eth_payload_tlast and eth_hdr_ready_int and eth_hdr_valid) or not eth_hdr_valid_int:
if not fifo.empty():
frame = fifo.get()
frame = EthFrame(frame)
eth_dest_mac.next = frame.eth_dest_mac
eth_src_mac.next = frame.eth_src_mac
eth_type.next = frame.eth_type
eth_payload_fifo.put(frame.payload)
if name is not None:
print("[%s] Sending frame %s" % (name, repr(frame)))
eth_hdr_valid_int.next = True
return logic, pause_logic, eth_payload_source
def EthFrameSink(clk, rst,
eth_hdr_valid=None,
eth_hdr_ready=None,
eth_dest_mac=None,
eth_src_mac=None,
eth_type=None,
eth_payload_tdata=None,
eth_payload_tkeep=Signal(bool(True)),
eth_payload_tvalid=Signal(bool(True)),
eth_payload_tready=Signal(bool(True)),
eth_payload_tlast=Signal(bool(True)),
eth_payload_tuser=Signal(bool(False)),
fifo=None,
pause=0,
name=None):
eth_hdr_ready_int = Signal(bool(False))
eth_hdr_valid_int = Signal(bool(False))
eth_payload_pause = Signal(bool(False))
eth_payload_fifo = Queue()
eth_header_fifo = Queue()
eth_payload_sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=eth_payload_tdata,
tkeep=eth_payload_tkeep,
tvalid=eth_payload_tvalid,
tready=eth_payload_tready,
tlast=eth_payload_tlast,
tuser=eth_payload_tuser,
fifo=eth_payload_fifo,
pause=eth_payload_pause)
@always_comb
def pause_logic():
eth_hdr_ready.next = eth_hdr_ready_int and not pause
eth_hdr_valid_int.next = eth_hdr_valid and not pause
eth_payload_pause.next = pause # or eth_hdr_valid_int
@instance
def logic():
frame = EthFrame()
while True:
yield clk.posedge, rst.posedge
if rst:
eth_hdr_ready_int.next = False
frame = EthFrame()
else:
eth_hdr_ready_int.next = True
if eth_hdr_ready_int and eth_hdr_valid_int:
frame = EthFrame()
frame.eth_dest_mac = int(eth_dest_mac)
frame.eth_src_mac = int(eth_src_mac)
frame.eth_type = int(eth_type)
eth_header_fifo.put(frame)
if not eth_payload_fifo.empty() and not eth_header_fifo.empty():
frame = eth_header_fifo.get()
frame.payload = eth_payload_fifo.get()
fifo.put(frame)
if name is not None:
print("[%s] Got frame %s" % (name, repr(frame)))
frame = dict()
return logic, pause_logic, eth_payload_sink

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
module = 'eth_axis_rx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_axis_rx(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_eth_hdr_valid=output_eth_hdr_valid,
output_eth_hdr_ready=output_eth_hdr_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_eth_payload_tdata=output_eth_payload_tdata,
output_eth_payload_tvalid=output_eth_payload_tvalid,
output_eth_payload_tready=output_eth_payload_tready,
output_eth_payload_tlast=output_eth_payload_tlast,
output_eth_payload_tuser=output_eth_payload_tuser,
busy=busy,
frame_error=frame_error)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_eth_payload_tready = Signal(bool(0))
output_eth_hdr_ready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_eth_hdr_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_eth_payload_tdata = Signal(intbv(0)[8:])
output_eth_payload_tvalid = Signal(bool(0))
output_eth_payload_tlast = Signal(bool(0))
output_eth_payload_tuser = Signal(bool(0))
busy = Signal(bool(0))
frame_error = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = eth_ep.EthFrameSink(clk,
rst,
eth_hdr_ready=output_eth_hdr_ready,
eth_hdr_valid=output_eth_hdr_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
eth_payload_tdata=output_eth_payload_tdata,
eth_payload_tvalid=output_eth_payload_tvalid,
eth_payload_tready=output_eth_payload_tready,
eth_payload_tlast=output_eth_payload_tlast,
eth_payload_tuser=output_eth_payload_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_eth_axis_rx(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
output_eth_hdr_ready.next = True
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source 2")
current_test.next = 7
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink 2")
current_test.next = 8
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 9: tuser assert")
current_test.next = 9
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
axi_frame = test_frame.build_axis()
axi_frame.user = 1
source_queue.put(axi_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
assert rx_frame.payload.user[-1]
yield delay(100)
yield clk.posedge
print("test 10: truncated packet")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = bytearray(b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09')
source_queue.put(test_frame)
yield clk.posedge
yield input_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

110
tb/test_eth_axis_rx.v Normal file
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_eth_axis_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_eth_hdr_ready = 0;
reg output_eth_payload_tready = 0;
// Outputs
wire input_axis_tready;
wire output_eth_hdr_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [7:0] output_eth_payload_tdata;
wire output_eth_payload_tvalid;
wire output_eth_payload_tlast;
wire output_eth_payload_tuser;
wire busy;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_ready,
output_eth_payload_tready);
$to_myhdl(input_axis_tready,
output_eth_hdr_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tvalid,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error);
// dump file
$dumpfile("test_eth_axis_rx.lxt");
$dumpvars(0, test_eth_axis_rx);
end
eth_axis_rx
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// Ethernet frame output
.output_eth_hdr_valid(output_eth_hdr_valid),
.output_eth_hdr_ready(output_eth_hdr_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_eth_payload_tdata(output_eth_payload_tdata),
.output_eth_payload_tvalid(output_eth_payload_tvalid),
.output_eth_payload_tready(output_eth_payload_tready),
.output_eth_payload_tlast(output_eth_payload_tlast),
.output_eth_payload_tuser(output_eth_payload_tuser),
// Status signals
.busy(busy),
.frame_error(frame_error)
);
endmodule

560
tb/test_eth_axis_rx_64.py Executable file
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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
module = 'eth_axis_rx_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_axis_rx_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_eth_hdr_valid=output_eth_hdr_valid,
output_eth_hdr_ready=output_eth_hdr_ready,
output_eth_dest_mac=output_eth_dest_mac,
output_eth_src_mac=output_eth_src_mac,
output_eth_type=output_eth_type,
output_eth_payload_tdata=output_eth_payload_tdata,
output_eth_payload_tkeep=output_eth_payload_tkeep,
output_eth_payload_tvalid=output_eth_payload_tvalid,
output_eth_payload_tready=output_eth_payload_tready,
output_eth_payload_tlast=output_eth_payload_tlast,
output_eth_payload_tuser=output_eth_payload_tuser,
busy=busy,
frame_error=frame_error)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_eth_payload_tready = Signal(bool(0))
output_eth_hdr_ready = Signal(bool(0))
# Outputs
input_axis_tready = Signal(bool(0))
output_eth_hdr_valid = Signal(bool(0))
output_eth_dest_mac = Signal(intbv(0)[48:])
output_eth_src_mac = Signal(intbv(0)[48:])
output_eth_type = Signal(intbv(0)[16:])
output_eth_payload_tdata = Signal(intbv(0)[64:])
output_eth_payload_tkeep = Signal(intbv(0)[8:])
output_eth_payload_tvalid = Signal(bool(0))
output_eth_payload_tlast = Signal(bool(0))
output_eth_payload_tuser = Signal(bool(0))
busy = Signal(bool(0))
frame_error = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = eth_ep.EthFrameSink(clk,
rst,
eth_hdr_ready=output_eth_hdr_ready,
eth_hdr_valid=output_eth_hdr_valid,
eth_dest_mac=output_eth_dest_mac,
eth_src_mac=output_eth_src_mac,
eth_type=output_eth_type,
eth_payload_tdata=output_eth_payload_tdata,
eth_payload_tkeep=output_eth_payload_tkeep,
eth_payload_tvalid=output_eth_payload_tvalid,
eth_payload_tready=output_eth_payload_tready,
eth_payload_tlast=output_eth_payload_tlast,
eth_payload_tuser=output_eth_payload_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_eth_axis_rx_64(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_valid,
output_eth_hdr_ready,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tready,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
output_eth_hdr_ready.next = True
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame.build_axis())
yield clk.posedge
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source 2")
current_test.next = 7
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink 2")
current_test.next = 8
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1.build_axis())
source_queue.put(test_frame2.build_axis())
yield clk.posedge
while input_axis_tvalid or output_eth_payload_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 9: tuser assert")
current_test.next = 9
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
axi_frame = test_frame.build_axis()
axi_frame.user = 1
source_queue.put(axi_frame)
yield clk.posedge
yield output_eth_payload_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
assert rx_frame.payload.user[-1]
yield delay(100)
yield clk.posedge
print("test 10: truncated packet")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame()
test_frame.data = bytearray(b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09')
source_queue.put(test_frame)
yield clk.posedge
yield input_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
assert frame_error
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_eth_axis_rx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_eth_hdr_ready = 0;
reg output_eth_payload_tready = 0;
// Outputs
wire input_axis_tready;
wire output_eth_hdr_valid;
wire [47:0] output_eth_dest_mac;
wire [47:0] output_eth_src_mac;
wire [15:0] output_eth_type;
wire [63:0] output_eth_payload_tdata;
wire [7:0] output_eth_payload_tkeep;
wire output_eth_payload_tvalid;
wire output_eth_payload_tlast;
wire output_eth_payload_tuser;
wire busy;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_eth_hdr_ready,
output_eth_payload_tready);
$to_myhdl(input_axis_tready,
output_eth_hdr_valid,
output_eth_dest_mac,
output_eth_src_mac,
output_eth_type,
output_eth_payload_tdata,
output_eth_payload_tkeep,
output_eth_payload_tvalid,
output_eth_payload_tlast,
output_eth_payload_tuser,
busy,
frame_error);
// dump file
$dumpfile("test_eth_axis_rx_64.lxt");
$dumpvars(0, test_eth_axis_rx_64);
end
eth_axis_rx_64
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// Ethernet frame output
.output_eth_hdr_valid(output_eth_hdr_valid),
.output_eth_hdr_ready(output_eth_hdr_ready),
.output_eth_dest_mac(output_eth_dest_mac),
.output_eth_src_mac(output_eth_src_mac),
.output_eth_type(output_eth_type),
.output_eth_payload_tdata(output_eth_payload_tdata),
.output_eth_payload_tkeep(output_eth_payload_tkeep),
.output_eth_payload_tvalid(output_eth_payload_tvalid),
.output_eth_payload_tready(output_eth_payload_tready),
.output_eth_payload_tlast(output_eth_payload_tlast),
.output_eth_payload_tuser(output_eth_payload_tuser),
// Status signals
.busy(busy),
.frame_error(frame_error)
);
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
module = 'eth_axis_tx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_axis_tx(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata,
input_eth_payload_tvalid=input_eth_payload_tvalid,
input_eth_payload_tready=input_eth_payload_tready,
input_eth_payload_tlast=input_eth_payload_tlast,
input_eth_payload_tuser=input_eth_payload_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
busy=busy)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:0])
input_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[8:])
input_eth_payload_tvalid = Signal(bool(0))
input_eth_payload_tlast = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
input_eth_hdr_ready = Signal(bool(0))
input_eth_payload_tready = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = eth_ep.EthFrameSource(clk,
rst,
eth_hdr_ready=input_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
eth_payload_tdata=input_eth_payload_tdata,
eth_payload_tvalid=input_eth_payload_tvalid,
eth_payload_tready=input_eth_payload_tready,
eth_payload_tlast=input_eth_payload_tlast,
eth_payload_tuser=input_eth_payload_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_eth_axis_tx(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tdata,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame)
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield output_axis_tlast.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source 2")
current_test.next = 7
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink 2")
current_test.next = 8
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 9: tuser assert")
current_test.next = 9
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame.payload.user = 1
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
assert rx_frame.user[-1]
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_eth_axis_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [7:0] input_eth_payload_tdata = 0;
reg input_eth_payload_tvalid = 0;
reg input_eth_payload_tlast = 0;
reg input_eth_payload_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_eth_payload_tready;
wire input_eth_hdr_ready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tvalid,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tready);
$to_myhdl(input_eth_hdr_ready,
input_eth_payload_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_eth_axis_tx.lxt");
$dumpvars(0, test_eth_axis_tx);
end
eth_axis_tx
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata),
.input_eth_payload_tvalid(input_eth_payload_tvalid),
.input_eth_payload_tready(input_eth_payload_tready),
.input_eth_payload_tlast(input_eth_payload_tlast),
.input_eth_payload_tuser(input_eth_payload_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status signals
.busy(busy)
);
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
module = 'eth_axis_tx_64'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_axis_tx_64(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_eth_hdr_valid=input_eth_hdr_valid,
input_eth_hdr_ready=input_eth_hdr_ready,
input_eth_dest_mac=input_eth_dest_mac,
input_eth_src_mac=input_eth_src_mac,
input_eth_type=input_eth_type,
input_eth_payload_tdata=input_eth_payload_tdata,
input_eth_payload_tkeep=input_eth_payload_tkeep,
input_eth_payload_tvalid=input_eth_payload_tvalid,
input_eth_payload_tready=input_eth_payload_tready,
input_eth_payload_tlast=input_eth_payload_tlast,
input_eth_payload_tuser=input_eth_payload_tuser,
output_axis_tdata=output_axis_tdata,
output_axis_tkeep=output_axis_tkeep,
output_axis_tvalid=output_axis_tvalid,
output_axis_tready=output_axis_tready,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
busy=busy)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:0])
input_eth_hdr_valid = Signal(bool(0))
input_eth_dest_mac = Signal(intbv(0)[48:])
input_eth_src_mac = Signal(intbv(0)[48:])
input_eth_type = Signal(intbv(0)[16:])
input_eth_payload_tdata = Signal(intbv(0)[64:])
input_eth_payload_tkeep = Signal(intbv(0)[8:])
input_eth_payload_tvalid = Signal(bool(0))
input_eth_payload_tlast = Signal(bool(0))
input_eth_payload_tuser = Signal(bool(0))
output_axis_tready = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[64:])
output_axis_tkeep = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
input_eth_hdr_ready = Signal(bool(1))
input_eth_payload_tready = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
sink_pause = Signal(bool(0))
source = eth_ep.EthFrameSource(clk,
rst,
eth_hdr_ready=input_eth_hdr_ready,
eth_hdr_valid=input_eth_hdr_valid,
eth_dest_mac=input_eth_dest_mac,
eth_src_mac=input_eth_src_mac,
eth_type=input_eth_type,
eth_payload_tdata=input_eth_payload_tdata,
eth_payload_tkeep=input_eth_payload_tkeep,
eth_payload_tvalid=input_eth_payload_tvalid,
eth_payload_tready=input_eth_payload_tready,
eth_payload_tlast=input_eth_payload_tlast,
eth_payload_tuser=input_eth_payload_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tkeep=output_axis_tkeep,
tvalid=output_axis_tvalid,
tready=output_axis_tready,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
pause=sink_pause,
name='sink')
# DUT
dut = dut_eth_axis_tx_64(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_hdr_ready,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tready,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tready,
output_axis_tlast,
output_axis_tuser,
busy)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
print("test 1: test packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: longer packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: test packet with pauses")
current_test.next = 3
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(256))
source_queue.put(test_frame)
yield delay(64)
yield clk.posedge
sink_pause.next = True
yield delay(32)
yield clk.posedge
sink_pause.next = False
yield delay(64)
yield clk.posedge
source_pause.next = True
yield delay(32)
yield clk.posedge
source_pause.next = False
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets")
current_test.next = 4
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield output_axis_tlast.posedge
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alternate pause source")
current_test.next = 5
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alternate pause sink")
current_test.next = 6
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(32))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(32))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 7: alternate pause source 2")
current_test.next = 7
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 8: alternate pause sink 2")
current_test.next = 8
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(33))
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(33))
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
yield clk.posedge
while input_eth_payload_tvalid or output_axis_tvalid:
sink_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = False
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 9: tuser assert")
current_test.next = 9
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
test_frame.payload.user = 1
source_queue.put(test_frame)
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
check_frame = eth_ep.EthFrame()
check_frame.parse_axis(rx_frame)
assert check_frame == test_frame
assert rx_frame.user[-1]
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

113
tb/test_eth_axis_tx_64.v Normal file
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@ -0,0 +1,113 @@
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_eth_axis_tx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_eth_hdr_valid = 0;
reg [47:0] input_eth_dest_mac = 0;
reg [47:0] input_eth_src_mac = 0;
reg [15:0] input_eth_type = 0;
reg [63:0] input_eth_payload_tdata = 0;
reg [7:0] input_eth_payload_tkeep = 0;
reg input_eth_payload_tvalid = 0;
reg input_eth_payload_tlast = 0;
reg input_eth_payload_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_eth_payload_tready;
wire input_eth_hdr_ready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_eth_hdr_valid,
input_eth_dest_mac,
input_eth_src_mac,
input_eth_type,
input_eth_payload_tdata,
input_eth_payload_tkeep,
input_eth_payload_tvalid,
input_eth_payload_tlast,
input_eth_payload_tuser,
output_axis_tready);
$to_myhdl(input_eth_hdr_ready,
input_eth_payload_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
busy);
// dump file
$dumpfile("test_eth_axis_tx_64.lxt");
$dumpvars(0, test_eth_axis_tx_64);
end
eth_axis_tx_64
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.input_eth_hdr_valid(input_eth_hdr_valid),
.input_eth_hdr_ready(input_eth_hdr_ready),
.input_eth_dest_mac(input_eth_dest_mac),
.input_eth_src_mac(input_eth_src_mac),
.input_eth_type(input_eth_type),
.input_eth_payload_tdata(input_eth_payload_tdata),
.input_eth_payload_tkeep(input_eth_payload_tkeep),
.input_eth_payload_tvalid(input_eth_payload_tvalid),
.input_eth_payload_tready(input_eth_payload_tready),
.input_eth_payload_tlast(input_eth_payload_tlast),
.input_eth_payload_tuser(input_eth_payload_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status signals
.busy(busy)
);
endmodule