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Fix organization
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@ -69,6 +69,8 @@ reg s_axis_cq_tlast = 0;
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reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
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reg s_axis_cq_tvalid = 0;
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reg m_axis_cc_tready = 0;
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reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num = 0;
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reg s_axis_rq_seq_num_valid = 0;
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reg [1:0] pcie_tfc_nph_av = 0;
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reg [1:0] pcie_tfc_npd_av = 0;
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reg [2:0] cfg_max_payload = 0;
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@ -127,8 +129,6 @@ wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep;
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wire m_axis_cc_tlast;
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wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser;
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wire m_axis_cc_tvalid;
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reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num = 0;
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reg s_axis_rq_seq_num_valid = 0;
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wire [18:0] cfg_mgmt_addr;
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wire cfg_mgmt_write;
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wire [31:0] cfg_mgmt_write_data;
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@ -69,6 +69,8 @@ reg s_axis_cq_tlast = 0;
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reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
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reg s_axis_cq_tvalid = 0;
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reg m_axis_cc_tready = 0;
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reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num = 0;
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reg s_axis_rq_seq_num_valid = 0;
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reg [1:0] pcie_tfc_nph_av = 0;
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reg [1:0] pcie_tfc_npd_av = 0;
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reg [2:0] cfg_max_payload = 0;
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@ -127,8 +129,6 @@ wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep;
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wire m_axis_cc_tlast;
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wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser;
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wire m_axis_cc_tvalid;
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reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num = 0;
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reg s_axis_rq_seq_num_valid = 0;
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wire [18:0] cfg_mgmt_addr;
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wire cfg_mgmt_write;
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wire [31:0] cfg_mgmt_write_data;
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